You may need to enable or update / install Adobe Flash Player Plug-in to display JPE e-Book in your device properly. If you use Google Chrome, please find information here > Archives > Current Issues JPE, Vol. 18, No. 2, March 2018 Development of a Switched Diode Asymmetric Multilevel Inverter Topology D. Karthikeyan, Vijayakumar Krishnaswamy, and Mohd. Ali Jagabar Sathik Area High Power Converters Abstract This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup. Keyword Asymmetric cascaded multilevel inverter,Nearest level modulation,Reduced switches,Total harmonic distortion PDF Full-text