A Hybrid Modular Multilevel Converter Topology with an Improved Nearest Level Modulation Method


Vol. 17, No. 1, pp. 96-105, Jan. 2017
10.6113/JPE.2019.17.1.96


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 Abstract

In this paper, a hybrid modular multilevel converter (MMC) topology with an improved nearest level modulation method is proposed for medium-voltage high-power applications. The arm of the proposed topology contains N series connected half-bridge submodules (HBSMs), one full-bridge submodule (FBSM) and an inductor. By exploiting the FBSM, half-level voltages are obtained in the arm voltages. Therefore, an output voltage with a 2N+1 level number can be generated. Moreover, the total level number of the inserted submodules (SMs) is a constant. Thus, there is no pulse voltage across the arm inductors, and the SM capacitor voltage is rated. With the proposed voltage balancing method, the capacitor voltage of the HBSM is twice the voltage of the FBSM, and each IGBT of the FBSM has a relatively low switching frequency and an equalized conduction loss. The capacitor voltage balancing methods of the two kinds of SMs are implemented independently. As a result, the switching frequency of the HBSM is not increased compared to the conventional MMC. In addition, according to a theoretical calculation of the total harmonic distortion of the electromotive force (EMF), the voltage quality with the presented method can be significantly enhanced when the SM number is relatively small. Simulation and experimental results obtained with a MMC-based inverter verify the validity of the developed method.


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Cite this article

[IEEE Style]

J. Wang, X. Han, H. Ma, Z. Bai, "A Hybrid Modular Multilevel Converter Topology with an Improved Nearest Level Modulation Method," Journal of Power Electronics, vol. 17, no. 1, pp. 96-105, 2017. DOI: 10.6113/JPE.2019.17.1.96.

[ACM Style]

Jun Wang, Xu Han, Hao Ma, and Zhihong Bai. 2017. A Hybrid Modular Multilevel Converter Topology with an Improved Nearest Level Modulation Method. Journal of Power Electronics, 17, 1, (2017), 96-105. DOI: 10.6113/JPE.2019.17.1.96.