Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids

Kai Li; An Bo; Hong Zheng; Ningbo Sun

Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids

Vol. 17, No. 1, pp. 262-271, Jan. 2017

10.6113/JPE.2019.17.1.262

Distorted grid

Small-signal model

Three-phase phase-locked loop

Unbalanced grid

PDF

Abstract

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

Statistics

Show / Hide Statistics

Cumulative Counts from September 30th, 2019
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.

Cite this article

[IEEE Style]

K. Li, A. Bo, H. Zheng, N. Sun, "Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids," Journal of Power Electronics, vol. 17, no. 1, pp. 262-271, 2017. DOI: 10.6113/JPE.2019.17.1.262.

[ACM Style]

Kai Li, An Bo, Hong Zheng, and Ningbo Sun. 2017. Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids. Journal of Power Electronics, 17, 1, (2017), 262-271. DOI: 10.6113/JPE.2019.17.1.262.