Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

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Cite this article

[IEEE Style]

A. S. Hayder, Y. Park, S. Kim, Y. Pu, S. Yoo, Y. Yang, M. Lee, K. C. Hwang, K. Lee, "Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process," Journal of Power Electronics, vol. 17, no. 3, pp. 821-834, 2017. DOI: 10.6113/JPE.2019.17.3.821.

[ACM Style]

Abbas Syed Hayder, Young-Jun Park, SangYun Kim, Young-Gun Pu, Sang-Sun Yoo, Youngoo Yang, Minjae Lee, Keum Choel Hwang, and Kang-Yoon Lee. 2017. Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process. Journal of Power Electronics, 17, 3, (2017), 821-834. DOI: 10.6113/JPE.2019.17.3.821.