Verification of an Autonomous Decentralized UPS System with Fast Transient Response Using a FPGA-Based Hardware Controller


Vol. 9, No. 3, pp. 507-515, May  2009
10.6113/JPE.2009.9.3.507


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 Abstract

This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.


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Cite this article

[IEEE Style]

T. Yokoyama, N. Doi, T. Ishioka, "Verification of an Autonomous Decentralized UPS System with Fast Transient Response Using a FPGA-Based Hardware Controller," Journal of Power Electronics, vol. 9, no. 3, pp. 507-515, 2009. DOI: 10.6113/JPE.2009.9.3.507.

[ACM Style]

Tomoki Yokoyama, Nobuaki Doi, and Toshiya Ishioka. 2009. Verification of an Autonomous Decentralized UPS System with Fast Transient Response Using a FPGA-Based Hardware Controller. Journal of Power Electronics, 9, 3, (2009), 507-515. DOI: 10.6113/JPE.2009.9.3.507.