Design and Implementation of a Multi Level Three-Phase Inverter with Less Switches and Low Output Voltage Distortion

Mahrous E. Ahmed; Saad Mekhilef

Design and Implementation of a Multi Level Three-Phase Inverter with Less Switches and Low Output Voltage Distortion

Mahrous E. Ahmed

Saad Mekhilef

Vol. 9, No. 4, pp. 593-603, Jul. 2009

10.6113/JPE.2009.9.4.593

Two-level inverter

Multi level inverter

Total harmonic distortion

Three level output waveform inverter

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Abstract

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.

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Cite this article

[IEEE Style]

M. E. Ahmed and S. Mekhilef, "Design and Implementation of a Multi Level Three-Phase Inverter with Less Switches and Low Output Voltage Distortion," Journal of Power Electronics, vol. 9, no. 4, pp. 593-603, 2009. DOI: 10.6113/JPE.2009.9.4.593.

[ACM Style]

Mahrous E. Ahmed and Saad Mekhilef. 2009. Design and Implementation of a Multi Level Three-Phase Inverter with Less Switches and Low Output Voltage Distortion. Journal of Power Electronics, 9, 4, (2009), 593-603. DOI: 10.6113/JPE.2009.9.4.593.