Analysis and Implementation of a New Three-Level Converter

Vol. 14, No. 3, pp. 478-487, May  2014



This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at Vin/2. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.

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Cite this article

[IEEE Style]

B. Lin and Y. Nian, "Analysis and Implementation of a New Three-Level Converter," Journal of Power Electronics, vol. 14, no. 3, pp. 478-487, 2014. DOI: 10.6113/JPE.2014.14.3.478.

[ACM Style]

Bor-Ren Lin and Yu-Bin Nian. 2014. Analysis and Implementation of a New Three-Level Converter. Journal of Power Electronics, 14, 3, (2014), 478-487. DOI: 10.6113/JPE.2014.14.3.478.