A Canonical Small-Signal Linearized Model and a Performance Evaluation of the SRF-PLL in Three Phase Grid Inverter System


Vol. 14, No. 5, pp. 1057-1068, Sep. 2014
10.6113/JPE.2014.14.5.1057


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 Abstract

Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-usedfor grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they arenonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed inthis paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang,bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of aSRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although theproposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.


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Cite this article

[IEEE Style]

P. Mao, M. Zhang, W. Zhang, "A Canonical Small-Signal Linearized Model and a Performance Evaluation of the SRF-PLL in Three Phase Grid Inverter System," Journal of Power Electronics, vol. 14, no. 5, pp. 1057-1068, 2014. DOI: 10.6113/JPE.2014.14.5.1057.

[ACM Style]

Peng Mao, Mao Zhang, and Weiping Zhang. 2014. A Canonical Small-Signal Linearized Model and a Performance Evaluation of the SRF-PLL in Three Phase Grid Inverter System. Journal of Power Electronics, 14, 5, (2014), 1057-1068. DOI: 10.6113/JPE.2014.14.5.1057.