Non‑isolated input‑series–output‑parallel three‑level buck converter

Jianfei Chen; Chen Duan; Caisheng Wang

Non‑isolated input‑series–output‑parallel three‑level buck converter

Jianfei Chen

Chen Duan

Caisheng Wang

Vol. 20, No. 1, pp. 1-10, Jan. 2020

10.1007/s43236-019-00005-6

Abstract

This paper proposes a non-isolated input-series–output-parallel (ISOP) three-level buck converter. A theoretical analysis indicates that it has a large step-down ratio and low component voltage stress with the input and output terminals sharing the same ground. An automatic current-balancing mechanism is revealed, and it indicates that the parasitic parameters and inductance variations influence the automatic current-balancing effect. Thus, current-balance control is necessary. Considering that the proposed topology has an ISOP configuration, two voltage-balance control strategies are proposed to realize input capacitor voltage balancing and output inductor current balancing. One is implemented based on a two-loop configuration with an output voltage loop and a voltage-balance loop. The other is developed based on a three-loop configuration by adding one inner current loop on the two-loop configuration. Finally, experimental results have been given to verify both the proposed converter and voltage-balance control.

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Cite this article

[IEEE Style]

J. Chen, C. Duan, C. Wang, "Non‑isolated input‑series–output‑parallel three‑level buck converter," Journal of Power Electronics, vol. 20, no. 1, pp. 1-10, 2020. DOI: 10.1007/s43236-019-00005-6.

[ACM Style]

Jianfei Chen, Chen Duan, and Caisheng Wang. 2020. Non‑isolated input‑series–output‑parallel three‑level buck converter. Journal of Power Electronics, 20, 1, (2020), 1-10. DOI: 10.1007/s43236-019-00005-6.