Complete loss distribution model of GaN HEMTs considering the influence of parasitic parameters


Vol. 24, No. 1, pp. 119-129, Jan. 2024
10.1007/s43236-023-00710-3




 Abstract

When compared with Si-based devices, Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) possess the advantages of lower junction-to-case thermal resistance, smaller on-state resistance, faster switching velocity, and higher switching frequency. These advantages make them a promising power semiconductor device. However, with the enhancement of switching frequencies, the influence of parasitic parameters on switching ringing and the losses of GaN HEMTs are increasingly severe. Thus, it is necessary to predict the loss distribution by establishing an accurate loss model of the switching process. On the premise of considering parasitic inductance, nonlinear junction capacitance, and reverse transfer characteristics, this article proposes a precise switching loss model of GaN HEMTs to predict the loss distribution in the switching process. In addition, it verifies results based on the double pulse test (DPT) circuit, which validates the accuracy of the proposed model. Ultimately, based on the above-mentioned loss model, this article discussed the influence of parasitic capacitance and inductance on the output capacitance loss (Eqoss), the reverse conduction loss (ESD), the opening V-I overlap loss (Eopen), the closing V-I overlap loss (Eclose), and the total loss (Etotal). Then, this article produces an optimizing method to enhance the conversion efficiency of GaN HEMTs in accordance with laboratory findings.


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Cite this article

[IEEE Style]

S. Gao, J. Tian, X. Fu, Y. Li, B. Wang, L. Zhao, "Complete loss distribution model of GaN HEMTs considering the influence of parasitic parameters," Journal of Power Electronics, vol. 24, no. 1, pp. 119-129, 2024. DOI: 10.1007/s43236-023-00710-3.

[ACM Style]

Shengwei Gao, Jinrui Tian, Xiaoyu Fu, Yongxiao Li, Bo Wang, and Lixia Zhao. 2024. Complete loss distribution model of GaN HEMTs considering the influence of parasitic parameters. Journal of Power Electronics, 24, 1, (2024), 119-129. DOI: 10.1007/s43236-023-00710-3.