사각형입니다.

https://doi.org/10.6113/JPE.2018.18.1.11

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Analysis and Implementation of a New Single Switch, High Voltage Gain DC-DC Converter with a Wide CCM Operation Range and Reduced Components Voltage Stress


Babak Honarjoo*, Seyed M. Madani, Mehdi Niroomand*, and Ehsan Adib**


*,†Department of Electrical Engineering, University of Isfahan, Isfahan, Iran

**Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran



Abstract 

This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for renewable energy applications. The proposed converter is composed of a coupled inductor, a passive clamp circuit, a switched capacitor and voltage lift circuits. The passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The configuration of the passive clamp and switched capacitor circuit increases the voltage gain. A wide continuous conduction mode (CCM) operation range, a low turn ratio for the coupled inductor, low voltage stress on the switch, switch turn on under almost zero current switching (ZCS), low voltage stress on the diodes, leakage inductance energy recovery, high efficiency and a high voltage gain without a large duty cycle are the benefits of this converter. The steady state operation of the converter in the continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is discussed and analyzed. A 200W prototype converter with a 28V input and a 380V output voltage is implemented and tested to verify the theoretical analysis.


Key words: Coupled inductor, High step-up voltage gain, Single switch, Switched capacitor, Low voltage stress


Manuscript received Apr. 18, 2017; accepted Aug. 14, 2017

Recommended for publication by Associate Editor Chun-An Cheng.

Corresponding Author: madani104@yahoo.com  Tel: +98-31-37934547, Fax: +98-31-37933071 , University of Isfahan

*Dept. of Eng., Univ. of Isfahan, Iran

**Dept. of Electrical and Computer Eng., Isfahan Univ. of Tech., Iran



Ⅰ. INTRODUCTION

Environment pollution and the depletion of fossil fuels have pushed researchers to work on renewable energy sources, especially solar energy. The output voltage of solar panels is usually less than 50 volts. However, in order to inject power to the grid, the DC level must be stepped up to 380-400V DC for a full bridge inverter and 750-800V DC for a half bridge inverter. The series connection of photovoltaic (PV) panels is a solution to produce such high voltages. However, due to shading and panel mismatch, maximum power point tracking (MPPT) is not achieved which reduces the system efficiency. Moreover, in the case of panel failure, the entire panel set fails. For these reasons, paralleling PV panels is a better choice. On the other hand, in low power applications, it is possible to use only one panel. In such cases, a DC-DC boost converter is needed to increase the DC voltage of the PV panel. DC-DC boost converters are categorized into isolated and non-isolated types. The efficiency of isolated converters is less than that of non-isolated converters, since all of the input power is transmitted via magnetic coupling. Moreover, a large winding turn ratio of the transformer in an isolated converter increases the winding parasitic capacitors and transformer leakage inductance, which results in oscillations and increased losses and electromagnetic interference (EMI) noise.

The conventional boost converter is the simplest topology of this type of converter. However, the gain and efficiency of this converter is limited because of its high conduction and switching losses due to the reverse-recovery of the output diodes and the larger conduction losses due to the applied high voltage switch.

To increase the voltage gain of a boost converter various techniques have been introduced. The voltage gain of a three-level boost converter is almost same as that of a conventional boost converter, and the voltage stress on the switches and output diodes is half the output voltage. However, the reverse recovery of the output diodes is still a problem. In cascade boost converters, the voltage gain is high and equal to the product of its stages. However, the second stage has high voltage stress on the switch and diode, which results in low efficiency, due to two stage power processing. In addition, using two magnetic cores and switches, and its instability issue are the disadvantages of this converter [1]. In quadratic boost converters [1], [2], the active switch of the first stage is replaced with a diode, which makes the circuit simpler. However, like cascade boost converters, on the second stage, the high voltage stress on the output diode and active switch is equal to the output voltage. The integration of a boost converter with another converter, such as flyback or SEPIC [1], [3], [4] has the following advantages: some of the elements such as the active switch or inductor are shared between two converters, both converter outputs are added together, and the boost converter section behaves like a clamping circuit. The switched capacitor [1] and voltage lift [5] techniques are appropriate for low power applications. Meanwhile, in high power applications, high transient current passes through the active switch which reduces efficiency. Using voltage multiplier cells in the boost converter [6]-[9] is suitable for moderate voltage gain applications, because for a high gain voltage, a high number of cells decreases efficiency. Using a switched inductor in a boost converter [10] is also not appropriate for high voltage gain and high power applications, because the conduction losses of the switched inductor diodes are high, and the voltage stress of the active switch and output diode is equal to the output voltage. In active network converters (ANC) [10], the diodes of the switched inductor are removed and an active switch is added. In this configuration, the voltage and current stress on the switches are reduced. However, the voltage gain is low and it needs two isolated gate pulses for its two switches. Three state switching cell (3SSC)-based converters [11] have a low input current ripple, where the current ripple frequency of the auto transformer and inductor is twice the switching frequency, which reduces the volume and weight of the magnetic elements. Due to the presence of an autotransformer with a unit turn ratio, there is good current sharing between the switches. Although these converters have a large number of component, they are suitable for high power applications.

In high step-up applications, boost converters with coupled-inductors are particularly important. There are three main advantage of these converters. 1) Their high voltage gain with a low operating duty cycle can be adjusted by a proper turn ratio of the coupled inductor. 2) Their switch voltage stress is low. Therefore, switches with a low Rds (on) and low conduction losses can be utilized. 3) Their secondary leakage inductance reduces the reverse recovery ringing of the output diode.

There are three disadvantage of converters with coupled inductors. 1) When the active switch is turned off, the stored energy in the leakage inductance causes a voltage spike across the switch. 2) Their input current ripple is high, especially with increments of the turn ratio. 3) Using a higher turn ratio to achieve a higher voltage gain causes higher parasitic winding capacitors and leakage inductance, which increase the losses and EMI noise.

To overcome the problem of leakage inductance energy, Resistor-Capacitor-Diode (RCD) snubber circuits, passive clamp circuits [12] and active clamp circuits [13] have been proposed. The RCD snubber suppresses switch voltage spikes. However, it wastes the leakage inductance energy in the RCD resistor, which reduces the efficiency. Unlike the RCD snubber, both active and passive clamp circuits recover the energy of the leakage inductance. In the active clamp circuit, the zero voltage switching (ZVS) conditions is provided for each of the switches, but at the cost of an additional switch with an isolated drive circuit, resulting in increased complexity of the converter. Passive clamp circuits have simpler structure and do not need additional switches. References [3], [14], [18], [20], [23], [25] employ output stacking techniques to directly transferred the leakage inductance energy of the coupled inductor to the output.

To achieve a high voltage gain, various technique have been applied on the coupled inductor. In [18], by using output stacking and a switched capacitor in the secondary of the coupled inductor, the winding number of the coupled inductor is decreased and the voltage gain and core utilization-factor is increased. The authors of [14] proposed a high voltage gain converter with a low input ripple current, which is suitable for high power applications. This converters uses two coupled inductors, interleaved switching, a voltage multiplier cell, output stacking and voltage lift techniques. The converter in [20] has less input current ripple and the same voltage gain when compared to the converter in [14]. However, it uses two inductors and one coupled inductor. The converter in [21] uses a coupled inductor and the switched-capacitor technique. In flyback mode when the switch is off, four capacitor are charged. In the forward mode when the switch is on, the capacitors, input source and secondary of the coupled inductor are in series and supply the load. However, the source current in this converter is discontinuous.

In [22] a passive clamp capacitor, which recycles the leakage inductance energy, in series with the secondary of the coupled-inductor charges a voltage-lift capacitor. This increases the voltage gain of the converter. Using the three-winding coupled-inductor in [25] offers a more flexible adjustment of the voltage conversion and less voltage stress on each diode. However, it is more complicated. In [26], using two coupled-inductors and a switched-capacitor cell, a high step-up Z-source converter was proposed. Compared with a boost converter, the Z-source converter has a higher voltage gain. The converter in [26] has a high voltage gain and voltage spike across the switch is clamped. However, the presence of a diode at the input and a high current section cause losses which decreases efficiency. The converter in [27] has a three-winding coupled-inductor and an isolated- gate driver for the switch, which makes it complicated. The authors of [28] proposed a high step up converter using an active network, a three-winding coupled-inductor and a switched-capacitor cell. The active network reduces the voltage and current stress on the active switches and increases the voltage gain. This converter is complicated, due to the three-winding coupled-inductor and the two active switches with isolated gate drives.

The authors of [23], [24] proposed a cascade coupled inductor with a boost converter, which achieved a low input ripple current and a high voltage gain. However, like quadratic boost converters, due to the two power processing stages in the high current section, the efficiency is reduced. In addition, these converters use two magnetic cores which increase the volume.

In this paper a high voltage gain converter using a boost coupled inductor with a passive clamp circuit is proposed that utilizes the switched capacitor and the voltage lift technique to further increase the voltage gain. The configuration of the passive clamp and switched capacitor circuit increase the voltage gain. A high voltage gain without a large duty cycle, a high conversion ratio, a wide CCM operation, low voltage stress on the switch, switch turn on under almost ZCS, low voltage stress on the output diode, leakage inductance energy recovery and high efficiency are the benefits of this converter.



Ⅱ. OPERATING PRINCIPLE OF THE PROPOSED CONVERTER

Fig. 1 shows the circuit configuration of the proposed converter. The coupled inductor is shown with its equivalent circuit including an ideal transformer, the magnetizing inductance Lm and the leakage inductance Llk. NP and NS are the number of primary and secondary winding turns of an ideal transformer, respectively. C1 is a clamp capacitor, C3, C4, C5 are switched capacitors, C2 is a voltage lift capacitor, and CO is an output capacitor. D1 is a clamp diode, DO is the output diode and D2, D3, D4, D5 are blocking diodes. The semiconductor elements are assumed to be ideal. The coupling coefficient is represented by k=Lm/(Lm+Llk ), and n=NS/NP is the ideal transformer turn ratio.


A. Continuous Conduction Mode (CCM) Operation

There are five operating modes in one switching cycle of the proposed converter. Fig. 2 represents theoretical waveforms of the proposed converter at the CCM operation.


1) Mode I [t0-t1]: Fig. 3(a)

Before t0, the switch S is off and the diodes D3, D4, Do are conducting. At t0, the switch S is turned on. The primary side current of the coupled inductor iLlk increases linearly until it reaches the magnetizing inductor current iLm at t1. During this time interval the difference between iLm and iLlk (iLm-iLlk) flows through the primary side of the ideal transformer T1. The current of T1’s secondary is equal to n(iLm-iLlk) which decreases linearly until it reaches zero at t1. The currents of D3, D4, Do decrease linearly and reach zero at t1. Therefore, the reverse recovery problems of these diodes are alleviated. In addition, S1 turns on under almost ZCS.


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Fig. 1. Circuit configuration of the proposed converter.


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Fig. 2. Theoretical waveforms of the proposed converter at the CCM.


2) Mode II [t1-t2]: Fig. 3(b)

At t1, iLlk is equal to iLm. Therefore, the magnetizing inductance Lm begins to absorb energy from Vin. The current and voltage direction in the primary and secondary side of T1 are reversed. Diodes D2, D5 begin to conduct. In this mode, the voltage lift capacitor C2 is charged via the clamp capacitor C1, the switched capacitor C3 and the secondary side of T1. Moreover, the switched capacitor C5 is charged via the switched capacitor C4 and the secondary side of T1.


Fig. 3. Current path of the operating modes during one switching cycle in the CCM operation: (a) Mode I; (b) Mode II; (c) Mode III; (d) Mode IV; (e) Mode V.

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(a)

 

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(b)

 

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(c)

 

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(d)

 

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(e)


3) Mode III [t2-t3]: Fig. 3(c)

At t2, switch S is turned off. Diode D1 conducts and transfers the energy of the leakage inductance Llk to the clamp capacitor C1. Therefore, the voltage of the switch clamps to VC1. In addition, a part of the magnetizing inductance energy is absorbed by this capacitor in the next mode, which is used to charge the capacitor C2. In this mode, iLlk is greater than iLm, and iLlk-iLm flows through the primary side of T1. Lm still absorbs energy and the polarity of the T1 voltage has not changed yet. Therefore, the difference of C1 in series with the primary side of the T1 voltages and the input source voltage are imposed to Llk and force iLlk to decreases rapidly to iLm at t3. The currents of the T1 secondary side and the diodes D2, D5 decline and reach zero at t3.


4) Mode IV [t3-t4]: Fig 3(d)

In this mode, the current of the leakage inductance iLlk is less than the current of the magnetizing inductance iLm. Therefore, the current direction and voltage polarity of the T1 primary and secondary are reversed. The diodes D3, D4, DO conduct and their currents increase. In this mode, D1 still conducts and the reduction rate of its current is less than that of the previous mode, because the T1 voltage polarity is reversed. At t4, iLlk reaches iDO and the diode D1 turns off.


5) Mode V [t4-t5]: Fig. 3(e)

During this time interval, the energy of the magnetizing inductance Lm, leakage inductance Llk and input source Vin along with C2 and C5 is delivered to the load R. In addition, the switched capacitors C3, C4 are charged. In this mode C1, C5 are discharged. This mode ends at t5 when S is turned on and the next switching period starts.


B. Discontinuous Conduction Mode (DCM) Operation

Since the leakage inductance is very small, its voltage drop can be neglected when compared to the voltage across Lm. Therefore, the leakage inductance is ignored in these models. 

Fig. 4 shows theoretical-waveforms during the three major operating modes in the DCM. Fig. 5 shows the current flow paths for theses modes.


1) Mode I [t0-t1]: Fig. 4(a)

At t0, the switch S is turned on. The magnetizing inductance Lm absorbs energy from the source and its current increases linearly from zero. Simultaneously, the coupled inductor is in forward operation and transfers a part of the source (Vin ) energy to the capacitors C2 and C5. This mode ends at t1 when S is turned off.


2) Mode II [t1-t2]: Fig. 4(b)

In this mode, S is off. The energy of Lm is transferred to the capacitors C1, C3, C4, Co and the load R. The capacitors C2 and C5 are in series with the source and Lm, and give their energy to CO and the load R. This mode ends at t=t2 when Lm is discharged.


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Fig. 4. Theoretical waveforms of the proposed converter at the DCM operation.


Fig. 5. Current flowing path of operating modes during one switching cycle at DCM operation. (a) Mode I. (b) Mode II. (c) Mode III.

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(a)

 

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(b)

 

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(c)


3) Mode III: [t2-t3] Fig. 4(c)

In this mode, the switch S remains off and the Lm current is zero. Therefore, the load R is supplied by CO.



Ⅲ. STEADY-STATE ANALYSIS OF THE PROPOSED CONVERTER

A. CCM Operation

Modes I and III are very short, and can be neglected in the calculation of the converter DC gain. In modes III and IV the energy of the leakage inductor Llk is released to the clamp capacitor C1. As shown in the appendix, the duty cycle of the charging clamp capacitor C1, if mode III is neglected, is:  

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where tc1 is the charging duration of C1, and Ts is the switching period. Applying the voltage-second balance principle on Llk and Lm yields:

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where k is the coupling-coefficient and it is equal to k=Lm/(Lm+Llk).

By using (2), (3) the voltage of the clamp capacitor C1 can be obtained as:

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Using (3), the voltage across the switched capacitors C3,C4 can be written as:

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Using (5), the voltages of the lifting capacitor C2 and the switched capacitor C5 are obtained as:

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The output voltage VO is given as:

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Substituting (3),(4),(6) and (7) into (8) results in the DC voltage gain MCCM as:

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Fig. 6 shows the voltage gain variations versus the duty ratio of the proposed converter, in the CCM operation for various coupling coefficient k=1, 0.95 and for n=1.5, 2, 3, 4. Fig. 6 concludes that the voltage gain is not sensitive to the coupling coefficient k.


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Fig. 6. Voltage gain versus duty ratio in the CCM operation for various value of n, k.


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Fig. 7. Voltage gain versus duty ratio of the proposed converter and the converters in [15]-[19] in the CCM operation when n=2.


For k=1 the ideal CCM voltage is:

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Fig. 7 shows variations of the CCM voltage gain versus the duty ratio of the proposed converter and the converters of [15]-[19] when k=1 and n=2.


The voltage stress of switch S and diodes D1, D2, D3, D4, D5, Do are:

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B. DCM Operation

In the previous section, while neglecting the leakage inductance, three major operational modes are described. According to Fig. 4 in mode I, following equations can be written:

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where ILmp is the peak value of Lm. Applying volt-second balance principle to Lm yields:

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where DL is the duty cycle of the conducting diode Do. Considering 그림입니다.
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Therefore, the secondary winding voltage in mode II is:

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According to Fig. 5(b) and using (19), (20) the following equations can be written:

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Writing the voltage equations for Fig. 5(a) and using (21), (22), VC2 and VC5 are obtained as:

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The output voltage is:

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Substituting (19), (20), (23) and (24) into (25) yields:

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Therefore:     

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As expressed in the Appendix, in the same way, in mode II the charges and conducting durations of D1, D3, D4, Do are equal. Therefore, the Do peak current is:

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Since the average current of DO is equal to the average current of the load:

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The normalized magnetizing inductor time constant is defined as: 

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Equations (17),(27)-(30) yields the dc gain of the proposed converter in the DCM:

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TABLE I  Comparison Among the Proposed Converter and Converters in [15]-[19] for k=1.

 

Converter
in [
15]

Converter
in [
16]

Converter
in [
17]

 

Converter
in [
18]

 

Converter
in [
19]

Proposed
converter

Voltage gain

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Voltage stress on switch

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The highest voltage stress on diodes

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Series elements between switch and clamp capacitor

1 diode

1 diode and 1 capacitor

1 diode

 

1 diode

 

2 diodes and 1 capacitor

1 diode

Quantities of diodes

4

4

6

 

6

 

5

6


C. BCM Condition

In the boundary condition mode (BCM), the voltage gains of the CCM and DCM operations are equal. From (14), (31), the boundary normalized magnetizing-inductor time-constant can be expressed as:

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The variation curve of  versus the duty cycle D, with n=2 for this converter and the converters of [15]-[19] are plotted in Fig. 8. For each converter, if τLm is greater than τLmB, that converter operate in the CCM. As this figure shows, the proposed converter has a wider CCM operational region than the converters presented in [15]-[19].

The comparison among the proposed converter and the converters in [15]-[19] are summarized in Table I. More series elements between the switch and the clamped capacitor increases the parasitic inductance and resistance, which results in a higher voltage spike across the switch. 


Ⅳ. DESIGN GUIDELINES AND EXPERIMENTAL RESULTS

To verify the theoretical analysis, a prototype converter with the specifications in Table II is designed and implemented.

The first step of the design is selecting the nominal full load duty cycle. A larger duty-cycle results in a higher voltage stress. On the other hand, a lower duty-cycle results in a higher rms (root-mean-square) current and conduction losses. An appropriate duty cycle selection is considered as D=0.6. According to the input and output voltage of the converter, and using equation (10), the turns ratio n is obtained. In this example, assuming D=0.6 results in n=1.3. Since the winding turn numbers N1 and N2 are small, n=1.5 is


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Fig. 8. Boundary condition of the proposed converter and converter in [15]-[19] under n=2.


TABLE II  The Prototype Specifications

Parameter

Value

Maximum output power

200W

Input DC voltage

28 V

Output DC voltage

380 V

Switching frequency

50 KHz


TABLE III  Component Specifications of the Prototype

Component

Specification

Power switch (MOSFET)

IRF4410

Schottky diode D1

MBR20100CT

Fast diodes D3,D4,D5

MUR 820

Fast diodes D2,Do

MUR 830

Coupled inductor

n=1:1.5 , Lm=80μH , Llk=.4μH

Capacitors C1,C3,C4

2*10μF, 100V, MKT

Capacitors C2, C5

10μF, 250V, MKT

Capacitor Co

220μF, 450V


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Fig. 9. Prototype of the proposed converter.


selected. Therefore, the theoretical duty cycle D=0.57 is yielded. In the next stage, the range of the converter CCM operation is selected, and by using (30) and (31), the value of Lm is obtained. In this example, the range of the CCM operation is chosen as 25%-100% full load. Therefore, Lm=83μH is yielded. The voltage stresses of the switch and diodes are obtained based on Equations (11)-(14). Equations (4)-(7) are used to obtain the voltage of the capacitors C1, C2, C3, C4, C5. Since the charges absorbed or produced by the capacitors C1, C2, C3, C4, C5 are all equal, the size of these capacitors are obtained as:

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where Io is the load current, Ts is the switching period, and r is the ripple factor of the capacitor voltage, which is equal to the ratio of the capacitor peak-to-peak ripple voltage to the capacitor average voltage. Vi is the average voltage of the capacitor. By choosing r=.01, the size of the capacitors are C1=16μF, C2=6.4μF, C3=C4=18.7μF, C5=10.4μF. Table III and Fig. 9 show the component specifications and a photo of the implemented converter, respectively.

Fig. 10 presents experimental results obtained with the converter under full load conditions. These waveforms confirm the steady-state operating modes of the converter. Fig. 10(a) shows the leakage inductance current iLlk and drain-source voltage of the switch Vds, which shows that the peak voltage Vds is limited to 85V.

Therefore, a MOSFET with a low withstand voltage and conduction losses can be used. Fig. 10(b) shows that the switch S turns on under almost ZCS. Fig 10(c) shows the switch S turn off interval, which is used to calculate switching turn off losses. Fig. 10(d) shows that after the switch turns off, the clamp diode D1 starts to conduct and the leakage inductor energy is released to the capacitor C1. The conduction time of D1 is consistent with (1). Figs. 10(e)-10(h) show that when the switch is on, D2 and D5 conduct and when it is off D3 and D4 conduct. Fig. 10(i) shows the input and output voltage of the converter. Fig. 11 shows the output voltage and output current when load steps up/down from Po=70W to a full load of Po=200W.

Table IV presents the measured DC voltage of the capacitors C1, C2, C3, C4, C5 in accordance with (4)-(7). These results show that the measured voltages of the capacitors are consistent with the theoretical calculations.

To estimate the efficiency of the converter under a full load, the conduction losses of the switch, diodes and coupled- inductor, as well as the turn on and turn off switching losses are estimated. Assuming that the initial efficiency is equal to 0.95, the RMS value of the input or switch current IDS-rms is approximately equal to:

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The resistance of IRF4410 in the on-state is 9mΩ. The total copper resistance transferred to the primary of the coupled-inductor is 35mΩ. Therefore, the switch and inductor conduction losses , are:

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The conduction losses of the diodes are almost equal to the multiplication of their average current and their forward voltage drop. The average current through the diodes Idiodes-avg is equal to the load current. By considering VD1=0.7V, VD3=VD4=VD5=0.94V and VD2=VDO=1.15V from the diode datasheets, the diodes conduction losses 그림입니다.
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The turn-on switching losses are due to the discharge of the switch output capacitor (Coss) during turn-on, and the overlap of the switch voltage and current during a switching interval. According to the data sheet of an IRF4410, at Vds=68V, the Coss discharged energy is 1µJ. Therefore, the switching turn on losses are:

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Using Fig. 10(b), the second term due to the overlap is: 

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Therefore, the total switch turn-on losses are equal to:

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According to Fig. 10(c), the turn off losses are:

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(a)

 

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(b)

 

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(c)

 

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(d)

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(e)

 

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(f)

 

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(g)

Fig. 10. Experimental result of the converter under full load conditions.

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(h)

 

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(i)


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Fig. 11. Load variation between Po=70W and a full-load of Po=200W.


TABLE IV  Measured and Estimated DC Voltage of the Capacitors C1, C2, C3, C4, C5, Co

Parameter

Vc1

Vc2

Vc3

Vc4

Vc5

Vco

Measured DC Voltage

68V

160V

57V

57V

95V

380V

Estimated DC Voltage

65V

163V

55V

55V

97V

380V


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Fig. 12. Measured efficiency under various output powers.


Therefore, the estimated efficiency at a full load is:

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The measured efficiency of the proposed converter is shown in Fig. 12. The maximum efficiency is 96.1%, which occurs at an output-power of 80W. The full load efficiency is 94.7%. The difference between the estimated efficiency (95.9%) and the measured efficiency (94.7%) at a full load is due to the core losses and other losses.



Ⅴ. CONCLUSIONS

This paper proposed a new high step up DC-DC converter. By using a coupled inductor and utilizing the switched capacitor and voltage lift techniques, a high voltage gain is achieved. In this converter, the energy of the leakage inductance is recycled via a passive clamp circuit and the switch peak voltage is limited at 85V. Therefore, a MOSFET with a low withstand voltage and low conduction losses can be utilized. The steady-state operation of the converter in the CCM and the DCM is analyzed and the boundary condition is calculated. It is shown that the proposed converter has a high voltage gain and a wide CCM operation range with a low turn-ratio coupled inductor. A laboratory prototype is implemented in the laboratory. The prototype verifies the theoretical analysis. Finally an analysis of the losses is carries out and the experimental efficiency is obtained.


APPENDIX: Dc1 CALCULATION

Dc1 is the conducting duty-cycle of the diode D1. To calculate Dc1, the ripple of the magnetizing inductor current ILm is neglected. In modes III and IV, the leakage inductor energy is released to the clamp capacitor C1. Since the interval of [t2-t3] is very short, it is neglected. In the [t3-t4] interval, the D1 current linearly decreases from iLm to zero. Therefore, the charge value of the capacitor C1 is:

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In steady-state operation, the charge balance principle yields:

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Thus, considering that the charging time of C3, C4 is equal to the discharging time of the capacitors C2, C5, the current of these the capacitors are equal:

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Therefore, in the [t4-t5] interval, the current of the capacitor C2 is equal to:

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During the [t3-t4] interval, the current of C2 increases from zero to iLm/(3n+1). Therefore, the total charge of C2 that discharges in the [t3-t5] interval is equal to:

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In steady-state operation, the charged and discharged charges of C1, C2 are equal (Qcharge = Qdischarge). Therefore, using (44), (46) and (50), Dc1 is obtain as:

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Babak Honarjoo was born in Isfahan, Iran, in 1976. He received his B.S. and M.S. degrees in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 1998 and 2001, respectively. He is presently working towards his Ph.D. degree in Electrical Engineering at the University of Isfahan, Isfahan, Iran. His current research interests include high step up DC-DC converters and multiport DC-DC converters.


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Seyed M. Madani received his B.S. degree from the Sharif University of Technology, Tehran, Iran, in 1989; his M.S. degree from the University of Tehran, Tehran, Iran, in 1991; and his Ph.D. degree from the Eindhoven University of Technology, Eindhoven, Netherlands, in 1999, all in Electrical Power Engineering. From 2000 to 2005, he was a Professor or Visiting Professor at Texas A&M University, College Station, Texas, USA; the University of Puerto Rico, Mayaguez, Puerto Rico; and the University of Wisconsin - Madison, Madison, WI, USA. From 2005 to 2011, he worked as an Assistant Professor at the Isfahan University of Technology, Isfahan, Iran. He is presently working as an Associate Professor at the University of Isfahan, Isfahan, Iran. He is also a Senior Member of the IEEE. His current research interests include  power electronics and electric drives.


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Mehdi Niroomand He was born in Isfahan, Iran, in 1979. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the Isfahan University of Technology (IUT), Isfahan, Iran, in 2001, 2004 and 2010, respectively. Since 2010, he has been with the Department of Electrical Engineering at the University of Isfahan, Isfahan, Iran, where he is presently working as an Assistant Professor. His current research interests include power electronics, uninterruptible power supplies, switching power supplies, control in power electronics and renewable energy.


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Ehsan Adib was born in Isfahan, Iran, in 1982. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 2003, 2006 and 2009, respectively. He is presently working as a Faculty Member in the Department of Electrical and Computer Engineering, Isfahan University of Technology. He is the author of more than 100 papers published in journals and conference proceedings. His current research interests include dc–dc converters and their applications, and soft-switching techniques. Dr. Adib was a recipient of the Best Ph.D. Dissertation Award from the IEEE Iran Section, in 2010.