https://doi.org/10.6113/JPE.2018.18.1.23

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

A SiC MOSFET Based High Efficiency Interleaved Boost Converter for More Electric Aircraft

Haider Zaman^†, Xiancheng Zheng^*, Mengxin Yang^*, Husan Ali^*, and Xiaohua Wu^*

^†,*School of Automation, Northwestern Polytechnical University, Xi’an, China

Abstract

Silicon Carbide (SiC) MOSFET belongs to the family of wide-band gap devices with inherit property of low switching and conduction losses. The stable operation of SiC MOSFET at higher operating temperatures has invoked the interest of researchers in terms of its application to high power density (HPD) power converters. This paper presents a performance study of SiC MOSFET based two-phase interleaved boost converter (IBC) for regulation of avionics bus voltage in more electric aircraft (MEA). A 450W HPD, IBC has been developed for study, which delivers 28V output voltage when supplied by 24V battery. A gate driver design for SiC MOSFET is presented which ensures the operation of converter at 250kHz switching frequency, reduces the miller current and gate signal ringing. The peak current mode control (PCMC) has been employed for load voltage regulation. The efficiency of SiC MOSFET based IBC converter is compared against Si counterpart. Experimentally obtained efficiency results are presented to show that SiC MOSFET is the device of choice under a heavy load and high switching frequency operation.

Key words: High Power Density (HPD), Interleaved Boost Converter (IBC), More Electrical Aircraft (MEA), Peak Current Mode Control (PCMC), Silicon Carbide (SiC)

Manuscript received Jun. 17, 2017; accepted Sep. 25, 2017

Recommended for publication by Associate Editor Joung-Hu Park.

^†Corresponding Author: hdrzaman@hotmail.com

Tel: +86-130-22995582, Northwestern Polytechnical University

^*School of Automation, Northwestern Polytechnical University, China

Ⅰ. INTRODUCTION

The aircraft industry has experienced rapid growth over the last few decades and by 2020 it is estimated that air traffic will grow 5% per year. Being one of the fossil fuel consumer, civil aviation emitted about 2% of all man-made CO₂ emissions [1]. For smooth operation, different systems of aircraft use electrical, hydraulic, mechanical and pneumatic energy. The current trend is to the replace subsystems consuming nonelectrical power, partially or wholly with electrical systems to improve the efficiency and emissions without compromising reliability. In traditional aircraft electrical power is primarily used for commercial loads and cabin de-icing, while in modern aircraft, for example the Boeing 787, the peak electrical power demand can go as high as 1000 KVA [2].

One of the major changes in the electric power system of commercial aircraft has been the replacement of the constant voltage and constant frequency electric power bus, with constant voltage and variable frequency bus. In traditional aircraft, integrated drive generators have been used to couple the jet engine to the main generator, to ensure a constant frequency i.e. 400Hz. However, in the latest commercial aircraft the integrated drive generator is eliminated and the main generator is directly coupled with the jet engine, generating ac voltage with a frequency that is proportional to the engine speed [3]. Loads that run on a DC or a constant frequency AC, require power electronic converters.

Fig. 1 shows the electrical power system of a modern more electric aircraft (MEA). Synchronous generators (SG) deliver power to the variable frequency, AC voltage bus by a 3-phase connection. In this kind of electrical system architecture, the main DC bus is regulated at 270V. The communications and navigation as well as the display and management of multiple systems are connected to a low voltage DC (LVDC 28V) bus. Further low voltages for signal processors and integrated circuits are obtained by stepping down the 28V.

The increasing demand for electrical power in aircraft systems, leads to the integration of hybrid energy sources i.e. fuel cells, solar panels and batteries. The hybridization of the ram air turbine by means of super-capacitors and Li-ion batteries are presented in [9], [10]. In [10], the architecture for interfacing a hybrid power source comprising a Li-ion battery and a fuel cell to the distribution bus of an aircraft. Despite the limited available surface area, solar powered aircrafts have also been investigated [7].

Fig. 1. Electrical power system of modern aircraft.

Power electronic devices have experienced rapid growth over the last five decades in terms of power handling capability. The current rating of 1.5 kA and voltage blocking capability of 6.5 kV have been achieved with silicon semiconductor [4]. However, these devices can only attain a few kHz of switching frequency. The demand for high voltage blocking capability, low switching losses and reduced converter volume enables the trend towards compound semiconductor materials including SiC and GaN [5]. Due to their attractive features such as a high electric break down field, low thermal impedance and saturated electron drift velocity, SiC devices are replacing their Si counterparts [6].

The size and weight of power electronic converters are important optimization parameters along with the electrical parameters when an aircraft is the target application [7]. A second generation SiC MOSFET can significantly reduce the cost, weight and volume of a converter by operating these devices at higher switching frequencies. The N-Channel enhancement mode SiC MOSFET among other available SiC transistors (BJT, JFET and IGBT) is highly compatible with the Si MOSFET [8]. Therefore, the replacement of a Si MOSFET with its SiC counterpart is growing exponentially.

In this paper, a performance study of a SiC MOSFET based two-phase interleaved boost (IBC) is presented. The converter is employed for the voltage regulation of a LVDC when supplied by 24V. The converter has been built with a second generation state of the art SiC MOSFET to achieve a high power density (HPD). SiC MOSFET based converters are mostly reported in high voltage applications. However, its stable operation at higher temperatures makes it a potential candidate for low voltage, HPD and particularly high temperature converters. To experimentally verify the potential of SiC MOSFETs, the efficiency of a SiC based IBC converter is measured at different switching frequency and load conditions. The gate drive circuit is a key part of the system design in the context of a SiC MOSFET because high dv/dt generates noise which has deleterious effect on the performance of the converter. The peak current mode controller (PCMC) has been employed due to its distinguishing features of inherent over-current protection, negligible steady state error and low power consumption. Furthermore, for a PCMC there is no need for expensive Hall voltage and current sensors. Instead it operates with a voltage divider circuit for voltage feedback and a sense resistor for inductor current feedback.

The rest of this paper is organized as follows. The operation of the two-phase IBC in the steady state condition is presented in section II. Section III proposes the gate driver circuit for SiC MOSFETs and recognizes the parameters for reducing the miller current and gate voltage oscillations. The PCMC for the two-phase IBC is introduced in section IV along with simulation results. Section V presents a comparison of the switching and conduction losses of a SiC MOSFET converter and a Si MOSFET based counterpart, to evaluate their efficiency. Finally, Section VI presents some conclusions.

Ⅱ. OPERATION OF A TWO-PHASE IBC

Two-phase IBC converters have some advantages over conventional boost DC-DC converters in terms of ripple cancellation, high reliability and filter size reduction [1], [2]. Furthermore, the IBC extends the power handling capability of the converter. Fig. 2(a) shows the IBC converter, which facilitates the power transfer from the low voltage side v_IN to a high voltage v_o. The two boost channels are formed by {S_{A_M}, S_{A’_D} and L_A} and {S_{B_M}, S_{B’_D} and L_B}. The switching signals u_A and u_B for triggering S_{A_M} and S_{B_M} are 180^o out of phase as shown in Fig. 2(b). In addition, the devices in the same phase leg (S_{A_M}, S_{A’_M} and S_{B_M}, S_{B’_M}) are triggered through complementary signals to protect the circuit from shoot-through. The interleaving reduces the input current (i_IN) ripple to half the inductor current (i_LA or i_LB) ripple. With SiC MOSFET the converter can achieve the objectives of high efficiency and small volume because of its high switching frequency. Furthermore, the bidirectional current flow through the MOSFET enables the converter to operate only in the continuous conduction mode [3].

The switching model of the two-phase IBC is presented as:

   (1)

Fig. 2. (a) Two-phase interleaved boost converter; (b) steady state waveform of the gate signals u_A and u_B, inductor currents i_LA and i_LB, input current i_IN, and sum of the channel currents i_d.

(a)

(b)

where x ={A,B} and v_o is the load voltage, and the notation ∑ helps to visualize the equation for the generic n-channel.

Ⅲ. GATE DRIVE CIRCUIT

The design of the gate drive circuit is primarily associated with reducing the switching losses and enabling high frequency operation of the converter at evaluated power densities [4]. However, at higher switching frequencies, while consuming the minimum power, the driver circuit must not be vulnerable to EMI (electromagnetic interference). SiC MOSFETs unlike Si MOSFETs have a smaller gate charge. Thus, they require a gate driver circuit capable of sink/source only low currents.

The proposed gate drive circuit is shown Fig. 3(a). The current flows through R_on, as shown in Fig. 3(b), and through R_off and D_off for the corresponding high and low level of signal u, respectively. The diode D_off route the gate drive current during the turn-off process to provide a lower impedance path, which accelerates the turn-off process as shown in Fig. 3(c). The turn-off time can be lowered by applying a negative gate-to-source turn-off voltage or by reducing the external gate resistance R_off.

Fig. 3. (a) SiC MOSFET gate drive circuit; (b) when u=1; (c) when u=0.

The intrinsic drain inductance along with the parasitic inductance between the positive voltage clamp and the drain terminal of the MOSFET can introduce a ringing of v_DS and an overshoot exceeding the steady state v_DS. To limit the gate voltage within an allowable range i.e. -10/25 V a clipper circuit formed by two zener diodes has been employed.

For the negative off-bias voltage (-5V), a zener diode with a parallel capacitor is employed in the gate current path. The capacitor charges to 5V during the on time of the MOSFET serving as the local storage, and during the off-time it is applied to the gate. This eliminates the need for a dedicated negative voltage supply. The value of the capacitor must be high enough to source the gate signal for the off period [5]. The negative bias voltage has a negligible effect on the turn-on process of a standalone SiC MOSFET. The only impact on the turn-on is a prolonged delay time, because of a larger voltage swing.

During the switching transient of the SiC MOSFET, high dv/dt across the other MOSFET in the same phase leg charges its drain-gate capacitance. This current flows through the parasitic gate-source capacitance C_GS and the turn-off gate resistor R_off. If the value of R_off is chosen so that the voltage drop is greater than the gate voltage threshold, a miss- triggering of the other device in the same phase can occur. This is known as a Miller turn-on. The intrinsic gate resistance is particularly important while choosing the R_off value to protect the MOSFET from a Miller turn-on. The conventional method to protect the MOSFET from a Miller turn-on is to add an external gate-source capacitance [6]. In addition, this external gate-source capacitance is also effective in suppressing resonance because of the stray inductance of the copper line and parasitic gate-source capacitance C_GS of the SiC MOSFET. However, increasing the value of the external gate-source capacitance increases the rise time of the gate voltage, which leads to increased switching losses [7]. The external gate-source capacitance is given as C_c in Table I, which shows the parameters of the gate drive circuit.

Fig. 4. (a) Gate signals ₍₁₎ v_GA, ₍₂₎ v_GB; (b) gate and drain voltage signals of the S_{A_M} MOSFET₍₁₎ v_GA, ₍₂₎ v_DA; (c) turn-on transient; (d) turn-off transient.

The drive circuit components optimized for the application under study are shown in Table I. The switching waveforms for the low-side MOSFETs S_{A_M} and S_{B_M} switched at 250kHz frequency are shown in Fig. 4(a) and 4(b), respectively. The time axis and voltage axis are 1µs/div and 10V/div, respectively. The switching time period and the time shift between u_A and u_B are 4µs and 2µs, respectively. Fig. 4(c) and 4(d) illustrate the gate voltage transition from on-to-off (-4V to +18V) and from off-to-on (+18V to -4V), respectively. The measured rise and fall time are 92ns and 105ns, respectively. 

Ⅳ. PCM CONTROL OF INTERLEAVED BOOST CONVERTER

The controller is responsible for shaping the loop transfer function to achieve a necessary transient response and to ensure the overall system stability [8], [9]. The peak current- mode control is characterized as a robust and wide-bandwidth controller for DC-DC converters having the inherent properties of over-current protection, negligible steady state error and low power consumption. PCMC is preferred over the average current-mode control in high frequency DC-DC converters with terminal voltages below 60V. The IBC converter suffers from poor dynamic performance due to the presence of non-minimum phase because of right hand zero (RHZ). This RHZ limits the closed loop bandwidth that causes slower converter dynamics.

TABLE I  Parameters of the Gate Drive Circuit

Parameters	Values
Ron	10Ω
Roff	5Ω
Dzp	24V
Dzn	5V
Cz	1µF

The PCM controller for the two-phase IBC converter is shown in Fig. 5(a). The voltage control loop compares the feedback load voltage v_o with the reference voltage V_ref,  and translates the voltage error into a control signal vc. The compensation network synthesized with R_CMP, C_CMP1 and C_CMP2 refered to as a type-II voltage controller sets the desired cross over frequency and phase margin.

A clock signal CLK initiates the switching cycle by driving the Set (S) input of the RS-Latch high, which turns-on the MOSFET S_{x_M}. The sensed inductor current R_si_Lx increases with a positive slope M₁, while S_{x_M} is conducting during the subinterval DT_s as shown in Fig. 5(b). The signal R_si_Lx is compared with the control voltage v_C using an analog comparator, which resets the latch when R_si_Lx ≥ vc. During the interval (1-D)T_s, S_{x‘_M} conducts and R_si_Lx decreases with a negative slope M₂. The switching frequency is determined by the clock time period, while the duty ratio D depends on the control signal vc.

The sense resistor R_s allows the inductor current to pass, which constraints its value, which limits the magnitude of the current feedback. The susceptibility to noise in the control signal is a major disadvantage of the peak current controller which restricts its application in ringing drain signal environments. In PCM operation, the latch is set by the clock signal while the reset signal is generated from the current comparator when the sensed inductor current becomes greater than the control signal. A noisy inductor current can reset the latch before the appropriate current relation becomes true, which disturbs the normal operation of the controller.

It has been reported that current loop is unstable for duty ratio of D > 0.5. This phenomenon is termed as subharmonic oscillation, and it can be observed from a varying switching pulse width. Further, the inductor current does not return to the value at the start of a cycle. This subharmonic oscillation can be suppressed and the converter can be stabilizes by adding a ramp signal to the sensed inductor current [20], [21]. In addition, an appropriate phase boost can reduce the vulnerability of the current controller to switching noise. However, this comes at the cost of reduced controller bandwidth or in other words a slower transient response. The tuning of the controller bandwidth is discussed in more detail in subsection B.

Fig. 5. (a) Peak current controller for two-phase IBC; (b) inductor current i_{LA and} i_LB waveforms of peak-current controlled IBC.

(a)

(b)

A. Interleaving of Two Phases

Fig. 6(a) shows the proposed gate signal generator for two channels using a single clock CLK of a 50% duty cycle. The gate signal generator for both channels are the same except that the gate signal generator for channel B processes the complemented clock CLK’. The set (S) input of the RS-latch employed for channel A and channel B drives high respectively at the rising edge of CLK and CLK’ introducing 180^o phase difference. To improve the stability of the converter, a fixed ramp compensation is introduced by integrating the clock and necessary scaling. Steady state waveforms of the inductor currents and gate signals for both channels of two-phase IBC recorded from simulations in PLECs software, are shown in Fig. 6(b). The fundamental frequency of i_IN is twice the switching frequency, which reduces the input inductive and output capacitive filter requirements.  

Fig. 6. (a) Peak-current mode controller modified for two-phase IBC; (b) simulation results comprising the gate signal of the control MOSFET, inductor and input currents.

(a)

(b)

B. Type-II Compensator

Despite being a non-minimum phase system, the two-phase IBC with a type-II controller exhibits better closed-loop performance. Further, a minimum overshoot, zero steady state error and faster transient response can be achieved. For current-mode control or for DC-DC converters that operates in the discontinuous conduction mode, the type-II compensator provides enough phase boost. This is a kind of lead controller that employs an RC branch to boost the phase and flatten the gain in the mid-frequency range.

The type-II controller transfer function is given in equation (2), from the control voltage v_c to the output voltage v_o with a pair of pole-zero combination and with a pole at the origin.

                  (2)

where ω_po=1/R_F1C_cmp2, ω_p=1/R_cmpC_cmp2 and ω_z=1/R_cmpC_cmp1 are the poles and zero of the controller. The magnitude and phase of the transfer function are:

TABLE II  Specifications of the Two-Phase IBC

Descriptions	Parameters	Values
Input voltage	vIN	24V
output voltage	vo	28V
Capacitance	C2	330µF
Inductance	L	4.7 µH
Switching frequency	fs	250kHz
Max. load current	Io(max)	16A

 (3)

where f_c is the crossover frequency and the maximum phase boost occurs and is given as:

   (4)

The high frequency pole ω_p attenuates switching noise at the error amplifier stage output and sets the desired phase boost of the controller. Fig. 7 shows the magnitude and phase plot of type-II controller, where ω_z is fixed at 5509 rad/sec and the pole ω_p is varied from 8264 rad/sec to 826450 rad/s. From the phase plot, the phase boost decreases with an increasing value of C_CMP2.

To interpret its effect on the performance of converter in the time domain the transient response of the two-phase IBC is shown Fig. 8 for different C_CMP2. It is quite evident that a faster dynamic response can be achieved by setting C_CMP2 to a lower value or in other words, by setting a high bandwidth. However, a wide bandwidth can result in harmonic instability if the converter switching frequency is higher. To reduce the effect of PCB noise on the controller performance, the bandwidth should be a smartly designed. Based on the analysis in Fig. 8, 10nF for C_CMP2 has been employed as switching noise because large voltage swing needs to be reduced to safe limits. 

C. Experimental Results

A 450W, two-phase IBC prototype is shown in Fig. 9, with the specifications shown in Table II, has been developed for study. The prototype has been tailored for a high power density of 6.45W/cm² with PCB dimensions of 95mm x 73mm. The controller design has been validated experimentally by executing the transient response tests presented in Fig. 10 and Fig. 11. Fig. 10 illustrates the load voltage and load current of the converter with the load current stepping between 2A and 6A. In Fig. 10 (a), the overshoot is 0.62V and settling time is 1.67ms. Similarly, at 24V input voltage, as shown in Fig. 10 (b), the settling time is 1.7ms and the load voltage undershoot is 0.45V. The transient test is repeated again with a different step size. The load voltage and load current of the converter with load current stepping between 5A and 10A is shown in Fig. 11(a) and 11(b). The overshoot and undershoot are 0.71V and 0.5V, while the settling time is 1.8ms and 1.2ms, respectively. The experimental results closely resemble the simulation results with an absolute error of 0.13V.

Fig. 7. The frequency response of G_c(s) with C_CMP1 = 15nF, R_CMP = 12.1kΩ and for different C_CMP2.

Fig. 8. Load voltage waveform v_o, when the load current alternates between 5A and 10A for different values of C_CMP2.

Fig. 9. Prototype of two-phase interleaved boost converter.

V. EFFICIENCY COMPARISON BETWEEN SILICON AND SILICON-CARBIDE BASED CONVERTERS

The efficiency of power electronic converters mainly depends on the losses introduced by semiconductor devices during switching transition (switching loss) and during conduction (conduction loss). In this section, the conduction and switching losses of MOSFETs are formulated. The losses contributed by the parasitic resistances of passive components and gate drive circuits are neglected to have a fair efficiency evaluation of Si and SiC MOSFETs. The parameters of the evaluated SiC (C2M0080120D from Cree Inc.) and Si (IPW65R190CFD from Infineon Technologies) MOSFETs are listed in Table III. V_DS(max), I_D(max) and T_j(max) are the maximum allowed drain-source voltage, drain current and maximum junction temperature of the device, respectively. The recommended turn-on and turn-off gate voltage is denoted as V_GS(r).

A. Conduction Losses

The intrinsic drain-source semiconductor resistance, represented as R_DS(on) in device datasheet, is responsible for conduction loss. The instantaneous conduction loss is time varying and is the product of the drain current I_DS and drain-source voltage v_DS. Therefore, the average conduction loss is calculated over a switching cycle. 

The average conduction loss of a control MOSFET (S_{A_M} or S_{B_M}) is:

     (5)

In terms of the load current I_o, the average conduction loss is:

         (6)

where the parameter δ depends on the I_DS and T_j of the device. Similarly, the average conduction loss in the synchronous Mosfet (S_{A’_M} and S_{B’_M}) is:

Fig. 10. Load voltage v_o and load current i_o: (a) load steps from 2A to 6A; (b) load steps from 6A to 2A.

Fig. 11. Load voltage v_o and load current i_o waveforms at the input supply voltage: (a) stepping load current from 5A to 10A; (b) load current steps from 10A to 5A.

   (7)

where V_SD is the forward voltage of the body diode, R_D is the conduction resistance and I_F(rms) is the rms value of the forward current through the body diode of the MOSFET.

The conduction losses of S_{x’_M} are greater than S_{x_M} when the conduction interval of S_{x’_M} is longer. For the converter under steady because of a low voltage gain the, conduction time of S_{x’_M} is six times longer than that of S_{x_M}. The body diode of a SiC MOSFET has high conduction loss that affects the reliability of the MOSFET. Therefore, Si or SiC Schottky diodes are strongly recommended in parallel with a SiC MOSFET to achieve high efficiency. 

For a SiC MOSFET the R_DS(on) is only few tens of milliohms, which is much lower when compared to its Si counterpart. Furthermore, R_DS(on) increases with an increase in the operating junction temperature T_j of the device. Fig. 12 shows the increase in R_DS(on) with a rise in T_j (extracted form the device datasheet) when drain currents of 20A and 7.5A flows through the evaluated SiC and Si MOSFETs. For the SiC MOSFET (blue line), a change in R_DS(on) over the entire operating range is very small and increases almost linearly with an estimated slope of δ = 0.0014/°C. However, the Si MOSFET R_DS(on) increases quadratically with an increase in T_j.

Fig. 12. The dependence of R_DS(on) on junction temperature T_j.

B. Switching Losses

The size and weight of a power electronic converter are important optimization parameters when aircraft is the target application. Second generation SiC MOSFETs can significantly reduce the cost, weight and volume of a converter by operating these devices at high switching frequencies. The rise time t_r and fall time t_f of SiC MOSFETs are much smaller than their Si counterparts, and can attain hundreds of kHz. Representing the MOSFET blocking voltage by V_DS, the switching power loss for the synchronous (P_{S(x’_M)}) and control MOSFET (P_{S(x_M)}) is determined by the following equation:

          (8)

where the times t_r and t_f depend on the external gate resistance and parasitic gate-source capacitance. The second term is the loss due to the charging and discharging of the output drain to source capacitance C_oss, which depends on value of C_oss and the magnitude of the blocking voltage V_DS.

Combining the switching and conduction losses as P_D, the efficiency of the converter is formulated as:

      (9)

where P_IN is input power and P_o is the output power.

The estimated efficiencies of Si and SiC converters, using the loss models in (6) and (7) are given in Fig. 13. The power dissipation in parasitic resistances of the inductive and capacitive filters were not incorporated into the model. Further, the power loss in the gate drive circuit has been assumed to be constant i.e. 8W and independent of the operating conditions.

The experimentally obtained efficiency of the SiC and Si based two-phase interleaved boost converters and their efficiency difference are shown in Fig. 14(a), 14(b) and 14(c), respectively. It was determined that the efficiency of the Si based converter achieves its maximum efficiency at a light load (0-5A) and that with an increase in the switching frequency and load current the efficiency decreases significantly. On the other hand, a higher switching frequency has a negligible effect on the efficiency of the SiC based converter. Furthermore, at higher junction temperatures because of a low R_DS(on), the efficiency of the SiC at the heavy loading conditions is 94%.

Fig. 13. Estimated efficiency of SiC and Si based converters.

Fig. 14. Experimental results: (a) efficiency of SiC converter (η_SiC); (b) efficiency of Si converter (η_Si); (c) efficiency difference (η_SiC- η_Si).

(a)

(b)

(c)

TABLE III  Parameters of the SIC and SI Mosfets

	SiC	Si	Unit
Part no.	C2M0080120D	IPW65R190CFD	-
VDS(max)	1200	700	V
ID(max)	31.6	17.5	A
Tj(max)	150	150	oC
RDS(on)	80	190	mΩ
Tθ(jc)	0.60	0.83	oC/W
VGS	20 / -5	13 / 0	on/off V
Coss	80	86	pF

C. Stability Analysis

The interaction between different systems when connected in cascade or parallel may introduce system stability issues. Small-signal impedance models of the interconnected systems can explain the stability of the overall system [10]. Using Z_o as the notation for the output impedance of the converter and Z_IN as the notation for the input impedance of load as illustrated in Fig. 15(a) and in Fig. 15(b) as an equivalent voltage divider circuit, the following small-signal transfer function of the interconnected system can be obtained as:

     (10)

The transfer function T(s) is the ratio of Z_o to Z_IN, and it can be observed as the minor loop gain of the interconnected system. Thus, to evaluate the stability of the interconnected system the Nyquist criteria can be applied to T(s) [11]. The computation/measurement of the output impedance Z_o in an under compensated case is challenging because of its high peak-to-peak voltage ripple and varying inductor current frequency. The time domain analysis is easy to execute and better to portray the existence of sub-harmonic oscillations [12]. For the stable operation case, the stability can be evaluated using equation (8).

Fig. 16 shows the measurement setup for the output impedance of the converter. A sweep signal generated at the source terminal of the network analyzer perturbs the output voltage of the two-phase IBC. Channel T (CHT) and CHR record the small signal output voltage and current.

Fig. 17 shows the output impedance, measured using network analyzer, at different load conditions. The input impedance Z_IN of the electronic load is not presented because of its flat trend. Meanwhile a Nyquist plot of T(s) is presented in Fig. 18. The system exhibits stability according to the criteria there is no encirclement of -1.

Fig. 15. Stability analysis: (a) block diagram; (b) equivalent circuit.

Fig. 16. Measurement setup for the output impedance Z_o of the converter.

Fig. 17. Output impedance Z_o at different operating loads.

Fig. 18. Nyquist plot of the transfer function T(s).

VI. CONCLUSIONS

A PCMC two phase boost converter has been presented in this paper. With the high band-gap SiC MOSFET, featuring low conduction and switching losses, a 97% peak efficiency has been achieved by the compensated system. The ringing noise from the drain, when the MOSFET is switched at high frequency, has a significant influence on the operation of the peak current mode controller, which leads to ripple instability. The bandwidth of the controller is an important parameter to tune, especially when the designer has no control over the ramp compensation. In HPD converters, which are volume optimized, access to the internal states of the converter and switching signals is not possible. The analysis presented in this paper identified that sub-harmonic instability causes an increase in the peak-to-peak ripple and a rise in the temperature of the MOSFETs. It has been shown that by restricting the bandwidth of the controller, the converter enters the stable mode, which has been experimentally validated.

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Haider Zaman received his B.S. degree in Electronics Engineering from the University of Engineering and Technology (UET), Abbottabad, Pakistan, in 2008; and his M.S. degree in Electrical Engineering from the COMSATS Institute of Information Technology (CIIT), Abbottabad, Pakistan, in 2013. He is presently working towards his Ph.D. degree in the School of Automation, Northwestern Polytechnical University, Xi’an, China. His current research interests include silicon carbide based high power density DC-DC and DC-AC converters.

Xiancheng Zheng received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from Northwestern Polytechnical University (NPU), Xi’an, China, in 1998, 2001 and 2011, respectively. In 2001, he joined NPU, where he is presently working as a Professor in the School of Automation. His current research interests include bidirectional AC-DC converter designs for aircraft electrical power systems, and silicon carbide based high power density DC-DC and DC-AC converters.

Mengxin Yang was born in 1994. He received his B.S. degree from Northwestern Polytechnical University, Xi’an, China, in 2016, where he is presently working towards his M.S. degree. His current research interests include the application of SiC MOSFETs in more electric aircraft and embedded control system design for switch- mode power supplies.

Husan Ali received his B.S. degree in Electrical Engineering and his M.S. degree in Communication and Electronics Engineering from the University of Engineering and Technology (UET), Peshawar, Pakistan, in 2009 and 2012, respectively. He received his M.S. degree in Electrical Engineering from Northwestern Polytechnical University (NPU), Xi’an, China, in 2014, where he is presently working towards his Ph.D. degree in the School of Automation. His current research interests include behavioral modeling and analysis of distributed power systems.

Xiaohua Wu received her B.S., M.S. and Ph.D. degrees in Electrical Engineering from Northwestern Polytechnical University (NPU), Xi’an, China, in 1991, 1994 and 2004, respectively. In 1994, she joined NPU, where she is presently working as a Professor in the School of Automation. Her current research interests include modern control in power electronics, the modeling and simulation of power electronic devices and the application of power electronics.