사각형입니다.

https://doi.org/10.6113/JPE.2018.18.1.34

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Pulse-width Adjustment Strategy for Improving the Dynamic Inductor Current Response Performance of a Novel Bidirectional DC–DC Boost Converter


Mingyue Li and Peimin Yan*


†,*School of Communication and Information Engineering, Shanghai University, Shanghai, China



Abstract 

This paper presents a pulse-width adjustment (PWA) strategy for a novel bidirectional DC–DC boost converter to improve the performance of the dynamic inductor current response. This novel converter consists of three main components: a full-bridge converter (FBC), a high-frequency isolated transformer with large leakage inductance, and a three-level voltage-doubler rectifier (VDR). A number of scholars have analyzed the principles, such as the soft-switching performance and high-efficiency characteristic, of this converter based on pulse-width modulation plus phase-shift (PPS) control. It turns out that this converter is suitable for energy storage applications and exhibits good performance. However, the dynamic inductor current response processes of control variable adjustment is not analyzed in this converter. In fact, dc component may occur in the inductor current during its dynamic response process, which can influence the stability and reliability of the converter system. The dynamic responses under different operating modes of a conventional feedforward control are discussed in this paper. And a PWA strategy is proposed to enhance the dynamic inductor current response performance of the converter. This paper gives a detailed design and implementation of the PWA strategy. The proposed strategy is verified through a series of simulation and experimental results.


Key words: Dynamic response, Full-bridge converter (FBC), Pulse-width adjustment (PWA) strategy, Voltage-doubler rectifier (VDR)


Manuscript received May 24, 2017; accepted Oct. 7, 2017

Recommended for publication by Associate Editor Honnyong Cha.

Corresponding Author: my141125@163.com Tel: +86-18800206090, Shanghai University

*School of Communication and Information Eng., Shanghai Univ., China



Ⅰ. INTRODUCTION

Energy crisis, the greenhouse effect, and environmental pollution have recently become important issues worldwide. Hence, developing a new energy technology has become a general trend. In this process, energy storage devices play an important role in new practical energy fields [1]. Bidirectional DC–DC converters have numerous topology structures that can be used to fulfill the requirements of different applications [2], [3]. Many energy storage applications require high step-up bidirectional DC–DC converters, and numerous researchers have studied this requirement from various aspects [4]-[7]. Among these converters, a full-bridge converter (FBC) cascaded with a three-level voltage-doubler rectifier (VDR) was proposed in [7]. This converter is suitable for energy storage applications because of its high power density and wide voltage variation.

Two FBCs linked with a high-frequency transformer and an inductor can form an isolated bidirectional dual-active-bridge (DAB) DC–DC converter. Studies on DAB converters were discussed in [8], [9]. DAB converters are widely used in energy storage applications due to their simple implementation and soft-switching capability. In some control strategies, however, switches will lose zero-voltage switching (ZVS) operation under a light load when the voltage transformation ratio is unequal to one [10]. For example, in single-phase-shift control, high circulating power and an increase in current stress may reduce the efficiency of DAB converters [11]. Although voltage transmission ratio can be increased by adjusting the turns ratio of a transformer, an increase in turns ratio may also decrease efficiency and increase hardware requirements. A VDR is a good circuit configuration for solving the aforementioned problems; which is equivalent to a voltage multiplier and can generate the required high voltage through four high-endurance power switches [12], [13]. In addition, the use of a VDR on the high-voltage side can increase the voltage gain of a converter and alleviate the requirements of a transformer. With its excellent performance under a wide voltage range, the circuit structure of an FBC cascaded with a three-level VDR (FBC–VDR) inherits most of the advantages of these devices, which deserves further study. 

There are few papers have discussed FBC–VDR, and relevant studies have mainly focused on the soft-switching conditions of this converter, whereas analyses have been made based on steady states. However, there are many other issues should also be considered. Among which, system response under a load step change, particularly the dynamic inductor current response, is a highly important aspect. The input and output currents of FBC–VDR are associated with the inductor current; hence, the inductor current will also change when output (or input) power changes. Changes in output voltage level and output load current can result in changes in output power. The dynamic response performance of a system during changes in output voltage level can be enhanced using several advanced closed-loop control strategies [14]. However, load step response performance cannot be enhanced by simply using a series of complex feedback algorithms because a load step typically occurs when a converter needs to provide larger or smaller load current but has to maintain a constant DC output voltage [15]. Changing the control variables of a system can regulate the magnitude of the inductor current, and thus, influence output load current. The dynamic inductor current response is one of the most important load step responses. Accordingly, this study aims to improve dynamic inductor current response performance. In a conventional general feedforward control strategy, sudden changes in system control variables can cause a sharp change in the inductor current. The inductor current will then have an extremely high magnitude within a certain period. One hypothesis for ideal cases is that stored energy in the energy transfer inductor is constant under each steady state of FBC–VDR, thereby indicating that no DC component occurs in the inductor current [5], [7]. However, during this load step process, the DC component decays in the inductor current. The inductor current consists of two components: the transformer magnetizing current and the leakage inductance current. The magnetizing current is generally small, and the transformer current is regarded as the inductor current in an ideal transformer model. The DC component that appears in this dynamic process may saturate the inductor and the transformer. Meanwhile, an uncertain and undesirable dynamic inductor current can affect the reliability of power switches or devices and even the stability of the converter system. These problems should not be disregarded.

A number of studies have proposed several methods to eliminate this type of DC component and enhance the dynamic inductor current response and load step response performance based on simple phase-shift controls in other converters [16]-[18]. The common point of these methods is adjusting the pulse widths of switching signals during the dynamic response period. However, few studies have focused on improving the dynamic inductor current response performance of FBC–VDR. Therefore, this study aims to evidently improve such performance in FBC–VDR. To achieve this objective, a pulse-width adjustment (PWA) strategy is proposed based on PWM plus phase-shift (PPS) control because the duty ratios and phase shift angles of switching signals can be adjusted using PPS control [19]-[21]. Compared with other simple phase-shift controls, PPS control is more complex but flexible. It can be extended to a series of similar phase-shift controls. Thus, PPS control has universal significance, which makes the proposed PWA worthy of promotion. The proposed PWA strategy is analyzed through theories, simulations, and experiments, thereby proving that it is easy to realize in hardware and software. Moreover, this strategy can effectively improve the dynamic inductor current response performance in FBC–VDR.

The remainder of this paper is organized as follows. Section II presents the work principles and modes of the proposed FBC–VDR based on PPS control. Section III discusses the normal load step response in a conventional feedforward control strategy. Section IV provides the detailed principles of the proposed PWA strategy. The involved theoretical equations and the simulation results are also described to demonstrate the effects under the PWA strategy. Section IV presents the experimental results. Finally, Section V concludes the study.



Ⅱ. WORK PRINCIPLES AND MODES OF FBC–VDR BASED ON PPS CONTROL

Fig. 1 shows the topology of FBC–VDR. The DC voltage Vi is on the low-voltage side, whereas voltage Vo is on the high-voltage side. Ro is regarded as the equivalent output resistor. The output DC voltage across Ro should be maintained at Vo. io is the output current of the converter. S1–S8 are power metal–oxide–semiconductor field-effect transistor switches. L (including the leakage inductance of a transformer) is an energy transfer inductor, and iL is the inductor current. The turns ratio of a high-frequency transformer is 1:N. The equivalent voltage gain of this FBCVDR is defined as

그림입니다.
원본 그림의 이름: CLP000033e40013.bmp
원본 그림의 크기: 가로 1069pixel, 세로 828pixel

PPS control is applied to FBCVDR. ZVS can be realized over a wide range for FBCVDR under PPS control [7]. The primary side of FBCVDR is FBC. Diagonal switches, such as S1 and S4, will turn on and off simultaneously with 50% duty cycles. Therefore, the FBC on the primary side generates a square-wave AC voltage, which is defined as vab. Meanwhile, the VDR is on the secondary side, which is cascaded with FBC through a high-frequency transformer and inductor L. The duty cycles of S5–S8 are different from 50%, and the phase-shift angle between S5 and S6 (or S7 and S8) is 180°. A common turn-on duration of S7 and S8 occurs. Therefore, a zero-voltage state will be generated. Thus, the VDR side can generate a three-level square-wave AC voltage, which is defined as vcd. Moreover, the amplitude of Vo is twice that of vcd, which indicates that the voltage stress of the secondary switches can be significantly smaller. This advantage also allows the application of FBC–VDR to high step-up situations.


그림입니다.
원본 그림의 이름: CLP000033e40014.bmp
원본 그림의 크기: 가로 2019pixel, 세로 1059pixel

Fig. 1. Topology of FBC–VDR.


The key work waveforms of FBC–VDR under PPS control are shown in Fig. 2. Some switching signals are complementary with each other. For example, the switching signals of S1 and S4 are complementary with those of S2 and S3, the switching signal of S5 is complementary with that of S7, and the switching signal of S6 is complementary with that of S8.Therefore, only the switching signals of S1 and S4, S5, and S6 are illustrated in Fig. 2. As shown in Fig. 2(a), the duty ratio of vab is 0.5 and that of vcd is defined as Dy. T is half a switching period. Dφ is defined as the equivalent phase-shift ratio between vab and vcd, which indicates the phase shift between the mid-point of the high-level duration of vab and that of the high-level duration of vcd. Energy will flow from the primary side to the secondary side when Dφ > 0 and vice versa.

FBC–VDR has boost and buck operation modes with the variation of k and Dφ. In the forward-boost mode, the voltage gain is larger than one and Dφ is larger than zero. In the backward-buck mode, the voltage gain is smaller than one and Dφ is smaller than 0. The analyses are similar under different operation modes. For simplicity, this paper discusses only the forward-boost mode and assumes that energy flows from the primary side to the secondary side.

The forward-boost mode has three typical cases: continuous conduction mode (CCM) 1, CCM2, and CCM3. The work waveforms of the three modes are shown in Figs. 2(a) CCM1, 2(b) CCM2, and 2(c) CCM3.

As shown in Fig. 2(a), CCM1 is used as an example to show the operation principle of FBC–VDR under PPS control. The inductor voltage vL is vabvcd, as clearly indicated Fig. 1. Hence, iL can be given by the following equation:

그림입니다.
원본 그림의 이름: CLP000033e40015.bmp
원본 그림의 크기: 가로 2285pixel, 세로 482pixel            (1)

Six intervals occur in one switching period. S1, S4, S7, and S8 are on from t0 to t1. Vi supplies power to the inductor through the high-frequency transformer. The inductor current will satisfy Equation (2). The value of iL at t1 is IL (t1).


Fig. 2. Work waveforms of the three modes in the forward-boost mode: (a) CCM1, (b) CCM2, and (c) CCM3.

그림입니다.
원본 그림의 이름: CLP000032a448ad.bmp
원본 그림의 크기: 가로 1118pixel, 세로 1189pixel

 

그림입니다.
원본 그림의 이름: CLP000032a40001.bmp
원본 그림의 크기: 가로 1137pixel, 세로 1206pixel

 

그림입니다.
원본 그림의 이름: CLP000032a40002.bmp
원본 그림의 크기: 가로 1195pixel, 세로 1234pixel


TABLE I  Inductor Current in Steady State

Mode

IL(t0)/그림입니다.
원본 그림의 이름: CLP00000adc2bcc.bmp
원본 그림의 크기: 가로 671pixel, 세로 531pixel

IL(t1)/그림입니다.
원본 그림의 이름: CLP00000adc2bcc.bmp
원본 그림의 크기: 가로 671pixel, 세로 531pixel

IL(t2)/그림입니다.
원본 그림의 이름: CLP00000adc2bcc.bmp
원본 그림의 크기: 가로 671pixel, 세로 531pixel

CCM1

그림입니다.
원본 그림의 이름: CLP000033e40010.bmp
원본 그림의 크기: 가로 1504pixel, 세로 624pixel

그림입니다.
원본 그림의 이름: CLP000033e4000a.bmp
원본 그림의 크기: 가로 1369pixel, 세로 275pixel

그림입니다.
원본 그림의 이름: CLP000033e4000d.bmp
원본 그림의 크기: 가로 1417pixel, 세로 291pixel 

CCM2

그림입니다.
원본 그림의 이름: CLP000033e40011.bmp
원본 그림의 크기: 가로 2106pixel, 세로 531pixel

그림입니다.
원본 그림의 이름: CLP000033e4000b.bmp
원본 그림의 크기: 가로 1488pixel, 세로 236pixel

그림입니다.
원본 그림의 이름: CLP000033e4000e.bmp
원본 그림의 크기: 가로 1222pixel, 세로 297pixel

CCM3

그림입니다.
원본 그림의 이름: CLP000033e40012.bmp
원본 그림의 크기: 가로 1467pixel, 세로 542pixel

그림입니다.
원본 그림의 이름: CLP000033e4000c.bmp
원본 그림의 크기: 가로 2091pixel, 세로 330pixel

그림입니다.
원본 그림의 이름: CLP000033e4000f.bmp
원본 그림의 크기: 가로 1981pixel, 세로 326pixel


그림입니다.
원본 그림의 이름: CLP000032a40003.bmp
원본 그림의 크기: 가로 2055pixel, 세로 350pixel                (2)

Moreover, IL(t0) + IL(t3) = 0 due to the symmetry.

From Figs. 1 and 2(a), the equations for iL in the remaining intervals can be obtained using a similar analysis.

그림입니다.
원본 그림의 이름: CLP000032a40004.bmp
원본 그림의 크기: 가로 1685pixel, 세로 423pixel                      (3)

그림입니다.
원본 그림의 이름: CLP000032a40005.bmp
원본 그림의 크기: 가로 1625pixel, 세로 340pixel                  (4)

그림입니다.
원본 그림의 이름: CLP000032a40006.bmp
원본 그림의 크기: 가로 1869pixel, 세로 323pixel               (5)

그림입니다.
원본 그림의 이름: CLP000032a40008.bmp
원본 그림의 크기: 가로 1888pixel, 세로 444pixel                        (6)

The values of IL(t3)–IL(t6) are omitted in this section because the derivation process is similar to the previous analysis. To facilitate the subsequent analysis, the inductor current values for different intervals in CCM1, CCM2, and CCM3 are shown in Table I.

The standardization value IM in the table is defined as

그림입니다.
원본 그림의 이름: CLP000032a40007.bmp
원본 그림의 크기: 가로 1518pixel, 세로 706pixel                             (7)



Ⅲ. DYNAMIC INDUCTOR CURRENT RESPONSE WITH GENERAL FEEDFORWARD CONTROL

As mentioned earlier, the value of the equivalent resistance of Ro may change in practice to provide an alternative current, and the voltage across Ro should be maintained. Hence, system control variables, such as Dy and Dφ, should be adjusted to increase or decrease the inductor current with a constant voltage of Vo.

Fig. 3 presents an example of the dynamic inductor current response performance with general feedforward control in CCM1. To implement a step change in the inductor current iL, the duty ratio of vcd should suddenly change from Dy to Dy' at t0. Before t0, the waveform of iL is nearly completely symmetric along the zero axis. After t0, the waveform of iL will be asymmetrical along the zero axis, which indicates that the DC component Idc is contained within iL. Although control variables Dy and Dφ are changed, the inductor current or other circuit performance may not immediately change. The trend of the inductor current step response is illustrated in Fig. 4(a).


그림입니다.
원본 그림의 이름: CLP00001ea40006.bmp
원본 그림의 크기: 가로 1238pixel, 세로 854pixel

Fig. 3. Simulation waveforms of the dynamic inductor current response with general feedforward control in CCM1.


Fig. 4. Trends of the dynamic inductor current response with general feedforward control in (a) CCM1, (b) CCM2, and (c) CCM3.

그림입니다.
원본 그림의 이름: CLP0000140c0006.bmp
원본 그림의 크기: 가로 1597pixel, 세로 804pixel

(a)

 

그림입니다.
원본 그림의 이름: image27.emf
원본 그림의 크기: 가로 481pixel, 세로 211pixel

(b)

 

그림입니다.
원본 그림의 이름: image28.emf
원본 그림의 크기: 가로 603pixel, 세로 288pixel

(c)


The dynamic response time is evidently long, and a DC component occurs in iL during this step response. Moreover, the attendant excessive inductor current may damage the switches and other devices. Similar step responses in CCM2 and CCM3 are shown in Figs. 4(b) and 4(c), respectively.

The DC component in the inductor current may saturate the inductor and the transformer. The addition of an appropriate blocking capacitor in the series with the inductor or the transformer is a common and effective means to avoid the DC component problem [22]. The blocking capacitor can make the waveform of the inductor current symmetric.

However, the buffering speed of the blocking capacitor exhibits difficulty in meeting the real requirements of the step response. Therefore, improving the steady-state performance is necessary.

For example, the DC components in CCM2 (Fig. 4(b)) are caused by abrupt changes in the control variables. If a blocking capacitor is added, then a fluctuation occurs in the inductor current for a certain period and the excessive current is not removed (Fig. 5), which requires an enhanced method to improve response performance.


그림입니다.
원본 그림의 이름: CLP000048fc003d.bmp
원본 그림의 크기: 가로 1577pixel, 세로 756pixel

Fig. 5. Trends of the dynamic inductor current response with general feedforward control and with the addition of a blocking capacitor.



Ⅳ. PRINCIPLES AND SIMULATIONS OF THE PWA STRATEGY

A PWA strategy is proposed in this section to significantly improve the dynamic inductor current response performance.

Abrupt changes in the control variables can cause unstable dynamic response. In general feedforward control, to change Dy to Dy' and Dφ to Dφ' within a specific point in time, the phase shift Δ1T between two rising edges of vab (−Vi to Vi) and vcd (−0.5 Vo to 0.5 Vo) must be equal to the specified value (1/2 + Dφ' Dy'/2)T, as shown in Fig. 6. In addition, the duty ratio of vcd will be changed immediately to Dy', such that the parameters can reach their new design values in the subsequent periods. This method brings the DC component over a long period.

Unlike general feedforward control, the PWA strategy will gradually change Dy and Dφ to Dy' and Dφ', respectively. In the PWA strategy, the phase shift Δ2T between the two rising edges of vab (−Vi to Vi) and vcd (−0.5 Vo to 0.5 Vo) is a flexible parameter. The duty ratio of vcd during t1 to t2 is defined as Δ3. The value of Δ3 must be equal to a specified value to finally change the duty ratio of vcd to Dy'. Δ2 and Δ3 build a two-degree-of-freedom control structure to remove the DC component from t3 by assuming that the average value of iL is zero in each period after t3. Therefore, the DC component problem can be solved.

The theoretical derivations of the PWA strategy in the three CCM modes are presented in the remaining parts of this section.


A. PWA Strategy Applied to CCM1

The work waveforms of the PWA strategy in CCM1 are shown in Fig. 6. t0 is selected as the start time to implement the PWA strategy. As shown in Fig. 4, Δ2 is an adjustment factor that can reasonably change the control variables. The DC component in iL can be removed in each period after t3 by adjusting Δ2.

The time interval values in Fig. 6 are

그림입니다.
원본 그림의 이름: CLP00002bf00002.bmp
원본 그림의 크기: 가로 1220pixel, 세로 1260pixel       (8)

From Table I and Eqs. (1) and (8), the inductor current values can be obtained as follows:


그림입니다.
원본 그림의 이름: CLP00000138be43.bmp
원본 그림의 크기: 가로 602pixel, 세로 143pixel                     (9)

그림입니다.
원본 그림의 이름: CLP000001380001.bmp
원본 그림의 크기: 가로 729pixel, 세로 178pixel               (10)

그림입니다.
원본 그림의 이름: CLP000001380002.bmp
원본 그림의 크기: 가로 1147pixel, 세로 280pixel (11)

그림입니다.
원본 그림의 이름: CLP000001380003.bmp
원본 그림의 크기: 가로 1212pixel, 세로 159pixel  (12)

그림입니다.
원본 그림의 이름: CLP000001380004.bmp
원본 그림의 크기: 가로 1147pixel, 세로 266pixel (13)

그림입니다.
원본 그림의 이름: CLP000001380005.bmp
원본 그림의 크기: 가로 1139pixel, 세로 268pixel (14)

그림입니다.
원본 그림의 이름: CLP000001380006.bmp
원본 그림의 크기: 가로 1200pixel, 세로 141pixel   (15)


그림입니다.
원본 그림의 이름: CLP00001ea40007.bmp
원본 그림의 크기: 가로 926pixel, 세로 817pixel

Fig. 6. Comparative work waveforms between the two methods.


그림입니다.
원본 그림의 이름: CLP000001380007.bmp
원본 그림의 크기: 가로 834pixel, 세로 135pixel           (16)

그림입니다.
원본 그림의 이름: CLP000001380008.bmp
원본 그림의 크기: 가로 916pixel, 세로 145pixel        (17)

그림입니다.
원본 그림의 이름: CLP000001380009.bmp
원본 그림의 크기: 가로 645pixel, 세로 137pixel                        (18)

To remove the Idc, the average value of iL, which is defined as I () , should be zero from t3 to t9. Hence,

그림입니다.
원본 그림의 이름: CLP00000138000a.bmp
원본 그림의 크기: 가로 959pixel, 세로 160pixel       (19)

Therefore, 

그림입니다.
원본 그림의 이름: CLP00000138000b.bmp
원본 그림의 크기: 가로 446pixel, 세로 159pixel                         (20)

In addition,

그림입니다.
원본 그림의 이름: CLP00000138000c.bmp
원본 그림의 크기: 가로 393pixel, 세로 188pixel                           (21)

Eq. (20) presents the condition that should be satisfied. This variable Δ2 depends only on the values of Dφ and Dy. The time interval values of t1 to t2 are equal to Δ3T, such that Δ3 is limited to (Dy' + Dy)/2. Δ2 and Δ3 can be generated by changing the pulse widths of the switching signals. In the PWA strategy, the dynamic response speed can be increased by forcibly making the average value of the inductor current be zero within a remarkably short period. Hence, the excessive current is also limited to the new steady-state value.


B. PWA Strategy Applied to CCM2

The work waveforms of the PWA strategy in CCM2 are shown in Fig. 7. In this mode, the phase shift between vab and vcd is assumed to change from Dφ to Dφ' and the duty ratio of vcd is assumed to change from Dy to Dy'.

그림입니다.
원본 그림의 이름: CLP00001ea40008.bmp
원본 그림의 크기: 가로 1011pixel, 세로 692pixel

Fig. 7. Work waveforms of the PWA strategy in CCM2.


The time interval values in Fig. 5 are illustrated in Eq. (22):

그림입니다.
원본 그림의 이름: CLP00000138000d.bmp
원본 그림의 크기: 가로 976pixel, 세로 1202pixel      (22)

The inductor current values can be derived from Eqs. (1) and (22) and Table I.

그림입니다.
원본 그림의 이름: CLP00000138000e.bmp
원본 그림의 크기: 가로 739pixel, 세로 153pixel               (23)

그림입니다.
원본 그림의 이름: CLP00000138000f.bmp
원본 그림의 크기: 가로 1359pixel, 세로 165pixel      (24)

그림입니다.
원본 그림의 이름: CLP000001380010.bmp
원본 그림의 크기: 가로 1163pixel, 세로 155pixel    (25)

그림입니다.
원본 그림의 이름: CLP000001380011.bmp
원본 그림의 크기: 가로 1244pixel, 세로 133pixel (26)

그림입니다.
원본 그림의 이름: CLP000001380012.bmp
원본 그림의 크기: 가로 777pixel, 세로 160pixel             (27)

To remove the DC component in iL, Eq. (28) should be satisfied.

그림입니다.
원본 그림의 이름: CLP000001380013.bmp
원본 그림의 크기: 가로 909pixel, 세로 145pixel        (28)

Therefore, 

그림입니다.
원본 그림의 이름: CLP000001380014.bmp
원본 그림의 크기: 가로 438pixel, 세로 177pixel                          (29)

and 

그림입니다.
원본 그림의 이름: CLP000001380015.bmp
원본 그림의 크기: 가로 493pixel, 세로 111pixel                        (30)


그림입니다.
원본 그림의 이름: CLP00001ea40009.bmp
원본 그림의 크기: 가로 1013pixel, 세로 668pixel

Fig. 8. Work waveforms of the PWA strategy in CCM3.



C. PWA Strategy Applied to CCM3

The inductor current values can be obtained at different moments according to Table 1 and Eqs. (1) and (31).

그림입니다.
원본 그림의 이름: CLP000001380016.bmp
원본 그림의 크기: 가로 618pixel, 세로 140pixel                        (31)

그림입니다.
원본 그림의 이름: CLP000001380017.bmp
원본 그림의 크기: 가로 759pixel, 세로 147pixel                    (32)

그림입니다.
원본 그림의 이름: CLP000001380018.bmp
원본 그림의 크기: 가로 1130pixel, 세로 266pixel         (33)

그림입니다.
원본 그림의 이름: CLP000001380019.bmp
원본 그림의 크기: 가로 1198pixel, 세로 161pixel       (34)

그림입니다.
원본 그림의 이름: CLP00000138001a.bmp
원본 그림의 크기: 가로 612pixel, 세로 153pixel                        (35)

From the previous analysis, the following equation should be satisfied to remove the DC component in iL:

그림입니다.
원본 그림의 이름: CLP00000138001b.bmp
원본 그림의 크기: 가로 910pixel, 세로 147pixel               (36)

Therefore, 

그림입니다.
원본 그림의 이름: CLP00000138001c.bmp
원본 그림의 크기: 가로 449pixel, 세로 170pixel                             (37)

and

그림입니다.
원본 그림의 이름: CLP00000138001d.bmp
원본 그림의 크기: 가로 395pixel, 세로 174pixel                              (38)

Eq. (20) is the same as Eq. (36) and Eq. (21) is the same as Eq. (39), such that the conditions for CCM1 and CCM3 are the same.

The theoretical analysis and evaluation of the PWA strategy are simple, and this strategy exhibits the same complexity as the general feedforward method.

The simulation results of the PWA strategy are presented in Fig. 9. Compared with the results in Fig. 4, the dynamic inductor current response time can be significantly shortened by using the PWA strategy, Idc becomes zero within a short time, and the peak value of iL at the dynamic moments in Fig. 9 is closed to the subsequent steady-state value.


Fig. 9. Simulation waveforms of the inductor current with the PWA strategy in (a) CCM1, (b) CCM2, and (c) CCM3.

그림입니다.
원본 그림의 이름: image64.emf
원본 그림의 크기: 가로 504pixel, 세로 283pixel

(a)

 

그림입니다.
원본 그림의 이름: image65.emf
원본 그림의 크기: 가로 598pixel, 세로 301pixel

(b)

 

그림입니다.
원본 그림의 이름: image66.emf
원본 그림의 크기: 가로 529pixel, 세로 283pixel

(c)


As mentioned earlier, the inductor current iL is closely related to the output current io. The PWA strategy also helps improve output performance. The dynamic responses of the output current are shown under different cases in Fig. 10.


Fig. 10. Dynamic responses of the output current under different cases: (a) CCM1 with general feedforward control, (b) CCM1 with the PWA strategy, (c) CCM2 with general feedforward control, (d) CCM2 with the PWA strategy, (e) CCM3 with general feedforward control, and (f) CCM3 with the PWA strategy.

그림입니다.
원본 그림의 이름: image67.emf
원본 그림의 크기: 가로 585pixel, 세로 259pixel

(a)

 

그림입니다.
원본 그림의 이름: image70.emf
원본 그림의 크기: 가로 583pixel, 세로 256pixel

(b)

 

그림입니다.
원본 그림의 이름: image68.emf
원본 그림의 크기: 가로 586pixel, 세로 257pixel

(c)

 

그림입니다.
원본 그림의 이름: image71.emf
원본 그림의 크기: 가로 585pixel, 세로 258pixel

(d)

 

그림입니다.
원본 그림의 이름: image69.emf
원본 그림의 크기: 가로 585pixel, 세로 256pixel

(e)

 

그림입니다.
원본 그림의 이름: image72.emf
원본 그림의 크기: 가로 585pixel, 세로 257pixel

(f)



Ⅴ. EXPERIMENTAL VERIFICATION

An FBC–VDR prototype is built to verify the validity of the PWA strategy. The main parameters of the prototype are provided in Table II. This prototype is implemented on a DSP development board.


TABLE II  Main Circuit Parameters

Parameter

Value

DC voltage Vi

25 V

DC voltage Vo

120 V

Transformer turns ratio 1:N

1:2

S1–S4

IPP037N08N

S5–S8

IRFB4229

Inductor L

48 μH

Switching frequency

100 kHz

Capacitors Ci, Co1, and Co2

470 μF


A simple description of the block diagram of the PWA strategy is presented in Fig. 11. The controller will change the switching signals of S5, S6, S7, and S8 according to Δ2 and Δ3.


그림입니다.
원본 그림의 이름: CLP0000140c0009.bmp
원본 그림의 크기: 가로 1418pixel, 세로 777pixel

Fig. 11. Block diagram of the PWA strategy.


Fig. 12 illustrates the immediate impact of a blocking capacitor. The DC component problem and excessive current cannot be removed by adding a blocking capacitor. Fig. 13 shows the experimental trends of the dynamic inductor current response with general feedforward control in CCM1, CCM2, and CCM3. A DC component occurs in the inductor current within a long period.


그림입니다.
원본 그림의 이름: CLP00001ea4000a.bmp
원본 그림의 크기: 가로 1233pixel, 세로 629pixel

Fig. 12. Experimental waveform of iL with the addition of a blocking capacitor.


Fig. 13. Experimental trends of the dynamic inductor current response with general feedforward control in (a) CCM1, (b) CCM2, and (c) CCM3.

그림입니다.
원본 그림의 이름: CLP00001ea4000b.bmp
원본 그림의 크기: 가로 1218pixel, 세로 650pixel

(a)

 

그림입니다.
원본 그림의 이름: CLP00001ea4000c.bmp
원본 그림의 크기: 가로 1222pixel, 세로 644pixel

(b)

 

그림입니다.
원본 그림의 이름: CLP00001ea4000d.bmp
원본 그림의 크기: 가로 1213pixel, 세로 647pixel

(c)


In Figs. 4, 9, 13, and 14, Dy is changed from 0.25 to 0.35 and Dφ is changed from 0.0167 to 0.0833 under CCM1; Dy is changed from 0.2 to 0.2667 and Dφ is changed from 0.3667 to 0.5667 under CCM2; and Dy is changed from 0.2 to 0.4 and Dφ is changed from 0.7667 to 0.9333 under CCM3.

Fig. 14. Experimental waveforms of the inductor current with the PWA strategy in (a) CCM1, (b) CCM2, and (c) CCM3.

그림입니다.
원본 그림의 이름: CLP00001ea4000e.bmp
원본 그림의 크기: 가로 693pixel, 세로 926pixel

(a)

 

그림입니다.
원본 그림의 이름: CLP00001ea4000f.bmp
원본 그림의 크기: 가로 699pixel, 세로 927pixel

(b)

 

그림입니다.
원본 그림의 이름: CLP00001ea40010.bmp
원본 그림의 크기: 가로 696pixel, 세로 859pixel

(c)


When Fig. 14 is compared with Fig. 13, the experimental waveforms in the PWA strategy exhibit a faster dynamic response under all modes. During the first dynamic response periods, the excessive values of the inductor currents under the PWA strategy are considerably less than those under general feedforward control. The experimental results show that the proposed PWA strategy is suitable for removing the DC component in inductor currents and increasing dynamic response speed.



Ⅵ. CONCLUSIONS

FBC–VDR is a high step-up DC–DC converter for energy storage applications. This study focuses on the DC component problem in inductor and transformer currents and the step inductor current response performance caused by abrupt changes in control variables. After conducting theoretical analysis, a PWA strategy is proposed to address the aforementioned problems. This effective method is verified through simulations and experiments. The simulation and experimental results exhibit good agreement with the theory. The results prove that the PWA strategy can increase the dynamic response speed and enhance the step inductor current response performance in FBC–VDR. Thus, this strategy is effective for improving the stability and reliability of converter systems. It can make FBC–VDR suitable for real applications.



REFERENCES

[1] J. K. Eom, J. G. Kim, J. H. Kim, S. T. Oh, Y. C. Jung, and C. Y. Won, “Analysis of a novel soft switching bidirectional dc-dc converter,” J. Power Electron., Vol. 12, No. 6, pp. 2154-2159, 2012.

[2] B. R. Lin and C. C. Chen, “New three-level PWM DC/DC converter – Analysis, design and experiments,” J. Power Electron., Vol. 14, No. 1, pp. 30-39, 2014.

[3] Y. C. Lee, H. K. Kim, J. H. Kim, and S. S. Hong, “A study on implementing a phase-shift full-bridge converter employing an asynchronous active clamp circuit,” J. Power Electron., Vol. 14, No. 3, pp. 413-420, May 2014.

[4] K. C. Tseng, C. C. Huang, and W. Y. Shih, “A high step-up converter with a voltage multiplier module for a photovoltaic system,” IEEE Trans. Power Electron., Vol. 28, No. 6, pp. 3047-3057, Jun. 2013.

[5] H. Wu, Y. Lu, K. Sun, and Y. Xing, “Phase-shift-controlled isolated buck-boost converter with active-clamped three- level rectifier (AC-TLR) featuring soft-switching within wide operation range,” IEEE Trans. Power Electron., Vol.31, No.3, pp. 2372-2386, Mar. 2015.

[6] Y. M. Chen, A. Q. Huang, and X. Yu, “A high step-up three-port DC–DC converter for stand-alone PV/battery power systems,” IEEE Trans. Power Electron., Vol. 28, No. 11, pp.5049-5062, Nov. 2013.

[7] X. Zhan, H. Wu, Y. Xing, H. Ge, and X. Xiao, “A high step-up bidirectional isolated dual-active-bridge converter with three-level voltage-doubler rectifier for energy storage applications,” in IEEE Applied Power Electronics Conference and Exposition, 2016.

[8] S. Inoue and H. Akagi, “A bidirectional dc-dc converter for an energy storage system with galvanic isolation,” IEEE Trans. Power Electron., Vol. 22, No. 6, pp. 2299-2306, Nov. 2007.

[9] B. Zhao, Q. Song, W. Liu, and Y. Sun, “Overview of dual-active-bridge isolated bidirectional DC–DC converter for high-frequency-link power-conversion system,” IEEE Trans. Power Electron., Vol. 29, No. 8, pp. 4091-4106, Oct. 2014.

[10] H. W. Song, H.-S. Kim, G.-W. Moon, and M.-J. Youn, “Light-load efficiency improvement for zero-voltage switching boost integrated converters,” in 8th International Conference on Power Electronics – ECCE Asia, pp. 1591-1598. 2011.

[11] B. Zhao, Q. Yu, and W. Sun, “Extended-phase-shift control of isolated bidirectional DC–DC converter for power distribution in microgrid,” IEEE Trans. Power Electron., Vol. 27, No. 11, pp. 4667-4680, Nov. 2012.

[12] R. A. D. Camara, R. N. A. L. Silva, G. A. L. Henn, P. P. Praa, C. M. T. Cruz, and R. P. Torrico-Bascope, “Voltage doubler boost rectifier based on three-state switching cell for UPS applications,” in Conference of IEEE Industrial Electronics IEEE, pp. 950-955, 2009.

[13] H. W. Seong, H. S. Kim, K. B. Park, and G. W. Moon, “Zero-voltage switching flyback-boost converter with voltage-doubler rectifier for high step-up applications,” IEEE Energy Conversion Congress and Exposition, pp. 823-829. 2010.

[14] A. Dell' Aquila, M. Liserre, V. G. Monopoli, and P. Rotondo, “Overview of pi-based solutions for the control of dc buses of a single-phase h-bridge multilevel active rectifier,” IEEE Trans. Ind. Appl., Vol. 44, No. 3, pp.857-866, May/Jun. 2008.

[15] D. Segaran, D. G. Holmes, and B. P. Mcgrath, “Enhanced load step response for a bidirectional dc–dc converter”, IEEE Trans. Power Electron., Vol. 28, No. 1, pp. 371-379, Jan. 2013.

[16] K. Aoyama, N. Motoi, Y. Tsuruta, and A. Kawamura, “Transient behavior of the dual active bridge converter in high efficient energy conversion system,” in Power Electronics Conference IEEE, pp. 2266-2271, 2014.

[17] H. Bai, C. Mi, C. Wang, and S. Gargies, “The dynamic model and hybrid phase-shift control of a dual-active- bridge converter,” in Industrial Electronics, 2008. IECON 2008. Conference of IEEE Xplore, pp. 2840-2845, 2008.

[18] B. Zhao, Q. Song, W. Liu, and Y. Zhao, “Transient Dc component and Current Impact Effects of High- Frequency-Isolated Bidirectional DC-DC Converter in Practice,” IEEE Trans. Power Electron., Vol. 31, No. 4, pp. 3203-3216, Apr. 2016.

[19] D. Xu, C. Zhao, and H. Fan, “A PWM plus phase-shift control bidirectional DC-DC converter,” IEEE Trans. Power Electron., Vol. 19, No. 3, pp. 666-675, May 2004.

[20] H. F. Xiao and S. Xie, “A ZVS bidirectional DC–DC converter with phase-shift plus PWM control scheme,” IEEE Trans. Power Electron., Vol. 23, No. 2, pp. 813-823, Mar. 2008.

[21] Y. J. Lu, Y. Xing, and H. Wu, “A PWM plus phase-shift controlled interleaved isolated boost converter based on semiactive quadrupler rectifier for high step-up applications,” IEEE Trans. Ind. Electron., Vol. 63, No. 7, pp. 4211-4221, Jul. 2016.

[22] A. Pressman, A. Pressman, and A. Pressman, “Switching power supply design 3/e,” Mcgraw-Hill Publ. Comp, 2009.



그림입니다.
원본 그림의 이름: image82.jpeg
원본 그림의 크기: 가로 190pixel, 세로 225pixel

Mingyue Li was born in China in 1993. She obtained her B.S. in Electronic Information Engineering from The North University of China, Taiyuan, Shanxi in 2015. She is currently completing a Master’s in Com- munication and Information Engineering in Shanghai University, Shanghai, China. Her research interests include bidirectional DC–DC converters, phase shift control, and pulse-width modulation control.


그림입니다.
원본 그림의 이름: image81.jpeg
원본 그림의 크기: 가로 191pixel, 세로 234pixel

Peimin Yan was born in Shanghai, China. She obtained her B.S. in Radio and Information Engineering from Shanghai Science and Technology University, Shanghai, China in 1985 and her M.S. and Ph.D. in Communication and Information Engineering from Shanghai University, Shanghai, China in 2001 and 2005, respectively. She has been an Associate Professor in the School of Communication and Information Engineering since 2001. Her current research interests include circuits, digital signal processing, and digital image processing and control in various industrial fields.