https://doi.org/10.6113/JPE.2018.18.1.81

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Double Line Voltage Synthesis Strategy for Three-to-Five Phase Direct Matrix Converters

Rutian Wang^†, Yanfeng Zhao^*, Xingjun Mu^**, and Weiquan Wang^*

^†,*School of Electrical Engineering, Northeast Electric Power University, Jilin, China

^**Fujian Yongfu Power Engineering Co., Ltd., Fuzhou, China

Abstract 

This paper proposes a double line voltage synthesis (DLVS) strategy for three-to-five phase direct matrix converters. In the proposed strategy, the input and expected output voltages are divided into 6 segments and 10 segments, respectively. In addition, in order to obtain the maximum voltage transfer ratio (VTR), the input line voltages and “source key” should be selected reasonably according to different combinations of input and output segments. Then, the corresponding duty ratios are calculated to determine the switch sequences in different segment combinations. The output voltages and currents are still sinusoidal and symmetrical with little lower order harmonics under unbalanced or distorted input voltages by using this strategy. In addition, the common mode voltage (CMV) can be suppressed by rearranging some of the switching states. This strategy is analyzed and studied by a simulation model established in MATLAB/Simulink and an experimental platform, which is controlled by a DSP and FPGA. Simulation and experimental results verify the feasibility and validity of the proposed DLVS strategy.

Key words: Common mode voltage, Direct matrix converter, Double line voltage synthesis strategy, Source key, Three-to-five phase, Unbalanced or distorted input voltages

Manuscript received Apr. 24, 2017; accepted Oct. 6, 2017

Recommended for publication by Associate Editor Saad Mekhilef.

^†Corresponding Author: wrtmail@163.com

Tel: +86-15948696698, Northeast Electric Power University

^*School of Electrical Eng., Northeast Electric Power University, China

^**Fujian Yongfu Power Engineering Co., Ltd, China

Ⅰ. INTRODUCTION

Compared with traditional three-phase machines drives, the multi-phase machines drives have some advantages such as reducing torque pulsations, reducing the current per phase without increasing the phase voltage, designs with a lower voltage for the same total power, and most importantly high system reliability and stability [1]-[7]. The fault-tolerant property results in multi-phase systems being widely used for high performance applications where reliability is improntant such as electric/hybrid electric vehicle drives, electric ship propulsion, aircraft drives, locomotive traction, offshore wind generation, aerospace drives and some high power industrial applications [3]-[9].

Multi-phase power converters are energy conversion devices that are matched with multi-phase system drives, and they can achieve high power energy transformations under limited voltage levels. Multi-phase matrix converters are one of the most advanced AC-AC conversion technologies among the multiphase power converters. In addition, the three-to-five phase direct matrix converter (DMC) is the most representative of these converters, and its topology is shown in Fig. 1. There are bidirectional switches connecting each phase of the input with five-phase of the output. The benefits of the three-to-five phase DMC are similar to those of the three-to-three phase DMC since it has no large energy storage component requirements, a compact structure, a bidirectional energy flow, an unrestricted output frequency, and a controllable input power factor [10]-[12]. In addition, the maximum VTR of the three-to-five phase DMC is 0.7885 [12], [13].

At present, the most widely used modulation methods for the three-to-five phase DMC include the space vector pulse width modulation (SVPWM) and carrier-based pulse width modulation (CBPWM) methods. The duty ratio of each vector is obtained based on the division and combination of the input and output sectors in the SVPWM method [12]-[14]. This method is convenient for the elimination of narrow pulses and voltage compensation. The CBPWM method has recently been adopted in [15], [16] since it is easier to implement compared with the SVPWM method. However, the anti-disturbance capability of the above two methods is poor, and the total harmonic distortion (THD) of the output waveform is high under unbalanced or distorted input voltages. The direct transfer function approach was adopted in [17]. The relations of the output voltages to input voltages, and the input currents to output currents can be defined by the switching matrix in terms of the switching action. As a result, the switching states can be determined directly according to the relation. Even if the input voltages are unbalanced or distorted, a good output performance can be achieved by this method. However, the computation is complex when compared with other methods.

The DLVS strategy has not been applied in the modulation approaches for the three-to-five phase DMC. In this paper, based on the topology and operational principles of the three-to-five phase DMC, a DLVS strategy is proposed. According to the segments of the input and output reference voltages, the input line voltages and source key should be selected reasonably to synthesize the output voltages. The advantages of the proposed DLVS strategy are that the output voltages and currents are sinusoidal and symmetrical under unbalanced or distorted input voltages, and the calculation of the duty ratio is very simple. In addition, the CMV can also be reduced by rearranging some of the switching states. In order to show the validity of the proposed DLVS strategy, simulation models and an experimental platform are established.

Ⅱ. OPERATIONAL PRINCIPLES OF THE DLVS STRATEGY

A. Topology of the Three-to-Five Phase DMC

The topology of the three-to-five phase DMC is illustrated in Fig. 1. It can be seen that it has fifteen bidirectional switches connecting the input with the output.\

Fig. 1. Three-to-five phase DMC topology.

u_a, u_b, u_c and i_a, i_b, i_c are the three-phase input voltages and currents respectively; i_A, i_B, i_C, i_D, i_E are the five-phase output currents; and R-L is the resistance-inductance load. R_f, L_f and C_f are the resistor, inductor and capacitor of the input filter. The bidirectional switches of the three-to-five phase DMC are defined by S_jk (j∈{A, B, C, D, E}; k∈{a, b, c}).

B. Division Principle of the Input and Output Segments

Assume that the input three-phase voltages are:

                   (1)

where U_im and ω_i are the amplitude and angular frequency of the input voltages, respectively. One period of the input voltages can be divided into six segments, as shown in Fig. 2. Each segment has common characteristics: two of the input phase voltages are positive or negative, while the polarity of the other one is opposite. x, y and z (x, y, z∈{a, b, c}) denote the corresponding phases that possess the maximum, medium, and minimum absolute values of the input voltages, respectively. Take segment 1 as an example. It can be divided into two parts equally. x, y, z denote a, b, c in the first part, and they denote a, c, b in the latter part.

Fig. 2. Segments of the input three-phase voltages.

Assume that the expected fundamental output voltages are:

                  (2)

where U_om and ω_o are the amplitude and angular frequency of the output phase voltages, respectively. The expected output five-phase voltages are divided into ten segments, as shown in Fig. 3. As can be seen, the dividing lines of the segments pass through the intersections of the phase voltages, and the values order of the phase voltages remain unchanged in each segment. Take segment Ⅰ and Ⅱ as an example. The dividing line passes through p₁ and p₂, and the values orders are and in Ⅰ and Ⅱ, respectively. The corresponding phases that possess the absolute values of the output voltages in descending order are denoted by U, V, W, X, and Y (U, V, W, X, Y∈{A, B, C, D, E}). Take segment Ⅰ as an example. It can also be divided into two parts equally. U, V, W, X, Y denote A, D, C, B, E in the first part, and they denote D, A, B, C, E in the latter part.

Fig. 3. Segments of the expected output five-phase voltages.

C. Operational Principles of the DLVS Strategy

In order to gain the maximum VTR, two larger input line voltages in every segment should be selected for synthesis. The following two cases are discussed.

1)

Three input line voltages can be used to synthesize the output voltages, the control function can be expressed as:

         (3)

where d_i1, d_i2, d_i3, d_i0 (i=1, 2, 3, 4) are the duty ratios of u_xy, u_xz, u_zy, u_xx within one sampling period, respectively, and their value range is [0, 1].

In addition, the relationship among these duty ratios can be described as follows:

           (4)

Define the value of each duty ratio is proportional to the input voltage, so that the duty ratios can be expressed as:

        (5)

where α₁, α₂, α₃, α₄ are the proportion coefficients of the corresponding voltages. Therefore, the duty ratios can be obtained by equation (3) and (5) as follows:

    (6)

where k is defined by:

     (7)

However, a line voltage can be indicated by the other two line voltages in the input side. In order to gain the maximum VTR, and to ensure the minimum switching number within one sampling period, the two input line voltages u_xy, u_xz and zero voltage u_xx are selected, and u_zy can be described as:

       (8)

The control function in equation (3) and duty ratios in equation (6) can be described as:

              (9)

 (10)

According to the control function described in (3), in the modulation, the switch S_Ux, which is defined as the “source key”, must always be kept on in the whole sampling period. At the same time, S_Uy and S_Uz must be kept off. When the output line voltage u* UV is synthesized, the switch S_Vy is kept in the ON state during the time (T_s is the sampling period), the switch S_Vz is kept in the ON state during the time , and the switch S_Vx is kept in the ON state during the time . The synthetic principles of the voltages u* UW, u* UX and u* UY are similar to those of the voltage u* UV. The input voltage in segment 1 and the output voltage in segment I are taken as an example. Then, the switching sequence can be rearranged as shown in Fig. 4.

2)

This case is similar to the case (1). However, in order to ensure the minimum switching number within one sampling period, the output line voltages u* VU, u* VW, u* VX and u* VY, are selected. Thus, the control function is as follows:

           (11)

The relationship of the duty ratios is the same with case (1). And the duty ratios in equation (11) are obtained as follows:

     (12)

Fig. 4. Switching sequence with output voltage synthesis.

where k is defined in equation (7), and the switch S_Vx is selected to be the “source key”.

All of the above equations are derived under balanced input voltages. When the input voltages are unbalanced or distorted, it is assumed that the unbalanced or distorted input line voltages are given by , and . The output voltage u_AB is obtained by:

      (13)

, and can be derived in the same way. Obviously, the control function based on the DLVS can be adjusted by itself under unbalanced or distorted input voltages. Therefore, sinusoidal and symmetrical output waveforms can also be obtained.

The output voltages are composed of input voltages, and the input currents can be synthesized by output currents. Take i_x in case (1) as an example. It can be described as:

         (14)

It can be obtained by equation (10) and (14) as follows:

    (15)

Where P_L is the five phase load power, which is defined by:

          (16)

It can be seen from equation (15) that when the input voltages are symmetrical, the input current i_x is equal to 3ku_xP_L, the input current is proportional to the input voltage and there is no phase difference between them. In addition, the unity input power factor can be achieved, and the input currents are distorted when the input voltages are unbalanced or distorted.

Ⅲ. SUPPRESSION OF COMMON MODE VOLTAGE BY THE IMPROVED STRATEGY

The common mode voltage (CMV) is the zero sequence component of the output voltages. The output voltages are high frequency pulse waves. As a result, the CMV is also a high frequency pulse wave. The CMV u_Ng is the voltage between the load neutral point and the ground as shown in Fig. 1. The circuit equation of the output side can be expressed as:

                 (17)

TABLE I  Values of the CMV under Different Switching States

Values of uNg	Ranges of uNg	| uNg |max
(ua+4ub)/5
(ua+3ub+uc)/5
(ua+2ub+2uc)/5
(ua+ub+3uc)/5
(ua+4uc)/5
(2ua+3ub)/5
(2ua+2ub+uc)/5
(2ua+ub+2uc)/5
(2ua+3uc)/5
(3ua+2ub)/5
(3ua+ub+uc)/5
(3ua+2uc)/5
(4ua+ub)/5
(4ua+uc)/5
ua

Since the five phase output currents are symmetrical, namely i_A+ i_B+ i_C+ i_D+ i_E=0, u_Ng can be derived by equation (17) as follows:

            (18)

Take the input voltage in segment 1 and the output voltage in segment Ⅰ as an example, and assume that the input voltages are balanced. There are many possible switching states. However, the values of u_Ng may be the same. Take S_Aa, S_Bb, S_Cb, S_Dc, S_Ec switch on and S_Aa, S_Bc, S_Cc, S_Db, S_Eb switch on as an example, u_Ng is equals to (u_a+2u_b+2u_c)/5 under the two switching states. On this basis, the values of the CMV under different switching states are listed in Table Ⅰ.

TABLE II  Simulation Parameters

Root mean square (RMS) of input phase voltage	100V
Input frequency	50Hz
Input filter	Rf=0.5Ω, Lf=1mH, Cf=20μF
Five-phase R-L load	R=16Ω, L=12mH
Switching frequency	10kHz
Root mean square (RMS) of output phase voltage	70V
Output frequency	20Hz

As can be seen from Table I, the absolute value of u_Ng reaches its maximum when the output phases all connected to the input phase a, and the output line voltages are all 0. In fact, the output line voltages can achieve 0 as long as the output phases all connected to the same input phase. In order to reduce the CMV, when the five phase output line voltages are all 0 in a switching cycle, the five output phases can be connected to the input phase which possesses the minimum absolute value in the three input phases.

In this improved strategy, the action of the switches remain unchanged as described in the last paragraph of part Ⅱ. C. (1), except that when the output line voltages should all be 0, and the concept of the “source key” disappears in this duration. By the improved strategy, the maximum value of the CMV can be effectively reduced to approximately 72% of the input phase voltage amplitude without affecting the quality of output. However, at the same time, the switching losses increase slightly due to the increase of switching times.

Ⅳ. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results

In order to verify the feasibility of the proposed DLVS strategy, a simulation of a three-to-five phase DMC based on Matlab/Simulink and S-function was carried out. The simulation analysis is divided into the following two cases.

1) Balanced Input Voltages

The parameters of the simulation model are listed in Table II.

The simulation results under balanced input voltages are shown in Figs. 5-8. Fig. 5 shows the waveform of the adjacent line-to-line voltage u_AB in (a), and its harmonics analysis in (b). It can be observed that the THD of the output line-to-line voltage is 120.73%. It can also be seen that it contains very little lower order harmonics, and that the higher harmonics with a larger amplitude are mainly concentrated near the switching frequency. In Fig. 6, the output five-phase currents are sinusoidal and symmetrical. This indicates that the fundamental output voltages are sinusoidal and symmetrical. Waveforms of u_Ng with the two strategies are shown in Fig. 7. The frequency of u_Ng is three times of the input frequency. The peak value of u_Ng with the unimproved strategy in (a) is about 140V, which is approximately equal to the amplitude of the input phase voltage. However, peak value of u_Ng with the improved strategy in (b) is about 100V, which is approximately 72% of the amplitude of the input phase voltage.

Fig. 5. Output adjacent line-to-line voltage u_AB under balanced input voltages and its harmonics analysis.

(a) Waveform of uAB.

(b) Harmonics analysis of uAB.

Fig. 6. Output phase currents under balanced input voltages.

Fig. 7. Waveforms of u_Ng with the two strategies under balanced input voltages.

Fig. 8. Input phase voltage and current under balanced input voltages.

Fig. 9. Unbalanced input voltages.

Fig. 10. Output adjacent line-to-line voltage u_AB under unbalanced input voltages and its harmonics analysis.

(a) Waveform of uAB.

(b) Harmonics analysis of uAB.

As shown in Fig. 8, the unfiltered input current is a pulse wave, and there is no angle difference between the input voltage and the unfiltered input current. However, the input filter causes a displacement angle between the input voltage and the filtered current. Despite this, the input power factor is close to the unity power factor.

2) Unbalanced or Distorted Input Voltages

The simulation parameters are the same as those in Table II except that the input voltages are unbalanced, and the RMS of the three phase input voltages are 90V/100V/110V, as shown in Fig. 9. The output results in Figs. 10-11 are similar to those under balanced input voltages. The shape of u_AB is irregular in Fig. 10(a) compared with that in Fig. 5(a).

Fig. 11. Output phase currents under unbalanced input voltages.

Fig. 12. Waveforms of u_Ng with the two strategies under unbalanced input voltages.

Fig. 13. Input currents under unbalanced input voltages.

However, the harmonics analysis shows that the output voltages hardly contains any lower order harmonics, and that the fundamental amplitudes are almost equal in the two cases. The output five-phase currents show that the output is still sinusoidal and symmetrical. The waveforms of u_Ng in Fig. 12 are not as regular as those in Fig. 7 because of the unbalanced input voltages. However, the relations are the same. The maximum value of u_Ng with the unimproved strategy reaches the maximum value of the input phase voltage, and improved strategy can reduce it to 72% of the maximum value. Since the MC does not have an energy dissipating element, and the converter loss is ignored, the average output power and input power are equal. Thus, the input three-phase currents are abnormal as shown in Fig. 13 because of the unbalanced or distorted input voltages. In addition, due to the unbalanced input voltages, there is a displacement angle between the input voltage and unfiltered input current in Fig. 14.

Fig. 14. Input phase voltage and current under unbalanced input voltages.

Fig. 15. Three-to-five phase DMC prototype.

Fig. 16. Three phase balanced input voltages.

B. Experimental Results

An experimental prototype of three-to-five phase DMC based on a DSP (TMS320F28335) and a FPGA (XC6SLX9) was implemented to verify the feasibility of the proposed DLVS strategy, as shown in Fig. 15. The input of the experimental prototype was connected to the power grid through a voltage regulator, and an input R-L-C filter was adopted to suppress the switching harmonics. The function of clamp circuit fitted between the input and the output is to protect the matrix converter against the overcurrent and overvoltage that occur on both sides of the converter. Each of the bidirectional switches of the main circuit is constituted by two MOSFETs and diodes, and the driving voltages of the switches supplied by the driver circuit are isolated from each other. The controller consists of two parts, a DSP for the proposed DLVS strategy and a FPGA for the switch commutation. The parameters of the experimental prototype are the same as those of the simulation. 

Fig. 17. Experimental results under balanced input voltages.

(a) Output adjacent line-to-line voltage.	(b) Output phase currents.
(c) Harmonics analysis of iA.	(d) CMV with the unimproved strategy.
(e) CMV with the improved strategy.	(f) Input phase voltage and current.

Fig. 18. Three phase unbalanced input voltages.

Three phase balanced input voltages are shown in Fig. 16, and the RMS of each phase is 100V. Fig. 17 shows experimental results under balanced input voltages. The output waveforms of the adjacent line-to-line voltages are shown in Fig. 17(a). As can be seen, the output voltages are high frequency pulse waves. It can also be observed that sinusoidal and symmetrical output currents are achieved under balanced input voltages from Fig. 17(b). In addition, the harmonics analysis of the phase current in Fig. 17(c) shows that there are little lower order harmonics and that the value of the THD is very small, which meets the expectations. The waveforms of the common mode voltage in Fig. 17(d) and Fig. 17(e) are in accordance with those of the simulation. The maximum value of the CMV can be reduced to 72% with the improved strategy. Fig. 17(f) presents the input phase voltage and current under balanced input voltages, phase angle of unfiltered input current is same as that of input voltage. The filtered input phase current is sinusoidal with very little distortion, and the current leads the voltage by a little displacement angle caused by the capacitive filter.

Three phase unbalanced input voltages are shown in Fig. 18. The RMS of each phase is 90V/100V/110V. Figs. 19-20 show experimental results under unbalanced input voltages, where Fig. 19 shows results with the proposed DLVS strategy, and Fig. 20 shows results with the conventional SVPWM strategy.

Similar output results are achieved under unbalanced input voltages with the proposed DLVS strategy, as shown in   Fig. 19. As displayed in Fig. 19(a), the waveform of the output adjacent line-to-line voltage is a little different from that under balanced input voltages because of the unbalanced input voltages. However, the output phase currents are still sinusoidal and symmetrical in Fig. 19(b), and the harmonics distributions are similar. It can be seen that unbalanced or distorted input conditions do not deteriorate the quality of the output. Waveforms of common mode voltage are also similar to those of the simulation. The maximum absolute values of the CMV under the two strategies are about 155V and 110V, respectively. Fig. 19(f) gives the input phase voltage and current under unbalanced input voltages. There is also a displacement angle, and the distortion of the input current under unbalanced input voltages is worse due to the unbalanced input voltages.

Fig. 19. Experimental results under unbalanced input voltages.

(a) Output adjacent line-to-line voltage.	(b) Output phase currents.
(c) Harmonics analysis of iA.	(d) CMV with the unimproved strategy.
(e) CMV with the improved strategy.	(f) Input phase voltage and current.

Fig. 20. Experimental results under unbalanced input voltages with the SVPWM strategy.

(a) Output phase currents.	(b) Harmonics analysis of iA.
(c) CMV with the SVPWM strategy.

Furthermore, an experiment was conducted with the conventional SVPWM strategy under unbalanced input voltages. Fig. 20(a) and Fig. 20(b) clearly show that the output phase currents are no longer sinusoidal, and there are low-order harmonics in the waveform. The output waveforms are heavily distorted when the degree of unbalance increases. The shape of the CMV in Fig. 20(c) is different from that under the proposed DLVS strategy. However, the maximum absolute value of the CMV is about 155V, which is equal to the maximum value under the unimproved DLVS strategy proposed in this paper.

The experiment results matched expectations and they are consistent with the theoretical analysis and simulation.

Ⅴ. CONCLUSION

In this paper, a DLVS strategy is proposed that is suitable for the three-to-five phase DMC. In order to gain the maximum VTR, two larger input line voltages should be selected for synthesis. The duty ratios are calculated by the input voltages and the expected output voltages. The calculating process is very simple. Moreover, in order to reduce the number of switchings within one sampling period, the source key is selected reasonably in each of the input and output intervals. The feasibility and validity of the proposed method were verified by means of computer simulations and experiments. The results of the simulations and experiments all show that both the output voltages and the input currents can be effectively modulated when the input voltages are sinusoidal and symmetrical. In addition, the output voltages and currents are still sinusoidal and symmetrical with little lower order harmonics under unbalanced or distorted input voltages, desirable output can be achieved under different input conditions, and the CMV can be effectively reduced by rearranging some of the switch states at the price of the switching loss slightly increasing.

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Rutian Wang was born in Weifang, China, in 1979. He received his B.S. and M.S. degrees in Power Systems and its Automation at the Northeast China Institute of Electric Power, Jilin, China, in 2002 and 2005, respectively; and his Ph.D. degree in Power Systems and its Automation at the Harbin Institute of Technology, Harbin, China, in 2009. He is presently working as an Associate Professor and a M.S. Supervisor in the School of Electrical Engineering, Northeast Electric Power University, Jilin, China. His current research and teaching interests include high efficiency electric energy conversion, and the application of power electronic technology in power systems.

Yanfeng Zhao was born in Chengde, China, in 1991. He received his B.S. degree in Electrical Engineering and Automation at the Zhongyuan University of Technology, Zhengzhou, China, in 2015. He is presently working towards his M.S. degree in Electrical Engineering at the Northeast Electric Power University, Jilin, China. His current research interests include control theory and the application of matrix converters.

Xingjun Mu was born in Shangqiu, China, in 1987. He received his B.S. degree in Electrical Engineering and Automation at the Henan Polytechnic University, Jiaozuo, China, in 2014; and his M.S. degree in Electrical Engineering at the Northeast Electric Power University, Jilin, China, in 2017. He is presently working at the Fujian Yongfu Power Engineering Co., Ltd, Fuzhou, China.

Weiquan Wang was born in Dandong, China, in 1993. He received his B.S. degree in Electronical Information Science and Technology at the Northeast Electric Power University, Jilin, China, in 2015, where he is presently working towards his M.S. degree in Electrical Engineering. His current research interests include control theory and the application of matrix converters.