https://doi.org/10.6113/JPE.2018.18.1.116

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Fundamental Output Voltage Enhancement of Half-Bridge Voltage Source Inverter with Low DC-link Capacitance

Ahmed Elserougi^†,*, Ahmed Massoud^**, and Shehab Ahmed^***

^†,**Department of Electrical Engineering, Qatar University, Doha, Qatar

^*Department of Electrical Engineering, Alexandria University, Alexandria, Egypt

^***Department of Electrical and Computer Engineering, Texas A&M University at Qatar, Doha, Qatar

Abstract

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors’ voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors’ voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

Key words: Enhanced output voltage, Half-bridge voltage source inverter, Low dc-link capacitances

Manuscript received Apr. 17, 2017; accepted Aug. 16, 2017

Recommended for publication by Associate Editor Yijie Wang.

^†Corresponding Author: ahmed.elserogi@qu.edu.qa  Tel: +974-55184657, Qatar University

^*Dept. of Electr. Eng., Alexandria Univ., Egypt

^**Dept. of Electr. Eng., Qatar Univ., Qatar

^***Dept. of Electr. & Computer Eng., Texas A&M Univ. at Qatar, Qatar

Ⅰ. INTRODUCTION

CONVENTIONAL two-level Half-Bridge Voltage Source Inverter (HB-VSI), shown in Fig. 1(a), is one of the most common VSIs which can be used in various applications [1]-[6]. The HB-VSI has a limited ac output voltage magnitude, i.e. voltage buck capability. When sinusoidal pulse width modulation is employed, by varying the peak of the modulating signal (M) from zero to unity, the ac output voltage magnitude varies linearly from zero to half of the dc input voltage (0.5V_dc). Then by increasing M above unity, a higher output voltage magnitude, but with low order harmonics, is generated (over modulation). Increasing M more saturates the output voltage, and a square waveform with a fundamental output voltage magnitude of 2V_dc/π is obtained. This represents the maximum achievable value of the fundamental output voltage magnitude in the HB-VSI [7]. If a higher ac output voltage value is required, typically a boosting circuit between the dc source and the dc-link capacitors or a step-up transformer at the output stage can be added [1], [8]. The main drawback of these solutions is adding a further hardware stage, which affects negatively the system cost, efficiency and reliability [9, 10]. On the other hand, Z-source HB-inverter has been proposed in [8, 11] to enhance the fundamental output voltage of the HB-VSI efficiently. Yet, passive elements have to be added.

In HB-VSI, the load current circulates through the two dc- link capacitors, which results in capacitor voltage fluctuations (ac components) generating distorted output voltage [12, 13]. Conventionally, to reduce these fluctuations, large and bulky dc-link electrolytic capacitors, with a short lifetime, are employed. In HB-VSI, the voltage of each capacitor of the dc-link has typically a dc component, an ac component with the fundamental frequency, and insignificant high frequency components which can be neglected. Therefore, the dc component and the ac component with the fundamental frequency are only considered throughout this paper.

Fig. 1. HB-VSI with low dc-link capacitances (a) single-phase topology, (b) corresponding voltages of the dc-link capacitors at C_dc>C_cr, (c) corresponding voltages of the dc-link capacitors at C_dc=C_cr, and (d) three-phase version of low capacitances HB-VSI.

(a)

(b)

(c)

(d)

In this paper, employing low dc-link capacitances with small size, is investigated to enhance the fundamental output voltage magnitude of the HB-VSI. This is constrained to inductive loads, which is the most common ac load. When low dc-link capacitances are employed, the effect of the corresponding ac components of dc-link capacitors’ voltages is considerable. These ac components may enhance the fundamental component magnitude of the HB-VSI output voltage (based on the value of the load Displacement Factor (DF) as will be shown in the following sections). Employment of low dc-link capacitances yields a distorted load voltage. Nevertheless, the load current is maintained sinusoidal with the fundamental frequency. Operating with low dc-link capacitances influences positively the system cost and lifetime as non-electrolytic dc-link capacitors can be employed [14], [15]. Mathematical analysis of the proposed approach is presented in this paper for single-phase as well as three-phase systems by employing one and three single-phase HB-VSI(s), respectively.

Moreover, a detailed illustration for designing the dc-link capacitors is presented.

The dc-link capacitances should be properly selected to ensure unipolar voltages across the dc-link capacitors, i.e. their values should be larger than the capacitance at which the peak of ac component of the capacitor voltage reaches 0.5V_dc. For given specifications, a flow chart is presented in this paper to select the proper dc-link capacitances. Finally, simulation and experimental results are presented to validate the proposed approach. The main advantages of the proposed approach can be summarized as follows:

(ⅰ) The proposed approach provides an enhanced fundamental output voltage magnitude compared to the high dc-link capacitances-based HB-VSI especially for inductive loads with low DF,

(ⅱ) The proposed approach provides operating with switches rated at the dc input voltage regardless of capacitor voltage fluctuation which affects positively the inverter voltage rating,

(ⅲ) Low dc-link capacitances allows employment of non-electrolytic capacitors which affects positively on the overall cost and lifetime of the inverter.

Ⅱ. AC COMPONENTS OF HB-VSI DC-LINK CAPACITORS WITH LOW CAPACITANCES

In this section, the analysis of the ac components of single-phase HB-VSI dc-link capacitors with low capacitances, is presented. This analysis can be extended as well to the multi-phase HB-VSI due its modularity. Based on Fig. 1(a), using sinusoidal pulse width modulation, a bipolar output voltage (+/-0.5V_dc) appears across the load. This results in a sinusoidal load current with harmonic components that depend on the load DF, modulation index and modulation frequency ratio. The load current is divided into two currents, as shown in Fig. 1(a), namely (i₁ and i₂) which represent the currents of dc-link capacitors. As the fundamental component of each dc-link capacitor current (i_1F or i_2F) results in the main ac component of the capacitor voltage respectively, only the fundamental component of the output current will be considered in the following analysis (i.e. the effect of the harmonic components will be neglected).

The load current (i_o) circulates through the dc-link capacitors (C_dc) as shown in Fig. 1(a). This results in anti- phase ac voltage components across the dc-link capacitors as shown in Fig. 1(b) (assuming inductive load). It is clear that the voltage of each capacitor has two components (dc and ac components). The dc components of the capacitors’ voltages equal 0.5V_dc, while the phasors of the ac components can be expressed as follows,

        (1)

        (2)

where and are the fundamental components of the currents and , respectively, and is the angular frequency of the output voltage. The fundamental component of the currents and equals , where is the fundamental component of the output current.

From (1) and (2), and for a load current with a fundamental component of , the corresponding ac components of the dc-link capacitors’ voltages are given by,

    (3)

          (4)

where I_m is the peak of the fundamental output current component, and is the phase angle of the load current. Based on (3) and (4), it is clear that:

(i) The two components are anti-phase and their summation equals zero, i.e. as shown in Fig. 1(b). This means that the voltage ratings of the involved switches are not influenced by the fluctuation of the capacitors’ voltages.

(ii) The peak of the dc-link capacitors’ voltages ac components can be expressed by,

    (5)

i.e., the ac component peak of the capacitor voltage mainly depends on the peak of the fundamental component of the load current, dc-link capacitance (C_dc), and the angular frequency of the load voltage.

To have a unipolar voltage across each of the dc-link capacitors, the peak of the dc-link capacitors’ voltages ac component should be lower than 0.5V_dc, i.e.

         (6)

where C_cr is the critical capacitance which is defined as the lowest dc-link capacitance that can be employed for unipolar capacitor voltages. The corresponding voltage fluctuations of the dc-link capacitors at the critical value of the dc-link capacitances are shown in Fig. 1(c) assuming inductive load (i.e. ac component peak equals 0.5V_dc).

The three-phase version of the low dc-link capacitances based HB-VSI is shown in Fig. 1(d), which consists of three single-phase HB-VSI. The three-phase version can be used in three-phase motor drive systems with open winding motors. Also, it can be used for integrating photovoltaic systems with the three-phase electric power grid through an open winding transformer.

Ⅲ. OPERATION OF HB-VSI FEEDING AN INDUCTIVE LOAD WITH ENHANCED OUTPUT VOLTAGE MAGNITUDE

In this section, the operation and analysis of the HB-VSI, feeding an inductive load with enhanced output fundamental voltage, are presented.

A. Mathematical Analysis

Assume the following conditions,

⋅Modulating signal =, where .

⋅Load impedance (inductive load) =.

⋅, where V_o1 is the fundamental component of the output voltage, and V_o1 and are its magnitude and phase angle (which depends on the operational conditions), respectively. The expressions for the fundamental output voltage magnitude and phase angle will be found in the following analysis.

⋅The ac component of the capacitor voltage depends on the fundamental ac current that passes through the capacitor which is 0.5i_o1, i.e. the corresponding ac component can be expressed by,

     (7)

This component impacts the load voltage shape, i.e. the fluctuation appears on the load voltage as shown in Fig. 2(a), assuming 3 kHz switching frequency. On the other hand, if high dc-link capacitances are employed, the load voltage will be as shown in Figs. 2(b), assuming 3 kHz switching frequency.

Based on Figs. 2(c) and 2(e), the output voltage at low C_dc can be expressed as a summation of two terms as in (8). The first term () represents the output voltage when high dc-link capacitances are employed, while the second term represents the ac component of the upper dc-link capacitor ().

    (8)

Fig. 2. Effect of the value of C_dc on the shape of the output voltage (a) low capacitance, (b) high capacitance, (c) relation between the output voltages at low and high dc-link capacitances, (d) phasor diagram in case of high dc-link capacitances and (e) phasor diagram in case of low dc-link capacitances .

(a)	(b)
(c)
(d)	(e)

Equation (8) can be re-written as follows,

           (9)

i.e.,

      (10)

By equating the real and imaginary terms, the following equations can be extracted,

    (11)

    (12)

For a given input dc voltage, peak of modulating signal, load impedance, and dc-link capacitances, equation (12) can be used to obtain the value of , then substituting in (11), the value of V_o1 can be obtained. For a given operational data, the dc-link capacitances should be selected higher than the critical capacitance to ensure unipolar capacitor voltages. The critical capacitance can be expressed as a function of the fundamental output voltage magnitude as follows,

      (13)

As V_o1 depends on the selected value of dc-link capacitances, the flow chart that can be used to select the dc-link capacitance is presented as shown in Fig. 3.

B. Numerical Example

Based on the aforementioned mathematical relations and for M = 1, ω = 100π rad/s, V_dc = 100V, Z=5Ω, ϕ = 45^o, and C_dc = 1mF;

The corresponding V_o1 equals 62V. It is clear that the output voltage magnitude>50V, where 50V represents the fundamental output voltage magnitude in case of HB-VSI with high dc-link capacitances. So the corresponding enhancement of the fundamental output voltage magnitude equals 24% in the presented case. The corresponding C_cr equals 0.4 mF (i.e., C_dc > C_cr). While, the corresponding θ equals 16.2^o. Finally, the peak of ac component of the capacitor voltage equals 19.7V.

To validate the aforementioned calculation, a simulation model has been built for a single-phase HB-VSI with the aforementioned specifications, and the corresponding simulation results are shown in Fig. 4 assuming 3 kHz switching frequency. Based on Fig. 4, it is clear that the simulation results are identical to the calculated values.

Fig. 3. Flowchart to select proper dc-link capacitances.

Fig. 4. Simulation results of the given numerical example. (a) voltages of the dc-link capacitors and their summation and (b) actual and filtered output voltage.

(a)

(b)

Fig. 5. Effect of dc-link capacitance and lagging load DF on the enhancement of the fundamental output voltage magnitude and other system variables for M=1, V_dc=100 V, and Z=5 Ω at 50 Hz. (a) V_o1/V_dc versus dc-link capacitance, (b) θ versus dc-link capacitance, (c) peak of ac component/0.5V_dc versus dc-link capacitance, and (d) critical capacitance versus dc-link capacitance.

(a)

(b)

(c)

(d)

Fig. 6. Effect of load impedance magnitude on V_o1 at 0.5 lagging load DF and different values of dc-link capacitances.

C. Effect of dc-link Capacitance and Load on the Fundamental Output Voltage Magnitude

In this section, the effect of the dc-link capacitances and load on the enhancement of the fundamental output voltage magnitude is presented.

Based on the aforementioned equations, and for V_dc = 100V, M = 1, Z = 5Ω (inductive load) and ω=100π rad/s, the variation of peak of the fundamental output voltage, phase angle of the fundamental output voltage, and the peak of ac component of the capacitor voltage with the variation of the dc-link capacitance (C_dc) for different load DFs are shown in Figs. 5(a)-5(c).

Based on (13), the corresponding critical capacitances for different cases are shown in Fig. 5d. It is clear that enhanced output voltage magnitude increases with the decreasing of dc- link capacitances. It is also clear that the dc-link capacitance is higher than the critical capacitance in all cases (Fig. 5(d)) to ensure unipolar capacitor voltage.

On the other hand, Fig. 6 shows the effect of load impedance magnitude on the enhancement of the fundamental output voltage magnitude at 0.5 lagging load DF. Based on the results shown in Figs. 5 and 6, the following points can be concluded:

(i) It is clear from Fig. 5(a) that there is a limited or no enhancement for the fundamental output voltage magnitude in case of load with high lagging load DFs. The main reason for that is the phase angle and the magnitude of the fundamental ac component of the capacitor voltage which mainly depend on the load angle as shown in Fig. 7. The actual and filtered output voltage at unity load DF and 0.5 lagging load DF are shown in Figs. 7(a) and 7(b) respectively.

(ii) Based on Fig. 5, for a relatively low and lagging load DFs, as dc-link capacitance decreases (but still above the critical value), the peak of fundamental output voltage increases, i.e. the proposed approach is more beneficial when feeding loads with low lagging load DFs.

(iii) Based on Fig. 6, as the load impedance magnitude increases, the enhancement in the fundamental output voltage magnitude decreases because the load current decreases, which results in decreasing the ac component of dc-link capacitor voltage.

Fig. 7. Actual and filtered output voltage at different load DFs (a) unity DF, (b) 0.5 lagging DF.

(a)

(b)

Fig. 8. Gain versus M for different values of dc-link capacitance (C_dc) assuming an input dc voltage of 100 V, and Z=5 Ω, load angle ɸ=45^o at 50 Hz.

D. Assessment of the HB-VSI with Low dc-link Capacitances.

In this subsection, the low dc-link capacitances based HB-VSI is compared with the high dc-link capacitances based HB-VSI in terms of (i) gain versus M, and (ii) voltage rating of the involved switches. In this assessment, a simulation model has been built for the HB-VSI with input dc voltage of 100V, and Z= 5Ω, ɸ = 45^o at 50Hz. This model has been run multi-times to check the variation of the fundamental output voltage peak (V_o1) with the variation of (M) for two different cases (C_dc =10 mF, and C_dc=1 mF). The corresponding result is shown in Fig. 8.

With respect to the relation between gain and M and based on Fig. 8, it is clear that;

(i) Both relations have linear region till M=1, then they go into saturation region (i.e., over modulation effect).

(ii) Higher voltage can be obtained from the HB-VSI with lower dc-link capacitance (i.e. operation with enhanced fundamental output voltage magnitude), as the output voltage enhancement is clearly shown in Fig. 8.

With respect to the voltage rating of the involved switches in both cases, based on Fig. 8, for V_o1=70V and M=1; the required input dc voltage in each case can be estimated as follows;

(i) In case of high dc-link capacitances (C_dc=10 mF), at M=1, the gain equals 0.52, i.e. for V_o1=70V, the suitable V_dc is 135 V.

(ii) In case of low dc-link capacitances (C_dc=1 mF), at M=1, the gain equals 0.63, i.e. for V_o1=70V, the suitable V_dc is 110 V.

As the involved switches are rated at the input dc voltage, the switches in the case of low dc-link capacitances will have a lower voltage rating for the same output voltage which affects positively on the converter cost. On the other hand, with respect to the efficiency, the conduction losses (P_c) and switching losses (P_sw) of the HB-VSI leg are given by (14) and (11) respectively [16],

         (14)

        (15)

where V_T0 and R_T0 are the on-state voltage and resistance of the IGBTs, V_D0 and R_D0 are the on-state voltage and resistance of the anti-parallel diodes, I_m is the peak of module output current, f_sw is the switching frequency, t_on is the IGBT turn-on, t_off is the IGBT turn-off time, and V_DC is the input dc-link voltage. Based on (14), if the load current magnitude (I_m) is controlled to be constant at a certain level in both cases (low and high dc-link capacitances) and identical switches with the same on-state voltage and resistance are employed, the conduction losses in both cases will be the same. On the other hand, based on (15), the switching losses in case of low dc-link capacitance HB-VSI will be lower since the HB-VSI with low dc-link capacitances needs lower dc-link voltage to generate the same output current peak, i.e. it will offer higher efficiency.

Ⅳ. CLOSED LOOP CURRENT CONTROLLER FOR THE PROPOSED APPROACH

In this section, the presented approach is assessed through closed loop operation. Fig. 9 shows the per-phase current controller of the proposed approach, where T is the periodic time of output voltage and current. The per-phase current controller is responsible for maintaining the direct and quadrature current components within the desired levels. The current controller of the proposed approach is based on the conventional Proportional-Integral (PI) based current controller for single-phase systems. In the presented current controller, the phase current is measured and transformed into dq components (i_d and i_q). Then the reference of direct and quadrature components (i_{d ref} and i_{q ref}) compared with their actual values (i_d and i_q ), and the error signals are fed to the PI controllers. The outputs of PI controllers are the reference direct and quadrature components of the modulating signal (m_d and m_q) which can be transformed into αβ components (m_α and m_β). The α-component (m_α) represents the reference modulating signal for the involved HB-VSI. Finally, the generated modulating signal is used to generate the gate pulses of this phase switches by employing sinusoidal pulse width modulation. In three-phase systems, this current controller should be applied to the other phases with the same concept, but shifted by -120^o and +120^o.

Fig. 9. The per-phase current controller of the proposed approach.

Fig. 10. Performance of the per-phase closed loop current controller for the presented numerical example (a) output voltage, (b) voltages of dc-link capacitors (c) modulating signal, and (d) load current and its dq-components.

(a)

(b)

(c)

(d)

To show the performance of the per-phase controller, Fig. 10 shows the variation of output voltage, output current, modulating signal, and voltages of dc-link capacitors assuming the following parameters: (V_dc = 100V, C= 1mF, Z = 5Ω, ϕ= 45^o, ω = 100π rad/s, 10 kHz carrier signal, i_{d ref} = 12.5A, i_{q ref} = 0 A, and PI constants of k_p = 0.2 and k_i = 2). It is clear that enhanced output current with good quality is generated with the low-dc link-based HB-VSI at unity peak modulating signal.

It has to be noted that in case of high dc-link capacitances HB-VSI, the unity peak modulating signals is able to generate sinusoidal current of 10 A with good quality, i.e. 25% enhancement is achieved with employing low-dc link capacitances assuming a unity peak modulating signal in both cases. To generate the same fundamental component (12.5A)

in case of high-dc link capacitances (10 mF) HB-VSI, the inverter should be operated in the over modulation region, hence a distorted output current is generated as shown in Fig. 11.

Fig. 11. Comparison between the output current at low and high dc-link capacitance HB-VSIs for the presented numerical example.

The THD of the load current in case of low and high capacitance in case of fundamental peak of 12.5A equals 0.45% and 8.87% respectively.

Ⅴ. SIMULATION OF THREE PHASE HB-VSI

A simulation model has been built for three-phase HB-VSI (shown in Fig. 1(d)) to show the performance of three-phase HB-VSI with low dc-link capacitances. The simulation parameters are given in Table I.

TABLE I  Simulation Parameters

DC input voltage, Vdc	100 V series with 0.2 Ω
No. of dc-link capacitors	6 (2 per each phase)
DC-link capacitance (Cdc)	1 mF
Load impedance at 50 Hz	5∟45o per phase
Carrier frequency	10 kHz

A. Open Loop Control

Firstly, the performance of the proposed approach has been tested using unity peak three-phase modulating signals. The corresponding simulation results are shown in Fig. 12. Figs. 12(a) and 12(b) show the actual and filtered output voltages. It is clear nt of the fundamental output voltage magnitude (24% in the presented case) compared to the high dc-link cathat there is an enhancemepacitances based HB-VSI.

Fig. 12(c) shows the phase currents, as the currents are pure sinusoidal and there is no effect from the capacitor voltage fluctuation on the quality of the output currents. Fig. 12(d) shows the current at the dc side (i_dc in Fig. 1(d)). It is clear that a constant current is drawn from dc source, which is an important issue in some application such as PV and fuel cell applications. Finally, Fig. 12(e) shows the voltages of dc-link capacitors. It is clear that the ac components of the dc-link capacitors in each phase are anti-phase, so the summation of the voltages of the dc-link capacitors of each phase equals the input dc voltage (V_dc), i.e. voltage enhancement is achieved without increasing the voltage rating of the involved switches.

Fig. 12. Simulation results for three-phase load (a) actual output voltages, (b) filtered output voltages, (c) phase currents, (d) dc current, and (e) voltages of the dc-link capacitors.

(a)

(b)

(c)

(d)

(e)

B. Closed Loop Control

In this subsection the performance of the proposed closed loop current controller is tested by varying the direct current reference from 12.5A to 6.25A at t=0.5s, assuming zero quadrature current component. The corresponding simulation results are shown in Fig. 13.

Fig. 13(a) shows the variation of three-phase modulating signals with the operation, while Fig. 13(b) shows the three- phase load currents and their per-phase direct and quadrature components. Finally, the corresponding capacitors’ voltages are shown in Fig. 13(c).

It is clear that the voltage fluctuations decrease with the decrease of current magnitude. Based on the presented results, the proposed controller is able to track the current reference successfully.

Fig. 13. Simulation results for the closed loop controller testing. (a) Modulating signals, (b) load currents, and (c) capacitors’ voltages.

(a)

(b)

(c)

Ⅵ. EXPERIMENTAL VALIDATION

A simple single-phase HB-VSI has been used for experimental verification (Fig. 14) with the parameters shown in Table II. Two values of dc-link capacitance (C_dc) have been considered (450µF and 4700µF) to show the difference between the low and high dc-link capacitances.

Fig. 14. Experimental setup.

A. Open Loop Control

In this mode, a modulating signal with unity peak is applied.

The corresponding experimental results for low and high dc-link capacitances along with FFT for the load currents are shown in Figs. 15 and 16 respectively.

It has to be noted that both values are greater than the critical capacitance, i.e. the peak of ac component of the capacitor voltage is less than 0.5V_dc). The flow chart shown in Fig. 3 can be used to check that the selected values are greater than the critical capacitance value. Figs. 15(a) and 16(a) shows the variation of the voltages of dc-link capacitances. It is clear that the ac components of capacitors’ voltages are anti-phase and their summation equals zero. Fig. 15(c) and 16(c) sows the load currents, it is also clear that the load currents in both cases are sinusoidal.

Fig. 15. Experimental results for low dc-link capacitance case. (a) voltages of the dc-link capacitor, (b) load voltage, (c) the load current, and (d) FFT for the load current.

(a)

(b)

(c)

(d)

The current spikes (high frequency pulsating current) shown in the load currents (Figs. 15(c) and 16(c)) are due to device switching as high dv/dt and di/dt are the major sources of EMI noise with the existence of parasitic elements such as dc-link capacitor series inductance, and circuit stray capacitances/inductances [17]. As the current in the case of low dc-link capacitances is higher, a higher noise is expected with the switching. The FFT for the load current in case is shown in Figs. 15(d) and 16(d) respectively.

Fig. 16. Experimental results for high dc-link capacitance case. (a) voltages of the dc-link capacitor, (b) load voltage, (c) the load current, and (d) FFT for the load current.

(a)

(b)

(c)

(d)

TABLE II  Experimental Setup Parameters

Input dc voltage, Vdc	100 V
Load (RL inductive load)	R=6 Ω, and L=10mH
Frequency of the Carrier	5 kHz
Modulating signal (open loop)	1 sin (100π t)
DC-link capacitances	Case 1: 450µF, Case 2: 4700µF

Fig. 17. Experimental results for the closed loop control (a) high dc-link capacitances case, (b) low dc-link capacitances case.

(a)

(b)

Based of Figs. 15d and 16d, it is clear that both currents have almost the same THD. On the other hand, the magnitude of fundamental load current in case of low dc-link capacitances based HB-VSI is 7.1 A which is greater than its value in case of high dc-link capacitances based HB-VSI (6.134 A). This confirms the enhancement of the fundamental output voltage magnitude with the low dc-link capacitances based HB-VSI. The enhancement of the fundamental output voltage magnitude in the presented experimental results is 15.7%.

B. Closed Loop Control

The performance of the HB-VSI with low and high dc-link capacitances is investigated when the closed loop controller (shown in Fig. 9) is applied. A step reference is defined for the ac output current peak (step change from 5A to 2.5A) with PI constants of k_p=0.2 and k_i=8. The corresponding simulation results for the high and low dc-link capacitances are shown in Figs. 17(a) and 17(b), respectively. It is clear that; (i) the ac output current is generated as desired successfully in both cases, and (ii) the voltage fluctuations decrease with the decrease of current magnitude.

Ⅶ. CONCLUSION

In this paper, the performance of the low dc-link capacitances based HB-VSI has been presented. The main advantages of the proposed approach are:

(ⅰ) Enhanced fundamental output voltage magnitude compared to the high dc-link capacitances based HB-VSI when feeding an inductive load (especially at low load DF),

(ⅱ) Operating with switches rated at the dc input voltage regardless of capacitor voltage fluctuation which influences positively on the inverter cost and efficiency compared to the high dc-link capacitances based HB-VSI assuming the same fundamental output voltage magnitude, and

(ⅲ) Operating with low dc-link capacitances allows the employment of non-electrolytic capacitors which impacts positively on the overall cost and lifetime.

A detailed mathematical analysis of the proposed approach has been presented along with its closed loop current controller. To ensure unipolar capacitor voltage, the selected dc-link capacitor should be greater than the critical capacitance. A flow chart, which can be used to check if the selected dc-link capacitance is suitable or not, has been presented as well. Moreover, a family of curves describing the relation between system variables have been also presented in this paper. Simulation results have been presented to show the viability of the proposed approach in three-phase systems. Finally, experimental validation using single-phase HB-VSI has been made to show the possible enhancement in the output voltage magnitude when low dc-link capacitances are employed.

ACKNOWLEDGMENT

This publication was made possible by NPRP grant NPRP (9-092-2-045) from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors.

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Ahmed Elserougi was born in Alexandria, Egypt, in September 1982. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the Faculty of Engineering, Alexandria University, Egypt, in 2004, 2006, and 2011, respectively. From September 2012 to May 2017, he was a Research Fellow at Texas A&M University at Qatar. He is currently a Research Fellow at the College of Engineering, Qatar University, Doha, Qatar. He is also an Associate Professor in the Electrical Engineering Department, Faculty of Engineering, Alexandria University. His research interests include Power Quality, HVDC and FACTS, Renewable Energy, Electric Power Utility, and Pulsed Power Applications.

Ahmed Massoud received the B.Sc. (first class hons.) and M.Sc. degrees from the Faculty of Engineering, Alexandria University, Alexandria, Egypt, in 1997 and 2000, respectively, and the Ph.D. degree from the Department of Computing and Electrical, Heriot-Watt University, Edinburgh, U.K., in 2004, all in electrical engineering. From 2005 to 2008, he was a Research Fellow at Strathclyde University, Glasgow, U.K. From 2008 to 2009, he was a Research Fellow at Texas A&M at Qatar, Doha, Qatar. From 2009 to 2012, he was an Assistant Professor at the Department of Electrical Engineering, College of Engineering, Qatar University, Doha, Qatar, where he is currently an Associate Professor in the Department of Electrical Engineering. His research interests include power electronics, energy conversion, renewable energy and power quality.

Shehab Ahmed was born in Kuwait in July 1976. He received the B.Sc. degree from Alexandria University, Alexandria, Egypt, in 1999, and the M.Sc. and Ph.D. degrees from the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA, in 2000 and 2007, respectively, all in electrical engineering. From 2001 to 2007, he was with Schlumberger Technology Corporation working on downhole mechatronic systems. He is currently an Associate Professor at Texas A&M University at Qatar, Doha, Qatar. His research interests include mechatronics, solid-state power conversion, electric machines, and drives.