https://doi.org/10.6113/JPE.2018.18.1.277

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Compact Wireless IPT System Using a Modified Voltage-fed Multi-resonant Class EF₂ Inverter

Mohammad Kamar Uddin^*, Saad Mekhilef^†, and Gobbi Ramasamy^**

^*,†Power Electronics and Renewable Energy Research Laboratory (PEARL), Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia

^**Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia

Abstract 

Wireless inductive power transfer (IPT) technology is used in many applications today. A compact and high-frequency primary side inverter is one of the most important parts of a WPT system. In this study, a modified class EF-type voltage-fed multi-resonant inverter has been proposed for WPT application at a frequency range of 85–100 kHz. Instead of an infinite input choke inductor, a resonant inductor is used to reduce loss and power density. The peak voltage stress across the MOSFET has been reduced to almost 60% from a class-E inverter using a passive clamping circuit. A simple yet effective design procedure has been presented to calculate the various component values of the proposed inverter. The overall system is simulated using MATLAB/SimPowerSystem to verify the theoretical concepts. A 500-W prototype was built and tested to validate the simulated results. The inverter exhibited 90% efficiency at nearly perfect alignment condition, and efficiency reduced gradually with the misalignment of WPT coils. The proposed inverter maintains zero-voltage switching (ZVS) during considerable load changes and possesses all the inherent advantages of class E-type inverters.

Key words: Class E inverter, Class EF inverter, High-frequency inverter, Inductive power transfer, Misalignment tolerance

Manuscript received Feb. 7, 2017; accepted May 30, 2017

Recommended for publication by Associate Editor Yijie Wang.

† Corresponding Author: saad@um.edu.my  Tel: +603-79676851, Fax: +603-79675316, University of Malaya

* Power Electronics and Renewable Energy Research Lab. (PEARL), Department of Electrical Engineering, Univ. of Malaya, Malaysia

** Faculty of Engineering, Multimedia University, Malaysia

Ⅰ. INTRODUCTION

Wireless power transfer (WPT) is an emerging research area that shows great potential to redefine the way electrical power is consumed by communities. Among the various types of WPT methods, inductive power transfer (IPT) or resonance inductive power transfer (RIPT) has gained increasing popularity and research attention over the last decade. Studies in the implementation of IPT systems on various applications, ranging from low-power level (1 W) to medium-power level (> 1 kW), have been increasing.

Biomedical devices and sensors, electric appliances, portable devices, automotive assembly lines, clean factories, industrial automation applications, and electric vehicle (EV) charging are the most attractive application areas, considering the aforementioned power levels. Some of these applications operate at relatively higher frequency (>500 kHz to several MHz) and shorter distance (up to 3 cm), whereas others operate at a lower frequency (<200 kHz) and greater distance (10–30 cm) [1], [2].

In a typical IPT/WPT system, a high-frequency inverter delivers high-frequency, time-varying voltage/current to a primary coil, which induces a time-varying magnetic field. This magnetic field travels over a distance to energize a secondary coil to transfer power. Subsequently, the induced secondary voltage is conditioned to deliver power to a specific load or battery charger of an EV. High-resonance frequency is required to enhance the range and power transfer capability of the induced secondary voltage [3], [4]. Thus, a primary inverter that can deliver maximum power at a higher operating frequency plays a vital role in an IPT system.

Several primary inverter topologies have been described in the current literature. Full-bridge-series LC resonant (SLC) and series-parallel resonant (LCL) topologies [5]-[11] are primarily used in applications in which the required power level is 1 kW or higher. However, a single-switch class-E resonant inverter can also meet the requirements of the WPT system because of its capability to deliver medium power (1–3 kW) at higher switching frequencies [3], [12], [13]. This inverter also has a simple topology with lower component count and timing control, and requires a relatively simple gated drive because of the absence of high- and low-side complimentary switches.

Thus, a passive resonant network can be added parallel to the load network to reduce the high switching stress of a class E inverter. This type of modified class E inverter is referred to as Class EF (class E/F) inverter [14], [15]. Voltage stress in this family of inverters is reduced to 40% from class E. The performance and power output capability of this inverter are also higher. Voltage stress could be reduced further by placing a passive resonant circuit between the finite DC-feed inductor and the semiconductor switch. These types of inverters are referred to as class Ф inverter in the literature [14]. These two families of inverters have demonstrated potentiality for various IPT applications. In the contemporary literature, detailed designs of these types of inverters are confined to the frequency range between 800 kHz and 13.6 MHz, although some WPT applications operate on a 20 kHz–100 kHz frequency range [15], [16]. Therefore, a clear scope for the performance evaluation of these types of inverters under above-frequency constraint exists. In this study, a modified class EF₂ voltage-fed multi-resonant single switch inverter topology has been proposed for IPT applications. A medium-frequency (85–100 kHz) region with practical IPT coil parameters is used to evaluate the performance and effectiveness of the inverter. The proposed inverter has all the advantages of a class E inverter. The contributions of this paper can be summarized as follows:

1. Design and analysis of a modified class EF₂ inverter for WPT EV charging system. A 500-W experimental prototype that exhibits 90% efficiency at nearly perfect aligned condition has been built.

2. Considerable reduction of peak voltage stress across semiconductor devices has been achieved.

3. A simple design procedure has been introduced to calculate the various component parameters of the inverter for a pre-built WPT coil.

This rest of this paper is organized as follows. Section II discusses the working principle, pros, and cons of a current-fed class E resonant inverter. Section III describes the proposed voltage-fed multi-resonant class EF₂ inverter, and discusses the design procedure of the proposed inverter for IPT application and simulation model. Sections IV and V contain the discussion of simulation and experimental results, respectively. Finally, Section VI concludes the paper.

Ⅱ. CURRENT-FED CLASS E RESONANT INVERTER

Figs. 1 and 2 show the current-fed class E resonant inverter topology and operating waveform during nominal condition.

Fig. 1. Current-fed class E inverter.

This inverter was first introduced by Sokal [16]. A conventional current-fed class E inverter (Fig. 1) usually consists of a dc-supply V_IN(DC), an input choke (dc-feed) inductance, L_choke, power MOSFET, which is used as a switching device, a shunt capacitor, C_P, and load circuit (combination of series-resonant circuit L_S-C_S and ac load resistance, R_L).

During nominal operation, the class E inverter maintains zero-voltage switching (ZVS) and zero-derivative switching (ZDS) simultaneously. Thus, high-power conversion at higher frequencies is achieved. Switching loss was also reduced significantly because of zero-voltage and jumpless current at a turn-on instance. The ZVS/ZDS condition is expressed in Equation (1):

   (1)

where ωt = 2πD. These conditions are referred to as “nominal condition” for class E inverter operation. In case of maximum power conversion efficiency, conduction losses for ESR components and switch-on/off time resistance must be considered. This operating condition, including ESR, is referred to as “optimal condition.” Fig. 2 shows the nominal operating waveforms of a class E inverter when D = 0.5 (duty cycle). The difference of currents through the dc-feed inductance (or choke inductance), L_choke, and resonant network (L_S–C_S) flows through the capacitor C_P during a switch turn-off interval. The selected operating frequency is greater than the resonant frequency of L_S–C_S but less than the resonant frequency of L_S–C_S–C_P. Furthermore, the output resonant circuit of a class E inverter usually has a high-quality factor Q. Thus, load current i_out is regarded as a sinusoid.

Class E inverters have a smaller component count, simple gate drive configuration, inherent sine-wave voltage/current output, and efficient high-frequency operation because of ZVS/ZDS. ZDS operation reduces Miller effects. Although class E inverters have significant advantages, they are also prone to few severe consequences, such as the peak switch voltage stress across the semiconductor switch. Fig. 2 shows that drain-to-source voltage, V_DS, is 3-3.5 times higher than the input DC voltage. This phenomenon is not desired in high-power and high-frequency conditions. Another major disadvantage of a class E inverter is its high input dc-feed inductor loss because of its bulky size. Thus, core loss and ESR loss are high.

Fig. 2. Nominal operating waveforms of current-fed class E inverter (D = 0.5).

Several topologies have been proposed in the literature to overcome these limitations and increase the efficiency of the inverter at higher frequency ranges (tens of megahertz) [14], [17], [18]. As previously stated, most of the designs of the inverter were concentrated for very high-frequency (MHz) operations. In this study, a new voltage source single-switch multi-resonant inverter topology is introduced. The new inverter can maintain a sine-wave output similar to that of a class E inverter while maintaining a reduced peak switch voltage stress. The new inverter also has a higher power conversion efficiency than the class E inverter. Moreover, the new inverter is suitable for contactless power transfer application ranging from 85–100 kHz. The proposed inverter design focuses on reducing the peak-voltage stress and input inductor loss while maintaining power output capability. In the following sections, a detailed design of this inverter is presented.

Ⅲ. VOLTAGE-FED MODIFIED CLASS EF₂ RESONANT INVERTER

Fig. 3 shows the proposed inverter topology. The input dc-feed inductance is replaced with a resonant inductance L_R. In a class E inverter, the input dc-feed choke inductance is bulky and produces high losses while operating in a frequency region of 30–100 kHz. This loss has been substantially reduced using a resonant inductor. Thus, the volume and value of the inductor have been reduced because this inductor now resonates with a frequency higher than the switching frequency. Thus, a small core area is required to construct the inductor with less turn, which will result in small magnetic and ESR loss.

Fig. 3. Proposed voltage-fed multi-resonant class EF₂  inverter.

Furthermore, a series resonant circuit (L_SR–C_SR) has been inserted between the input resonance inductor and switch to reduce the peak voltage stress across the switching device. This series resonant circuit is tuned to resonate with the second harmonic of the switching frequency. The extra resonant circuit with selected harmonic elimination is used to reduce the switching stress that has been discussed comprehensively in [14], [17]-[19]. The second harmonic elimination contributes in the reduction of peak switch voltage stress. For a class E current source inverter, the maximum peak voltage across the switch can reach up to 3.5 times the input DC voltage. However, the voltage peak in the proposed multi-resonant inverter is limited to only 2 times of the input DC, which is shown in following sections. This peak switch stress reduction is necessary when high input DC is used (rectified from utility). In case of a conventional class E, when a rectified voltage of 300 V is applied, the peak switch stress will reach up to 1 kV, which is not desirable. However, in case of the proposed inverter, the peak switch stress will reach up to 600 V, which is desirable in the range of the safe operating area (SOA) of the switch. Many commercial semiconductor switches are available for the practical implementation of the inverter.

The components of the inverter are calculated such that the peak voltage amplitude across the switch decreases and maintains the switch-mode operation through near zero- voltage at turn-on and turn-off at a given frequency and duty ratio. Fig. 4 shows a simplified circuit diagram of the proposed inverter.

A. Circuit Operation

When the switch is ON, the current through the MOSFET is given by Equation (2). The total switch current can be found by determining .

       (2)

The current through the input inductor is the resonant current, which can be defined as Equation (3) for any duty cycle D.

                                                         (3)

The current through the series-tuned second harmonic termination branch (L_SR–C_SR) can be found using Equation (4).

                                                    (4)

The coefficients K₁ and K₂ are determined based on the equation boundary conditions. Finally, the output current, i_out, can be evaluated as sinusoid using the fundamental harmonic approximation (FHA):

                                                                 (5)

where I_m is the magnitude of the output current, and “α” is the initial phase between the current and the voltage.

When the switch is OFF, the maximum voltage across the drain to the source port of the MOSFET can be calculated by determining the voltage across the capacitor C_P. The parallel capacitor will charge within an arbitrary time and reach a maximum point. The maximum voltage and shape of the drain to the source voltage, V_DS, will depend on the overall drain-to-source (Z_ds) characteristic. Fig. 5 shows that the V_DS will be a quasi-resonant wave. The current through C_P based on the duty cycle is given by Equation (6).

                                        (6)

During the OFF condition, the current in the L_SR–C_SR branch can be determined by applying KCL at the drain node

                                               (7)

Equation (8) can be written as:

                                                   (8)

The total voltage across the L_SR–C_SR branch is [14]:

                                       (9)

The final equation of the current through the L_SR – C_SR branch can be obtained by differentiating Equation (9) and substituting in Equation (8), as follows:x

                                     (10)

The general solution of Equation 10, which is a linear, non-homogeneous, differential equation, is the current through the series resonant branch during OFF condition, and can be given as follows:

                                                   (11)

where and

K₃ and K₄ values can be determined using the boundary conditions of the equation. The voltage and current continuity conditions when switching ON and OFF determine the boundary condition. The current through parallel capacitor can be obtained using Equation (9).

                                            (12)

The voltage across the C_P, which is the drain-to-source voltage of the MOSFET, is given by Equation (13)

                                                           (13)

where δ is a constant that indicates the maximum drain-to- source voltage slew rate. Equation (9) can be rewritten by incorporating the ZVS condition as follows:

                                     (14)

MATLAB function “fsolve” can be used to compute the values of unknown variables K₃, K₄, n, and α for the specific values of D, m, and F. This is one method of calculating the various component of the proposed voltage-fed inverter. However, in this study, a different design technique has been implemented to obtain the desired result. (11) shows that V_DS is dependent on m, n, F, and D, and “m” and “n” are dependent on F. Therefore, the values of F have been deduced first. The peak voltage stress of the semiconductor switch is dependent upon the ratio of “F”. Furthermore, the values of L_S–C_S can be calculated independently. Thus, the overall new design procedures are described in the following section based on the two aforementioned insights.

Fig. 4. Circuit diagram of voltage-fed single-switch multi-resonant inverter for analysis.

Fig. 5. Simulated drain-to-source voltage of proposed inverter (Input: 200 VDC).

B. Derivation of I_m

The switch current can be given as

                                   (15)

The average switch current is equal to the DC input current [14]; thus,

                                               (16)

Solving (16), we have

                                              (17)

As , substituting (17) into this equation

                                                (18)

C. Design of Modified Voltage-Fed Class EF₂ Resonant Inverter

Calculation of L_S–C_S and C_P

The values of L_S can be computed according to the specific application requirement. In this work, L_S is the inductance of the primary coil of a loosely coupled transformer. These types of transformers are widely used in WPT application. In the case of WPT system, reflected impedance is also added with L_S.

C_S is calculated such that the resonance frequency of L_S–C_S becomes lower than the switching frequency. A proper selection of this frequency is necessary to maintain the appropriate voltage gain. The combined effect of L_S–C_S contributes to the reduction of switch voltage stress.

The value of C_P is calculated to maintain the ZVS operation of MOSFET. The following criteria must be met while calculating the value of C_P.

                                                                (19)

where f_S, is the switching frequency and and are given by

      and                               (20)

Fig. 6. Duty cycle and V_DS for different F values.

Fig. 7. IPT system configuration schematic with proposed inverter.

After calculating the value of C_P, we determine the value of C_SR using the value of F. Different values of F will result in different levels of voltage and current stress on the semiconductor switch. Fig. 6 shows that a family of curves has been given for duty cycle and V_DS based on various F. The x-axis represents the duty cycle and y-axis represents the peak switch voltage stress (multiple of input DC voltage). When F values lie between 1.2 and 1.4, V_DS decreases within the duty cycle range of 30%-40%. Peak voltage stress increases rapidly with duty cycle when threshold and ZVS cannot be maintained.

Values of L_R, L_SR –C_SR

When the values of F and C_P are calculated, the value of C_SR can be calculated using . L_SR is calculated such that it resonates with C_SR on the second harmonic of the switching frequency. The value of L_SR can be calculated using (21). Equation (22) shows that the resonance frequency of L_R and C_P will be slightly higher than the switching frequency. When the value of C_P is determined, L_R is calculated using (22). The resonant frequency of L_R and C_P could work as design criteria of the inverter. This resonant frequency is selected such that the ZVS of the MOSFET can be achieved up to 60% of the load change.

  (21)

   (22)

In summary, the overall design procedure can be described as follows:

⋅L_S is calculated according to the application specification.

⋅C_S and C_P are determined according to the conditions specified in (19) and (20).

⋅C_SR is calculated based on C_P and F.

⋅L_SR is calculated using (21).

⋅The value of L_R is calculated based on Equation (22).

D. Simulation Model

A simulation model of the proposed voltage source multi-resonant inverter with a IPT (WPT) system has been built using MATLAB/SimPowerSystem toolbox to verify the design concept.

Figs. 7 and 8 show the schematic of the complete system and the simulation model, respectively. The simulation model is designed to transfer 1 kW power across a vertical gap distance of 8 cm. Primary inductance, secondary inductance, and mutual inductance have been measured using a LCR meter with 8 cm vertical gap and up to 30% horizontal misalignment [20]. Subsequently, these inductances are inserted into the simulation model. The rest of the inverter components are calculated using the method described in the previous section. Fig. 7 shows that the primary or transmitter side forms a capacitor-inductor-capacitor (CLC) compensation. Series compensation has been used in the secondary or vehicle side of the system.

The value of C_S is obtained by setting the resonance frequency of L_S–C_S to 95 kHz according to (12). The switching frequency in this study is selected as 100 kHz. C_P is obtained again using (12). The curve in Fig. 6 shows that the selected “F” value ranges from 1.4–1.5. Then, C_SR is calculated according to (8), and other component values have been solved using consecutive steps that are described in the previous section. The duty cycle has been maintained at 30% all the time, according to Fig. 6. The values of L_R, C_SR, C_P, and C_S have been changed for further tuning during the simulation to obtain the final inverter model. The inverter maintains ZVS even in considerable load changes (60%) and provides good power output with reduced switch voltage stress. The peak voltage stress is reduced considerably compared with other single-switch inverters [3], [14], [15]. The simulation result shows that the peak voltage only reaches up to 2 times the input DC voltage. However, for other single-switch inverters, this peak voltage stress increases up to 2.5–3.5 times with the same output power transfer capability. Besides, the proposed inverter has all the inherent advantages of a class E-type inverter. Table I shows the final component values of the simulated model.

Fig. 8. Simulation model.

TABLE I  Simulation Parameters

Components	Values
LR	15 µH
LSR	6.5 µH
CSR	100 nF
CS	26 nF
CP	146 nF
Inductance of primary coil of IPT system, LS	100.38 µH
Inductance of secondary coil of IPT system	103.77 µH
Secondary side compensation capacitor	24.5 nF
Mutual inductance	14.85 µH
Load resistance	25 Ω
Duty cycle	30%
	98.517 kHz
	107.55 kHz
	107.1 kHz

Ⅳ. SIMULATION RESULT AND DISCUSSION

Fig. 9(a) shows the drain-source voltage (V_DS) and the current (I_DS) waveform of the proposed inverter. V_DS has maintained ZVS/ZDS at turn-on and provided less peak stress, as calculated theoretically using Figure (6). Given 200 V DC input voltage, the peak stress across the switch is 400 V. However, I_DS is slightly higher in the simulation because of the simulation method used in the Simulink/SimPowerSystem toolbox. This problem may be solved by developing a custom component model of inductor and capacitor. However, this problem is beyond the scope of this work. Thus, existing component models have been used.

Fig. 9. (a) V_DS and I_DS at full load (DC Input: 200V) (b) V_GS and V_DS

(a)

(b)

Fig. 10 shows that this inverter exhibits good operating characteristics during considerable load changes. DC equivalent ac resistance is used for practical and simulation purposes to observe the load voltage and current. Fig. 11(a) shows load voltage and current waveforms. Voltage and current are in phase and resonance, indicating efficient power transfer. Fig. 11(b) shows that drain-to-source impedance (Z_DS) characteristic depicts the magnitude and phase at 100 kHz operating frequency. A certain Z_DS magnitude and phase must be observed to maintain ZVS and reduce peak switch stress. Fig. 11(b) shows the selected operating point for this design. Some other operating points could also be selected when impedance magnitude and phase are not below 20 Ω and 23°.

Fig. 10. (a) V_DS and I_DS at 40% load change (DC Input: 200V), (b) I_DS (magnified).

(a)

(b)

Fig. 11. (a) Load voltage and current (b) Drain-source impedance magnitude and phase.

(a)

(b)

Below these limits of impedance magnitude and phase, the proposed inverter could not maintain efficient operation because of hard switching. Fig. 12 shows that the overall system has constant output voltage characteristics with load change.

Fig. 12. Output voltage and Load resistance (Input DC: 200V).

Inverter efficiency is calculated after subtracting the losses of L_R, L_SR – C_SR branch, switch conduction loss, off time loss, and loss through C_P. This detailed simulation model is used to build the experiment setup. The details of the experimental result and discussion are provided in the next section.

Ⅴ. EXPERIMENT RESULT AND DISCUSSION

A 500-W experiment setup was built to verify the operation and performance of the proposed voltage source multi-resonant inverter with WPT system, as shown in Fig. 13. The specifications of the prototype are listed in Table II. A maximum of 150 W has been transferred to measure the efficiency and other parameters because of limited proper electromagnetic shielding and to maintain the safety of the digital controller. The gate signal was generated using an ePWM module of Texas Instruments TMS320F28335 digital signal processor. Figs. 14 to 16 show the experimental results. V_DS and V_GS completely agree with the simulation result. The voltage waveshape and peak stress of the V_DS is exactly similar to the designed model. V_DS has a spike during turn-off instant because of the mismatch between gate-to-source and gate-driver output impedance. This mismatch can be mitigated by modifying the gate driver circuit design. In the current gate driver, the output impedance is controlled using a fixed resistor. However, the output impedance of the gate drive circuit can be varied to match the gate-source impedance of the MOSFET by introducing a variable resistor. This resistor will eliminate unwanted ringing during turn-of condition, which will reduce the spike of V_DS. Primary side voltage and current are not in resonance because of the multi-resonance characteristic in the primary side. Load voltage and current have a small phase shift. This phenomenon occurs because of the out-of-resonance operation of the secondary side and the high leakage magnetic field of the IPT coils, which could be reduced by properly designing the coil. This phase-shift increases and affects the power transfer efficiency during misalignment condition.

Fig. 13. (a) Complete experiment setup (b) Proposed single- switch inverter.

(a)

(b)

Fig. 14. (a) V_GS and V_DS (b) V_DS and Load voltage.

(a)

(b)

TABLE II  Specifications of the Prototype

Inverter components	Value	Manufacturer
LR	14 µH – 15 µH	Coilcraft
LSR	6.5 µH	Coilcraft
CSR	98.55 nF (Polypropylene)	KEMET
CP	146 nF (Polypropylene)	KEMET
CS	26 nF (Polypropylene)	KEMET
Csec_comp	25.2 nF (Polypropylene)	KEMET
MOSFET	CREE C2M0080120D SiC MOSFET (VDS = 1200 V, ID = 36 A at 25 °C
DSP (for inverter control)	Texas Instruments TMS320F28335 eZDSP board and gate driver circuit
Coil parameters	LPrimary	LSecondary
	100.38 µH	103.77 µH
Total power	500 W (150 W used in the experiment)
Input Voltage	100- 130V

Fig. 15(a) shows that primary and secondary side voltages are in phase, indicating proper magnetic coupling. Fig. 15(b) shows the V_DS recorded at 30% misalignment. The peak voltage stress could be maintained at 30% misalignment condition of IPT coils. This feature is important for primary side inverters used in IPT system.

Fig. 15. (a) Primary-side voltage and secondary-side voltage (b) Peak V_DS at 30% misalignment condition (input voltage: 50 V DC).

(a)

(b)

Fig. 16. (a) Primary voltage and current (b) Secondary voltage and current.

(a)

(b)

TABLE III  Performance Evaluation of Proposed Modified Voltage-Fed Multi-Resonant Class Ef₂ Inverter with Class E and Conventional Class Ef₂ Inverters

Parameters	Class E [3, 4, 21]	Class EF2 [14, 15, 19, 22]	Modified voltage-fed class EF2
VDS (V) (times input DC)	3.5	2.5	2
Input DC voltage (V)	100–200	100–200	100–350
Output voltage and current waveshape	Sinusoidal	Sinusoidal	Sinusoidal
Misalignment tolerance	-	-	High
Input inductor loss	High	High	Low
Circulating current	-	-	Low
Efficiency	90%	88%	90%±2

A performance evaluation of the proposed inverter with two class E and class EF₂ high- frequency resonant inverter topologies, as shown in Table III. In every category, the proposed inverter has demonstrated better operating characteristics. The drain-to-source voltage across MOSFET in the proposed inverter is less than that of the conventional class EF₂ inverter. L_R is a resonant inductor in the proposed topology that reduces losses and size. Thus, the system can be designed to become compact and power density could be increased. The constant voltage characteristics could be maintained (Fig. 12), which is desirable for IPT application. Besides, these inverters have the inherent sine-wave characteristics similar to those of conventional class EF₂ and class E inverter. The proposed modified class EF₂ inverter can deliver similar output power with less device stress and losses than its conventional counterpart.

Fig. 17(a) and (b) show the efficiency of the inverter for two types of misalignment condition. Fig. 18(a) and (b) shows the coupling variations of the WPT coil used for this experiment. Efficiency during vertical misalignment is lower than in horizontal misalignment because of the low coupling and high leakage magnetic field of the coils. This efficiency measurement was conducted during 150-W power transfer condition. Power transfer was maintained in this range because of some experimental limitation. At this operating condition, the losses in L_R, L_SR – C_SR branches, switch conduction, off time loss, and loss through C_P were calculated using Equations (16) to (19).

Fig. 17. Inverter efficiency (a) during horizontal misalignment, (b) during vertical misalignment.

(a)
(b)

Fig. 18. Changes of coupling coefficient (a) during horizontal misalignment, (b) during vertical misalignment.

(a)
(b)

The loss in the input resonant inductor is equal to

                           &sp;                                           (23)

where is the ESR of the resonant inductor measured by the LCR meter.

The switch conduction loss is calculated using (17) with switch rms current and on-time resistance r_DS(ON).

                                              (24)

The power loss in C_P due to ESR is calculated by (25)

                                                        (25)

and the total power loss in L_SR-C_SR is

                                                            (26)

Ⅵ. CONCLUSIONS

This paper presents a modified single-switch voltage-fed multi-resonant class EF₂ inverter and its application in IPT system. An intuitive design method was described to calculate the various component values of the proposed inverter for an IPT system. Through the same design procedure, the component value of the proposed inverter can be calculated for other applications. The following are the main highlights of the proposed inverter compared with conventional class EF₂ and class E inverters:

⋅Input choke inductor loss is reduced using resonant inductor.

⋅Peak voltage stress across the switching device is reduced considerably using a passive resonant circuit.

⋅Zero-voltage switching operation.

⋅Inherent advantages of single-switch class E inverter are maintained.

⋅Constant output voltage characteristics for the IPT system are provided.

The inverter is experimentally verified using a 500-W IPT setup with a frequency range of 95 kHz–100 kHz. The maximum efficiency of the inverter is 90%±2 and maintains good operation during misaligned conditions of the IPT system.

ACKNOWLEDGMENT

The authors are grateful for the financial support provided by the University of Malaya, Malaysia, through the Postgraduate Research Grant (PPP) PG338-2016A and the Ministry of Higher Education of Malaysia through the Fundamental Research Grant Scheme (FRGS) FP014-2014A.

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Mohammad Kamar Uddin received his B.Sc. degree in electrical and electronic engineering from the International Islamic University Chittagong, Bangladesh in 2012. He is currently pursuing his M.Eng.Sc. degree at the Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia. His research interests include wireless power transfer system design, high-frequency power converter and their control, and DC/DC converter.

Saad Mekhilef is an IET fellow and an IEEE senior member. He is the associate editor of IEEE Transaction on Power Electronics and Journal of Power Electronics. He is currently a Professor in the Department of Electrical Engineering, University of Malaya. He is the Director of Power Electronics and Renewable Energy Research Laboratory-PEARL. He is the author and coauthor of more than 250 publications in international journals and proceedings. He is actively involved in industrial consultancy for major corporations in power electronics projects. His research interests include power conversion techniques, control of power converters, renewable energy, and energy efficiency.

Gobbi Ramasamy received his bachelor’s degree in electrical engineering from the University Technology, Malaysia, and his Master’s degree in technology management from the National University of Malaysia. He has been associated with technical education for more than 15 years. He was an R&D engineer in an electronics company before becoming a lecturer in electrical and electronics engineering. He has supervised research on variable-speed drives, automation, and domestic electrical installations. He is a project leader and member of various government research projects related to switched reluctance motors and power electronics systems. Dr. Gobbi is a corporate member of the Institute of Engineers, Malaysia. He is a professional engineer registered with the country’s Board of Engineers, Malaysia. He is a senior member of IEEE and vice chair of the Power Electronics, IEEE Chapter, Malaysia.