사각형입니다.

https://doi.org/10.6113/JPE.2018.18.2.323

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Bridgeless Buck PFC Rectifier with Improved Power Factor


Mahdi Malekanehrad* and Ehsan Adib


†,*Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran



Abstract

Buck power factor correction (PFC) converters, compared with conventional boost PFC converters, exhibit high efficiency performance in the entire range of universal line voltage. This feature has gotten more attention for eliminating the zero crossing dead angle of buck PFC rectifiers. Furthermore, bridgeless structures for the reduction of conduction losses have been proposed. The aim of this paper is to introduce a single-phase buck rectifier that simultaneously has unity power factor (PF) and bridgeless structure while operating in the continuous conduction mode (CCM). For this purpose, two auxiliary flyback converters without any active switches are applied to a bridgeless buck rectifier to eliminate the zero crossing dead angle and achieve unity power factor, low total harmonic distortion (THD) and high efficiency. The operation and design considerations of the proposed rectifier are verified on a 150W, 48V prototype using a conventional peak-current-mode control. The measurement results show that the proposed rectifier has nearly unity power factor, THD less than 7% and high efficiency.


Key words: Bridgeless AC-DC converters, Buck converter, Power factor correction, Zero crossing distortion


Manuscript received Feb. 15, 2017; accepted Aug. 27, 2017

Recommended for publication by Associate Editor Chun-An Cheng.

Corresponding Author: e.adib@cc.iut.ac.ir

Tel: +98-31-33912210, Fax: +98-31-33912862

*Dept. of Electr. Computer Eng., Isfahan Univ. of Tech., Isfahan, Iran



Ⅰ. INTRODUCTION

The use of power factor correction (PFC) converters as a current shaper in the front stage of ac/dc rectifiers is an effective method to provide high power factor (PF) and low total harmonic distortion (THD) for meeting IEC61000-3-2 [1]. On the other hand, high efficiency is a vital requirement of performance. Meeting the requirements of both high PF and efficiency poses a major challenge for ac/dc rectifiers. Boost converters are the most commonly used PFC converters. However, in universal-line application, the efficiency of a boost PFC is reduced about 1-3% at low-line voltage compared to high-line voltage due to its large operating duty cycle for providing a high voltage gain [2]-[4]. Furthermore, its high output voltage (380-400 V) increases the switch voltage stress and the voltage stress of the second stage switches and reduces efficiency [3], [4].

Recently, the use of front stage buck PFC converter has increased [2]-[25]. According to the authors of [3], a buck PFC converter with 80 VDC output demonstrates high efficiency across the universal-line range. Furthermore, the low output voltage of the buck PFC reduces the voltage stress of the output stage switches and improves the light load performance. In [4], a bridgeless buck PFC was proposed to reduce conduction losses by minimizing the number of simultaneously conducting semiconductor devices. However, in a buck converter, compared to its boost counterpart, there is an inherent dead angle in the input current around the zero crossings of the line voltage for input voltages that are lower than the output. This leads to a high current distortion and a low PF that limits the maximum power level. For example, in [4], the measured PF and THD at full load (700 W) and 115 Vac line voltage are 0.88 and 43.4% and at 10% load (75 W) and 230 Vac they are 0.66 and 19.4%, respectively. Although these values are in compliance with IEC 61000-3-2, the higher losses and EMI due to increased input current peak are drawbacks.

In [21]-[24], for Vin<Vout, an auxiliary flyback converter with an auxiliary switch, diode and inductor is activated to shape the input current and reduce the zero crossing dead angle. However, in these topologies, three or four simultaneously conducting semiconductor devices increase the conduction losses. Due to transition from flyback to buck mode at Vin = Vout, the input current can change abruptly and increase the THD.

In [25], the output capacitor of an auxiliary flyback converter is in series with the switch of a conventional buck converter. Thus, the voltage of the flyback output capacitor is added to the rectified line voltage. As a result, the zero crossing dead angle of the input current is omitted. However, three simultaneously conducting active components in the conducting period of the buck switch increase the conduction losses and reduce the efficiency.

In this paper, a bridgeless unity PF buck rectifier is proposed. Two auxiliary flyback converters are used in a bridgeless buck topology to omit the zero crossing dead angles of the positive and negative half-line cycles. Thus, the proposed rectifier provides both high PF and efficiency. Without any auxiliary switches and only with one auxiliary diode, one low voltage small capacitor and an additional winding on the core of the buck inductor, the dead angle of the input current is omitted and a unity PF is achieved. The operation of the proposed rectifier is verified using a 150 W, 48 V experimental prototype operating in the continuous conduction mode (CCM) using peak-current-mode control method.



Ⅱ. PRINCIPLE OF OPERATION

The proposed bridgeless unity PF buck rectifier is shown in Fig. 1, Figs. 2(a) and 2(b) show the operation of the rectifier in the positive and negative half-line cycles, respectively. Due to their similarity, only the positive half- line cycle is described. The buck converter of the positive half-line cycle, consists of a unidirectional switch implemented by diode D1 and switch S1, freewheeling diode D5, filter inductor L1, and output capacitor C1. The auxiliary flyback converter consists of diode D3, small capacitor Ca1 and inductor L3 that is couple with its buck counterpart L1 with a unity turn ratio. The operation of the rectifier is presented using theoretical waveforms (Fig. 3) and the following assumptions.


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Fig. 1. Proposed bridgeless unity power factor buck rectifier.


Fig. 2. Operation of the positive and negative half-line cycles. (a) Positive half-line cycle. (b) Negative half-line cycle.

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(a)

 

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(b)


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Fig. 3. Theoretical key waveforms.


- All of the components are ideal except for the coupled inductors L1,3 and L2,4, where their leakage inductances are included.

- The output capacitors C1,2 are large enough to obtain constant output voltages VO1,2 in a switching cycle.

- The initial voltage of Ca1 is equal to VO1 (VCa1 (t0) = VO1).


Mode 1 (t0-t1): According to Fig. 4a, by turning the buck switch S1 on, the voltage Vac+VCa1-VO1 is applied to the buck inductor L1 and iL1 increases linearly. The buck inductor current iL1 discharges the capacitor Ca1 and decreases its voltage VCa1 from the initial value VCa1 (t0) =VO1 to VO1 - ΔVCa1. The low voltage ripple of ΔVCa1 is desirable because the line voltage Vac is applied to the inductor L1 and the dead angle of the line current is omitted. The current iL1 is increased with a slope of Vac/L1 . At t = t1 = DT, switch S1 is turned off while iL1 reaches its maximum value Ip (Fig. 3).


Fig. 4. Equivalent circuits of the three modes during the positive half-line cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3.

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(a)

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(b)

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(c)


Mode 2 (t1-t2): Since VCa1 and VO1 are almost equal, by turning the switch S1 off, the diodes D3 and D5 conduct simultaneously (Fig. 4b). Thus, by turning the switch S1 off, a part of the inductor L1 energy charges the capacitor Ca1 and the other part charges the output capacitor C1.

Mode 3 (t2-t3): This mode starts when the capacitor Ca1 is charged up to VO1 and the inductor current iL3 is zero (Fig. 4c). The inductor current iL1 freewheels through D5 and supplies the load power. According to the operating modes, the buck converter shapes the line current for Vac < VO1 and the dead angle of the line current is omitted, which results a unity power factor.

In [3], [4] to provide low THD and high PF, a complex control circuit is applied. In the proposed rectifier, by eliminating the zero crossing dead angle, the conventional peak current control method can be applied. In this method, when the switch current reaches the reference current, the buck switch is turned off. After a switching period, it is turned on again to shape the input current.

In Table I, the proposed rectifier is compared with the topologies in [21]-[25]. According to Table I, just two simultaneously conducting semiconductor devices reduce the conduction losses and increase the efficiency.


TABLE I COMPARISON OF THE PROPOSED RECTIFIER AND THE TOPOLOGIES IN [21]-[25]

Parameters

[21]

[22]

[23],[24]

[25]

Proposed

switch

2

2

2

1

2

diode

7

7

6

6

6

magnetic element

2

1

1

1

2

conducting semiconductor devices

4

3

4

3

2

Transition from flyback to buck at Vin = Vout

yes

yes

yes

no

no

bridgeless

no

no

no

no

yes


In the proposed converter, each buck inductor is coupled with its flyback counterpart. Therefore, the series capacitor voltages are equal to their corresponding output voltages, VCa1=VO1 and VCa2=VO2. As a result, in the both positive and negative half-line cycles, independent of the values of VO1, 2 and L1, 2, the line voltage Vac is applied to L1, 2 and the dead angle of the buck converter is omitted. In addition, in order to achieve similar input current amplitudes for the positive and negative half cycles, due to the applied peak current control method, the values of L1 and L2 should be almost equal. Furthermore, C1 and C2 should be large enough to provide a small ripple and the difference in their values has minor effect in the converter operation.



Ⅲ. DESIGN PROCEDURE

According to the principle of operation, a simple design procedure is presented that includes the determination of the inductors, capacitors as well as the current and voltage stress of the semiconductor components.


A. Minimum Duty Cycle

As expressed in mode 1, the capacitor Ca1 should be selected large enough to provide a low voltage ripple for VCa1. Thus, the inductor L1 can be charged by the line voltage Vac in the time period of DT. By turning the buck switch S1 off, a part of the inductor L1 energy charges the capacitor Ca1 to the output voltage VO1 in a short time. Then, the inductor L1 is discharged by the output voltage VO1 in the time period of (1 – D)T. Writing the volt-second balance for L1 in the CCM as Vac D = VO1 (1 - D), the minimum duty cycle Dmin is expressed as (1). This shows that as line voltage increases, the duty cycle decreases and Dmin occurs for Vac,max.

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B. Auxiliary Capacitors Ca1,2

An input low pass filter should be designed to remove the switching component of the currents iS1,2 and produce sinusoidal line current. Thus, its low cut-off frequency has been considered to be about 10% of the switching frequency and the inductor Lf and the capacitor Cf are selected. The average current of the buck switch in each switching cycle is equal to the instantaneous input current. Thus, the peak of the switch current Iin,peak occurs at the peak of the line voltage.

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Based on the above equation, the maximum area under the curve of the switch current (Si) is obtained as (3), where fs is the switching frequency.

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At the switch on time, Ca1 voltage is discharged from VO1 to VO1 - ΔVCa1. The maximum variation of VCa1 occurs at the maximum of the line voltage. Therefore, the capacitor Ca1 is calculated as (4).

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C. Current and Voltage Stress of the Semiconductor Components

At the peak of the line voltage, the buck switch current iS1 is increased with a slope of Vin,max/L1 at the time period of DminT from Ip-ΔIL,max to Ip, where ΔIL,max is the maximum current ripple of the buck inductors (Fig. 3). The area under the curve of iS1 on DminT is equal to Si and is presented in (3). In other words, the area of a trapezoidal current with a height of DminT and two bases of Ip and Ip –ΔIL,max is calculated as (5).

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Using (3) and (5), the peak of the switch current Ip is obtained from (6).

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In mode 1 (Fig. 4a), the freewheeling diode D5 and the auxiliary flyback diode D3 are off. Considering VCa1 = VO1, their reverse voltages are Vac + VO1. In mode 2 (Fig. 4b), by conducting the freewheeling diode D5, the voltage stress of the buck switch S1 is equal to Vac + VO1. It is observed that the voltage stress of the semiconductor components of the proposed converter can be as much as VCa1 = VO1 = VO/2 greater than the conventional buck converter.


D. Detailed Analysis of the Second Operating Mode

As expressed in the second mode, the capacitor Ca1 should be large enough to provide a low voltage ripple for VCa1. Thus, the diodes D3 and D5 can be turned on simultaneously (Fig. 4b). Fig. 5 shows an equivalent circuit of this mode, where the magnetizing inductance and the leakage inductance of L1,3 are shown by LM and Llk, respectively. For the maximum of the line voltage Vac,max, the initial voltage of Ca1 is VO1 -ΔVCa1 and the initial current of LM and Llk is equal to Ip.

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Fig. 5. An equivalent circuit of the second mode.


When the switch S1 turns off, the voltage V1 with the polarity shown in Fig. 5 is increased rapidly and clamped to VO1- ΔVCa1 + Vγ,D3 and the diode D3 starts conducting. The leakage inductance Llk should continue its current. Thus, its voltage Vlk is reversed and reaches ΔVCa1, and the diode D5 continues its current ilk. The reverse voltage of Llk reduces the current ilk and considering a large LM and thus a constant ILM, the current i1 is increased. ΔVCa1 should be small enough so that at the instant of current division between i1 and ilk, the current ilk does not reach zero and the current i1 can charge the capacitor Ca1 to the voltage VO1. To satisfy the above condition, the minimum value of the capacitor Ca1 should be calculated correctly. For this purpose, the voltages of the buck circuit are written as (7). The threshold voltage of the diodes D3 and D5 are assumed to be equal to (그림입니다.
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Writing V1 as VCa1 + Vγ in the auxiliary flyback circuit, (7) can be rewritten as (8).

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By solving (8), the currents i1 and ilk at the instant of current division are obtained as (9) and (10), respectively.

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The current ilk should not reach zero (ilk > 0) at the instant of current division of ILM between ilk and i1 to satisfy the condition of the second mode operation. Therefore, the condition is written as (11).

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Substituting ΔVCa1 from (4) and ILM=Ip from (6) in (11), the minimum capacitance of Ca1 is obtained as (12).

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Using the charging current of Ca1 presented in (9), the charging time t̒ of Ca1 from Vo1-ΔVCa1 to Vo1 is calculated from (13) and is shown in (14).

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Thus, the amount of i1() and ilk() are calculated as (15) and (16).

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E. Buck Inductors

Due to the eliminating of the zero crossing dead angle, buck inductor is charged by the line voltage. Thus, the buck inductor L=L1=L2 is calculated from (17).

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F. Output Capacitor

The output capacitor of a PFC converter is calculated based on the output voltage ripple due to difference between instantaneous input and output voltage and is independent of the topology. Assuming unity power factor, the average input power is equal to Vin,rms Iin,rms, while instantaneous input power is equal to (18), where fl is the line frequency. The excess of input power, when the instantaneous input power is greater than the average input power, charges the output capacitor. Thus, the output capacitor based on the output voltage ripple is calculated as (19).

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Ⅳ. EXPERIMENTAL RESULTS

In the buck PFC rectifiers presented in [2]-[4], due to zero crossing dead angle, there is a strong tradeoff between the PF and THD performance and output voltage level. Since the line current is zero for Vin <Vout, increasing the output voltage deteriorates the PF and THD. On the other hand, decreasing the output voltage increases the current levels of the rectifier and leads to higher conduction losses and lower efficiency. This tradeoff is resolved in the proposed converter by eliminating the zero crossing dead angle.


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Fig. 6. Schematic of the implemented circuit.


The performance of the proposed rectifier is verified using a 150 W, 48 V prototype circuit with a 110 Vac line voltage. The schematic of the implemented circuit is shown in Fig. 6.

For VO=48 V, the average values of VO1, 2 are equal to 24 V (Fig. 6). Based on (1), the minimum duty cycle Dmin at the peak of the line voltage Vac,max=155 V is equal to 0.13. In the design of a regular buck converter, the current ripple of the buck inductor is considered about 20% of its maximum value. Due to the short ON time of the buck switches at the peak of the line voltage (Dmin=0.13) and restrictions on the response time of the elements of the control circuit, the maximum inductor current ripple ΔIL,max is considered about 60% of the maximum inductor current Ip. As a result, the current control loop can follow the changes of the inductor current well. Thus, based on (6), for Po=150 W, the maximum inductor current Ip is equal to 21 A and ΔIL,max is 12.5 A. Based on (17), for fs=40 kHz, the buck inductors L=L1=L2 are equal to 40 µH. To implement the coupled inductors L1, 3 and L2, 4 with a unity turn ratio, two ferrite cores (EE33/29) with 50 turns of wire are used. The measured leakage inductance of the coupled inductors is about 0.5 µH.

Based on (12), the condition of the second mode of operation is that the auxiliary flyback capacitors Ca1, 2 should be greater than 10 µF. To ensure the second mode operation, 33 µF electrolyte capacitors are used for Ca1, 2 and ΔVCa1,2=1.5 V is obtained from (4). According to (15) and (16), the currents I1 and I2 are equal to 10 and 11 A, respectively (Fig. 3).

The voltage stress of the switches and diodes was determined as Vac+ VO1=180 V. The peak current of S1 and D1 is Ip=21 A, while the auxiliary diode D3 and the freewheeling diode D5 are I1=10 A and I2=11 A, respectively. Therefore, IRFP260 MOSFET switches and BYV32-200 diodes were used for all of the semiconductor devices.

From (19), for Po=150 W, VO=48 V and ΔVO=5 V, the output capacitor CO is equal to 2 mF. Two electrolyte capacitors (2200 μF, 50 VDC) were used for the output capacitors C1 and C2.

The cut-off frequency of the input low pass filter (Lf and Cf) has been set to about 10% of the switching frequency to remove the switching component of the currents iS1, 2, which results in a sinusoidal line current. Thus, Lf=2 mH and Cf=1 µF have been chosen.


TABLE II COMPARISON OF THE PF, THD AND EFFICIENCY OF THE PROPOSED RECTIFIER AND STATE-OF-THE-ART BUCK RECTIFIERS FOR 110 VAC LINE VOLTAGE

Ref.

Spec.

PF

THD (%)

Efficiency (%)

[2]

VO=90V, PO=100W

0.9

-

97

[3]

VO=80V, PO=94W

0.93

-

96

[4]

VO=160V, PO=75W

0.92

31.3

97

[23]

VO=80V, PO=150W

0.99

7.6

95

[24]

VO=80V, PO=100W

0.99

-

93.6

[25]

VO=48V, PO=30W

0.99

5

92.5

Proposed

VO=48V, PO=150W

0.998

5

94.5


Fig. 7(a) shows the measured line current and voltage waveforms at 150 W of output power. It is observed that the zero crossing dead angle of the line current has been omitted. As a result, a near unity power factor has been obtained. Compliance of the measured line current harmonics, at 150 W of output power and 110 Vac of line voltage, with the Class D requirements of JIS C 6100-3-2 (corresponding to the Japanese specifications of IEC 61000-3-2 for a 110 Vac line voltage) is given in Fig. 7(b).


Fig. 7. Measured line waveforms at Po=150 W. (a) Line current and voltage waveforms (time: 5 ms/div). (b) Measured odd harmonic components of the line current with the Class D requirements of JIS C 6100-3-2.

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(a)

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(b)


Fig. 8(a) shows the measured low frequency voltages of VO, VO1,2 and VCa1,2. It can be observed that the output voltage of each auxiliary flyback converter VCa1,2 follows the corresponding output voltage VO1,2 of the buck converter. Thus, the line voltage Vac is applied to each of the buck inductors and the dead angle of the line current is omitted.

Experimental results show that the peak of the positive and negative line currents in Fig. 7a and the voltages VO1 and VO2 in Fig. 8a are well balance with each other. Therefore, for the values of the inductors L1 and L2 with small mismatching, the effect of mismatching of the buck inductors is negligible.

Measured switching current and voltage waveforms at the peak of the line voltage for 150 W of output power are shown in Figs. 8(b) and 8(c). The waveforms and the mount of currents and voltages are in agreement with the theoretical ones shown in Fig. 3 and the designed values.

The measured efficiency, PF and THD at different output powers are shown in Fig. 9. The small existing distortion at the line current zero crossing slightly increases the THD, especially for a small line current amplitude. Thus, the amount of THD of the line current is increased with a decreasing of the rectifier power as shown in Fig. 9(b). In addition, at a high output power, a higher voltage ripple of Ca1 and Ca2 slightly increases the THD.

A comparison of the PF, THD and efficiency of the proposed rectifier and state-of-the-art buck PFC converters for a 110 Vac line voltage is presented in Table II. It can be seen that the proposed converter with a simple auxiliary flyback converter and without an auxiliary switch has a PF of more than 0.997 and a THD of less than 7%. By eliminating the input bridge diodes, the number of conducting semiconductor elements in the inductor charging path has been reduced from 3 or 4 to 2 when compared with the topologies in [21]-[25]. This feature decreases the conduction losses. Hence, it increases the efficiency so that the proposed converter shows a high efficiency of around 94%.


Fig. 8. Measured waveforms at Po=150 W. (a) Low frequency voltages (10 V/div; time: 5 ms/div). (b) Switching currents at the peak of the line voltage (8 A/div; time: 10 µs/div). (c) Switching voltages at the peak of the line voltage (time: 10 µs/div)

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(a)

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(b)

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(c)


Fig. 9. Measured efficiency, PF and THD compared with output power.

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(a) Efficiency.

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(b) PF and THD.



Ⅴ. CONCLUSIONS

This paper presented a bridgeless unity power factor buck rectifier. It is shown that without any special design requirements, the dead angle of the buck rectifier can be eliminated. As a result, a unity power factor and a high efficiency can be achieved. A detailed theoretical analysis and design procedure have been presented and verified by experimental results obtained on a 150 W, 48 V output prototype, and 110 V line voltage. Thus, the proposed converter can achieve a unity power factor, a THD of less than 7% and a high efficiency of around 94%.



REFERENCES

[1] Limits- Limits for harmonic current emissions (equipment input current ≤ 16A per phase), IEC 61000-3-2: EMC Part 3-2, 2006.

[2] X. Wu, J. Yang, J. Zhang, and M. Xu, “Design considerations of soft-switched buck PFC converter with constant on-time (COT) control,” IEEE Trans. Power Electron., Vol. 26, No. 11, pp. 3144-3152, Nov. 2011.

[3] L. Huber, L. Gang, and M. M. Jovanovic, “Design-oriented analysis and performance evaluation of buck PFC front end,” IEEE Trans. Power Electron., Vol. 25, No. 1, pp. 85-94, Jan. 2010.

[4] Y. Jang and M. M. Jovanovic, “Bridgeless high-power- factor buck converter,” IEEE Trans. Power Electron., Vol. 26, No. 2, pp. 602-611, Feb. 2011.

[5] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari “A review of single-phase improved power quality AC-DC converters,” IEEE Trans. Ind. Electron., Vol. 50, No. 5, pp. 962-981, Oct. 2003.

[6] T. J. Liang, L. S. Yang, and J. F. Chen, “Analysis and design of a single-phase AC/DC step-down converter for universal input voltage,” IET Electric Power Appl., Vol. 1, No. 5, pp. 778-784, Sep. 2007.

[7] A. Emrani, M. R. Amini, and H. Farzaneh-fard, “Soft single switch resonant buck converter with inherent PFC feature,” IET Power Electron., Vol. 6, No. 3, pp. 516-522, Mar. 2013.

[8] A. A. Fardoun, E. H. Ismail, N. M. Khraim, A. J. Sabzali and M. A. Al-Saffar, “Bridgeless high-power-factor buck- converter operating in discontinuous capacitor voltage mode,” IEEE Trans. Ind. Appl., Vol. 50, No. 5, pp. 3457- 3467, Sep./Oct. 2014.

[9] X. Xie, C. Zhao, Q. Lu, and S. Liu “A novel integrated buck-flyback nonisolated PFC converter with high power factor,” IEEE Trans. Ind. Electron., Vol. 60, No. 12, pp. 5603-5612, Dec. 2013.

[10] Y. Ohnuma and J. I. Itoh, “A novel single-phase buck PFC AC-DC converter with power decoupling capability using an active buffer,” IEEE Trans. Ind. Appl., Vol. 50, No. 3, pp. 1905-1914, May/Jun. 2014.

[11] H. Endo, T. Yamashita, and T. Sugiura, “A high-power- factor buck converter,” in Proc. IEEE Power Electron. Spec. Conf. PESC ’92 Rec., pp. 1071-1076, 1992.

[12] S.-K. Ki and D. D.-C. Lu, “A high step-down transformerless single-stage single-switch AC/DC converter,” IEEE Trans. Power Electron., Vol. 28, No. 1, pp. 36-45, Jan. 2013.

[13] D. Gacio, J. M. Alonso, A. J. Calleja, J. Garcia, and M. Rico-Secades, “A universal-input single-stage high-power- factor power supply for HB-LEDs based on integrated buck-flyback converter,” IEEE Trans. Ind. Electron., Vol. 58, No. 2, pp. 589-599, Feb. 2011.

[14] D. D.-C. Lu and S-K. Ki, “Light-load efficiency improvement in buck-derived single-stage single-switch PFC converters,” IEEE Trans. Power Electron., Vol. 28, No. 5, pp. 2105-2110, May 2013.

[15] Y. W. Lo and R. J. King, “High performance ripple feedback for the buck unity-power-factor rectifier,” IEEE Trans. Power Electron., Vol. 10, No. 2, pp. 158-163, March 1995.

[16] A. Ramezan Ghanbari, E. Adib, and H. Farzanehfard, “Single-stage single-switch power factor correction converter based on discontinuous capacitor voltage mode buck and flyback converters,” IET Power Electron., Vol. 6, No. 1, pp. 146-152, Jan. 2013.

[17] J.M. Alonso, M.A. Dalla Costa, and C. Ordiz, “Integrated buck-flyback converter as a high-power-factor off-line power supply,” IEEE Trans. Ind. Electron., Vol. 55, No. 3 pp. 1090-1100, Mar. 2008.

[18] A. Emrani, M. Mahdavi, and E. Adib, “Soft switching bridgeless PFC buck converters,” J. Power Electron., Vol. 12, No. 2, pp. 268-275, Mar. 2012.

[19] H. Choi, “Interleaved boundary conduction mode (BCM) buck power factor correction (PFC) converter,”  IEEE Trans. Power Electron., Vol. 28, No. 6, pp. 2629-2634, Jun. 2013.

[20] C. Bing, X. Yun-Xiang, H. Feng, and C. Jiang-Hui, “A novel single-phase buck pfc converter based on one-cycle control,” in Proc. CES/IEEE Int. Power Electron. Motion Control Conf. (IPEMC), Shanghai, pp. 1401-1405, 2006.

[21] G. Spiazzi, “Analysis of buck converters used as power factor preregulators,” Proc. IEEE Power Electron. Spec. Conf. PESC ’97 Rec., pp. 564-570, 1997.

[22] X. Xie, C. Zhao, L. Zheng, and S. Liu, “An improved buck PFC converter with high power factor,” IEEE Trans. Power Electron., Vol. 28, No. 5, pp. 2277-2284, May 2013.

[23] J. Zhang, C. Zhao, S. Zhao, and X. Wu “A family of single-phase hybrid step-down PFC converters,” IEEE Trans. Power Electron., Vol. 32, No. 7, pp. 5271-5281, July 2017.

[24] J. Xu, M. Zhu, and S. Yao, “Distortion elimination for buck PFC converter with power factor improvement,” J. Power Electron., Vol. 15, No. 1, pp. 10-17, Jan. 2015.

[25] C. R. Lee, W. T. Tsai, and H. S. Chung, “A buck-type power-factor-correction circuit,” in Proc. IEEE Int. Power Electron. Drive Systems Conf. (PEDS), pp. 586-590, 2013.



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Mahdi Malekanehrad was born in Birjand, Iran, in 1987. He received his B.S. degree in Electrical Engineering from Hakim Sabzevari University, Sabzevar, Iran, in 2009; and his M.S. degree from the Isfahan University of Technology, Isfahan, Iran, in 2012, where he is presently working towards his Ph.D. degree in Electrical Engineering. His current research interests include power factor correction converters and soft-switching techniques in DC–DC converters.


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Ehsan Adib was born in Isfahan, Iran, in 1982. He received his B.S., M.S. and Ph.D. degrees  in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 2003, 2006 and 2009, respectively. He is presently working as a faculty member in the Department of Electrical and Computer Engineering, Isfahan University of Technology. He is the author of more than 100 papers published in journals and conference  proceedings. His current research interests include DC–DC converters and their applications, and soft-switching techniques.