https://doi.org/10.6113/JPE.2018.18.2.356

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

A Forward-Integrated Buck DC-DC Converter with Low Voltage Stress for High Step-Down Applications

Maedeh Ghanbari Adivi^* and Mohammad Rouhollah Yazdani^†

^†,*Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran

Abstract

The combination of a buck converter and a forward converter can be considered to accomplish a high step-down non-isolated converter. To decrease the insufficient step-down ratio of a regular buck converter and to distribute switch voltage stress, a forward-integrated buck (FIB) converter is proposed in this paper. The proposed interleaved DC-DC converter provides an additional step-down gain with the help of a forward converter. In addition to its simple structure, the transformer flux reset problem is solved and an additional magnetic core reset winding is not required. The operational principle and an analysis of the proposed FIB converter are presented and verified by experimental results obtained with a 240 W, 150 V/24 V prototype.

Key words: Buck converter, Electromagnetic interference, High step-down DC/DC conversion, Voltage stress

Manuscript received Apr. 21, 2017; accepted Oct. 18, 2017

Recommended for publication by Associate Editor Joung-Hu Park.

^†Corresponding Author: m.yazdani@khuisf.ac.ir Tel: +98-31-35354001, Fax: +98-31-35354060, Isfahan (Khorasgan) Branch, Islamic Azad University

^*Department of Electrical Eng., Isfahan (Khorasgan) Branch, Islamic Azad University, Iran

Ⅰ. INTRODUCTION

Non-isolated high step-down conversion techniques are widely used in DC-DC applications such as battery chargers, distribution power systems and electric vehicles [1]-[4]. Among the non-isolated converters, the conventional buck converter is usually preferred due to its lower voltage stress, lower non- inverting voltage gain and smaller number of reactive components [5], [6]. Among isolated converters, the forward converter is usually preferred at low to medium power levels due to its reduced number of semiconductor components. However, the conventional buck converter suffers from an extremely low duty cycle and high voltage stress for the switches in high step-down applications with a high input voltage [7], [8]. Although a high step-down conversion ratio with a proper duty cycle can be obtained in the conventional forward converter by adjusting the turn-ratio of the transformer, the switch voltage stress is approximately equal to twice the input voltage. In addition, the stored energy in the leakage inductance of the transformer discharges to the switch output capacitor and causes a voltage spike on the switch leading to more electromagnetic interference (EMI). Moreover, the conventional forward converter suffers from transformer flux reset problems especially for higher-input voltages [7]. So far, most of the research on step-down convestion techniques have been carried out to solve the above mentioned problems [8]-[19].

In [8]-[11], coupled inductors are used to provide a high step-down conversion ratio and to extend the duty cycle. However, the voltage stress of the switches in these converters remains high in applications with a high input voltage. In addition, the converter proposed in [8] suffers from a high output current ripple and it has a limitation on the conversion ratio. In [9] and [10], interleaved two-phase derivations of [8] are considered, and the output current ripple is reduced by adding a third winding. However, the circuit complexity is increased. In [11], a single-input dual-output buck is introduced using a coupled inductor. However, there are voltage spikes and a high-frequency ringing across the switches and the freewheeling diode, which can increase the EMI.

A family of high step-down converters based on switched- capacitor schemes is presented in in [12], where the step-down conversion ratio increases exponentially with their orders. However, the application of these converters is limited due to a lack of voltage regulation. In addition, the number of switches and diodes is high which leads to a reduction in efficiency and an increase in cost.

In [13]-[18], improved multiple-phase interleaved buck converters are presented. The converters proposed in [13], [14] provide a higher step-down voltage gain and lower voltage stress on the power switches when compared to the conventional buck converter. However, for high input voltage and low output voltage applications, the voltage conversion ratio is not low enough and extremely small operating duty cycles are required, which makes the converter efficiency low. In order to upgrade the step-down conversion ratio, multiphase interleaved buck converters with low voltage stresses on switches and diodes are presented in [15]-[18]. These converters have a higher step-down voltage gain when compared to the converters in [13], [14]. Therefore, the duty cycle is extended and the corresponding conduction losses can be reduced. As a result, the efficiency can be improved. However, these converters use too many components and need at least four active switches. Thus, they are suitable for high output current or high power level applications. In addition, the input and output grounds of the converters proposed in [16]-[18] are separated, which leads to limitations in terms of applications and a complicated control circuit. In [19], a buck converter with a tapped inductor is proposed. However, the operation mode is only the critical conduction mode (CRM).

One way to obtain a high step-down ratio in a non-isolated topology is to insert a dc voltage source into the input of a buck converter as shown in Fig. 1. Accordingly, the voltage gain of the converter is:

                          (1)

Fig. 1. Buck converter with a series input dc voltage.

where D is the duty cycle of S₁. V_dc can be implemented by a capacitor. However, an isolated converter should be added to provide the ampere-second balance of the capacitor. By properly selecting an isolated converter, many advantages such as high step-down capability and distributed voltage stresses can be achieved. To implement the circuit, a buck converter and a forward converter can be simply integrated. As a result, a forward integrated buck (FIB) converter is derived as shown in Fig. 2, where C₁ acts as the V_dc of Fig. 1. There are two capacitors in series, which are connected to the DC input voltage like a regular half-bridge converter, where C₁ and C₂ are charged by a DC input voltage with a positive current. The C₁ current is negative when S₁ is turned on, and C₂ current is negative when S₂ is turned on.

Fig. 2. Proposed forward integrated buck (FIB) converter.

The proposed converter uses two active switches where the voltage stress of one switch is equal to the input voltage. However, this switch is turned on at a voltage that is much less than the input voltage. Consequently, its capacitive turn-on losses are reduced. In addition, the mentioned switch turns on under the zero current switching (ZCS) condition. The voltage stress of the other switch is much less than the input voltage. In the proposed converter, the transformer flux reset problem is solved and there is no need to use any reset winding, which leads to a simpler structure. Moreover, the energy stored in the leakage inductance is absorbed by C₂ and is recycled. This paper is organized as follows. The proposed high step-down converter is explained in Section II. Its operational principles and design considerations are presented in Section III, and experimental results are shown in Section IV. Section V presents some concluding remarks.

Ⅱ. OPERATING PRINCIPLES

In the proposed converter, two active switches are controlled by two PWM pulses that are 180^◦ out of phase. The converter has seven distinct operating intervals in a switching period. Fig. 3 shows typical key waveforms at the steady state, and Fig. 4 illustrates the equivalent circuit of the proposed converter for each interval. In order to simplify the analysis, the following assumptions are made.

Fig. 3. Key waveforms of the proposed converter.

Fig. 4. Equivalent circuit for each of the operating intervals.

⋅ All of the active switches and diodes are ideal.

⋅ The capacitors C₁, C₂ and C_o are large enough so that their voltage variations can be ignored.

⋅ L₁ and L₂ are equal and large enough to assume that their currents are approximately constant.

Before the first interval, it is assumed that both of the switches are turned off, the diodes D₃ and D₄ are reversed biased, and the diodes D₁ and D₂ are conducting.

Interval 1 [t₀-t₁]: This interval begins when the switch S₁ turns on and the voltage V_C1 is applied to the inductor L_lk. Therefore, i_lk increases linearly from zero. The smooth increment of the current through the inductor L_lk ensures the zero current switching (ZCS) turn-on condition for the switch S₁ and the diode D₃. During this interval, the diodes D₄ is reverse biased and S_{2‌ is turned off.} This interval ends when the diode D₁ turns off under the ZCS condition. The important equations of this interval are as follows:

                  (2)

                          (3)

               (4)

              (5)

                   (6)

Interval 2 [t₁-t₂]: During this interval, V_C1 is applied to L_lk+L_m. Therefore, V_NP is equal to V_C1.L_m/(L_m+L_lk). During this interval i_S1 and i_D3 are obtained as follows:

   (7)

      (8)

Interval 3 [t₂-t₃]: At the beginning of this interval, the switch S₁ turns off and the diodes D₄ and D₁ start conducting. By the conduction of D₄, the voltage across S₁ is clamped to V_in. The voltage V_C2 is inversely applied to the inductor L_lk, and its current decreases until it reaches i_Lm(t₂). In this way, the leakage energy is absorbed and the voltage spikes across the switch S₁ are eliminated, which is an advantage from an electromagnetic compatibility (EMC) viewpoint. The current difference between i_Lm and i_lk is transferred to the secondary side of the transformer. When i_lk becomes equal to i_Lm(t₂), the diode D₃ turns off under the ZCS condition and this interval ends.

              (9)

                       (10)

               (11)

                     (12)

Interval 4 [t₃-t₄]: During this interval, V_C2 is reversely applied to L_lk+L_m. Therefore, the current of D₄ is smoothly decreased. The diodes D₁ and D₂ are conducting. As a result, L₁ and L₂ are discharged. In this interval, both of the switches are turned off and D₃ is reverse biased. The important equations of this interval are as follows:

               (13)

          (14)

Interval 5 [t₄-t₅]: At t₄ the switch S₂ is turned on. Therefore, the diode D₂ turns off. The voltages -V_o and V_C2‌-V_o are applied to the inductors L₁ and L₂, respectively. Therefore, the inductor L₁ is discharged and the inductor L₂ is charged. During this interval, i_D4 is still decreased. When i_D4 reaches zero, D₄‌ turns off under the ZCS condition and this interval ends.

               (15)

       (16)

        (17)

Interval 6 [t₅-t₆]: In this interval, the switch S₂ and the diode D₁ are turned on and all of the other semiconductor devices are off. In addition, L_1‌ is discharged and L₂ is charged. This interval continues until S₂ turns off at t₆. 

Interval 7 [t₆-t₇]: At t₆, S₂ is turned off. Therefore, D₂‌ starts conducting. In this interval, the inductors L₁ and L_2‌ are discharged. This interval continues until the switch S₁ turns on again. At t₇, one switching cycle is completed and the operation is repeated.

              (18)

               (19)

Ⅲ. CONVERTER ANALYSIS AND DESIGN CONSIDERATIONS

A. DC Conversion Ratio

The voltages of V_C1 and V_C2 can be obtained from the volt-second-balance of L₁ and L₂, respectively.

                               (20)

                                (21)

where n is the turn ratio N_P/N_S, D is the duty cycle of S₁‌, and Dˊ is the duty cycle of S₂. Since V_in is equal to V_C1+V_C2, the DC conversion ratio of the converter is obtained as follows:

           (22)

                     (23)

If , then

                          (24)

Fig. 5 shows a comparison between the voltage conversion ratio versus the duty cycle of the proposed converter under n‌=1, both the conventional buck converter and the conventional forward converter under n=1, and the buck converter with a tapped inductor (turn ratio, n=1), which presents the benefit of the proposed converter for achieving a high step-down conversion ratio. Although the cost and size of the buck converter with a tapped inductor in [19] are lower, the proposed converter has a better conversion ratio. To make sure that L_m is reset in the proposed converter:

                                (25)

Fig. 5. Voltage conversion ratio versus the duty cycle of the proposed converter with n=1 for a regular buck converter, a regular forward converter (n=1) and the buck converter with a tapped inductor (n = 1).

According to (25), is limited to 0.5 like the conventional forward converter for n=1. Fig. 6 shows the voltage conversion ratio versus the duty cycle of the proposed converter under different turn ratios. In Table I, the proposed converter is compared to the conventional interleaved buck converter and the converters proposed in [13] and [14].

Fig. 6. Voltage conversion ratio versus the duty cycle of the proposed converter under different turn ratios.

TABLE I COMPARISON BETWEEN THE PROPOSED CONVERTER AND THREE OTHER CONVERTERS

Items	Interleaved Buck	Converter in [13]	Converter in [14]	Proposed Converter
Conversion ratio
Voltage stress of switches
Voltage stress of diodes

B. Semiconductor Stress Analysis

When S₁ turns off, its voltage stress is equal to V_in. Since, the switch S₁ turns on at a voltage that is equal to V_C1, the switch capacitive turn-on loss (which is proportional to the square value of the switch voltage at the turn-on time) decreases too much. When S₁ turns on, the D_4‌ voltage stress is equal to V_in. In addition, when S₂ is off, its voltage stress is equal to V_C2 and the voltage stress of D₂ is equal to V_C2. A voltage stress analysis is shown in Table I, and the current stresses are summarized in Table II.

TABLE II SEMICONDUCTOR CURRENT STRESS ANALYSIS

Items	Formula
RMS current stress of S1
RMS current stress of S2
Average current stress of D1
Average current stress of D2
Average current stress of D3
Average current stress of D4

In order to implement the control circuit of the proposed converter, a SG3525 PWM controller IC is used and it has the capability of generating two pulses with a proper delay as shown in Fig. 7. Therefore, two interleaved pulses are produced. The duty cycle limiter limits the maximum duty cycle according to the value determined by (25) for a given n by adjusting the resistor. Since the maximum duty cycle ratio of the SG3525 is 50%, the limiter section is removed for n=1.

Fig. 7. PWM control scheme of the proposed converter.

Ⅳ. EXPERIMENTAL RESULTS

In order to verify the theoretical analysis, a 150 V to 24 V/10A prototype of the proposed converter is implemented as shown in Fig. 8. The specification and components of the proposed converter are illustrated in Table III. The values of the magnetizing inductance, output inductor and output capacitor of the forward and buck converter sections are designed like regular forward and buck converters, where the inductors L₁ and L₂ are calculated to operate in the continuous current mode at 240-W of output power. The capacitors C₁ and C₂ are 4.7 μF to have a negligible voltage variation.

Fig. 8. Photo of the power section of the prototype.

TABLE III PARAMETERS OF THE IMPLEMENTED PROTOTYPE

Parameter	Value
Switching frequency	100 kHz
Switch S1‌	IRF640
Switch S2‌	IRF540
Diodes D1, D2 and D3	BYV32-150
Diode D4	BYV27-200
n,	1
Lm , Llk	500H, 10H
Inductors L1‌ and L2	300H
Capacitors C1 and C2	4.7F / 100V
Capacitor Co	22F / 50V

Fig. 9 shows voltage and current waveforms of the switch S₁ and the diodes D₁, D₃ and D₄. As can be observed from Fig. 9(a), the voltage stress of the switch S₁ is equal to V_in. Before S₁ turns-on, the voltage across S₁ is equal to V_C1, which is much lower than V_in. Hence, the switch capacitive turn-on losses decrease too much. There are no considerable high voltage spikes across S₁ which is beneficial to the EMC [20]. On the other hand, with a regular high step-down buck converter with a tapped-inductor, the leakage inductance causes huge voltage spike [8]. Moreover, S₁ turns on under the ZCS condition as shown in Fig. 9(b).

Fig. 9. Voltage and current waveforms of: (a) S₁ (time scale 1µS/div), (b) S₁ (time scale 250nS/div), (c) D₁, (d) D₃, (e) D₄.

(a)

(b)

(c)

(d)

(e)

According to Fig. 9 (c), (d) and (e), the voltage stresses of the diodes D₁ and D₃ are less than the diodes voltage stress in a conventional interleaved buck converter. Moreover, the voltage stress of the diode D₄ is equal to the input voltage. Fig. 10 shows voltage and current waveforms of the switch S₂ and the diode D₂. From this figure, it can be seen that the voltage stress of S₂ and D₂ is about 80 V, which is less than the voltage stress of the switches in conventional interleaved buck and conventional interleaved forward converters. Table IV shows a loss analysis of the proposed converter.

Fig. 10. Voltage and current waveforms of: (a) S₂, (b) D₂.

(a)

(b)

TABLE IV IMPORTANT LOSSES IN THE PROPOSED CONVERTER

Type of loss	Element	Value (W)
Switches conduction losses (W)	S1	4.5
	S2	1.1
Switching losses (W)	S1	2
	S2	2.1
Diodes conduction losses (W) ,	D1	2
	D2	2.3
	D3	1.2
	D4	0.4
Other Losses (Gate driver, Core losses, …)	-	2

Fig. 11 shows a comparison between the efficiencies of the proposed converter and a conventional interleaved buck converter. For the conventional interleaved buck converter, IRF640 and MUR840 are used as switches and diodes, respectively. In addition, the value of the inductors is selected as 300μH. According to Fig. 11, the proposed converter provides a higher efficiency, and its efficiency at full load is around 92.7%. Since the buck section of the proposed circuit has a lower input voltage with respect to the regular interleaved buck converter, a MOSFET with a lower voltage stress and a lower R_ds(on) is employed for the buck section. Consequently, the conduction loss of the proposed converter is reduced in comparison to the conventional interleaved buck converter. It should be mentioned that to achieve a higher step-down conversion ratio, the turn ratio n is increased in the proposed converter. In this condition with a similar output power, the output voltage is decreased and the current of the components is increased which can result in more conduction losses according to the formulas in Table IV, and the efficiency may be reduced. The dynamic response of the proposed converter with the PWM controller of Fig. 7 is illustrated in Fig. 12 when the load is changed from a full load to a light load and vice versa. This confirms the proper operation of the PWM controller.

Fig. 11. Efficiency comparison between the proposed converter and a conventional interleaved buck converter.

Fig. 12. Dynamic response of the proposed converter (n=1).

Ⅴ. CONCLUSION

In this paper, an interleaved converter has been proposed that has the advantages of low switch voltage stress, low output current ripple, low switching losses, and an improved step- down conversion ratio, which makes it a good candidate for high input voltage, low output current ripple and non-isolated step-down converters. All of these benefits are obtained without any additional stress on the components. Experimental results based on a 200 V/ 24 V–10A prototype verify the theoretical analysis. According to the efficiency curves, the proposed converter has a better efficiency in comparison to the regular interleaved buck converter.

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Maedeh Ghanbari Adivi received her B.S. degree in Electrical Engineering from the Najafabad Branch, Islamic Azad University, Isfahan, Iran, in 2013; and her M.S. degree in Electrical Engineering from the Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran, in 2016. Her current research interests include switching power converters and EMI.

Mohammad Rouhollah Yazdani received his B.S. degree in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 2001; his M.S. degree in Electrical Engineering from the Najafabad Branch, Islamic Azad University, Isfahan, Iran, in 2004; and his Ph.D. degree in Electrical Engineering from the Sciences and Research Branch, Islamic Azad University, Tehran, Iran, in 2011. Since 2011, he has been a Faculty Member in the Department of Electrical and Computer Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran. His current research interests include soft-switching converters, EMI reduction techniques, signal integrity and EMC issues.