https://doi.org/10.6113/JPE.2018.18.2.375

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Active Controlled Primary Current Cutting-Off ZVZCS PWM Three-Level DC-DC Converter

Yong Shi^†

^†College of Electrical & Information Engineering, Shaanxi University of Science & Technology, Xi’an, China

Abstract

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

Key words: Three-level (TL) dc/dc converter, Zero-current switching (ZCS), Zero-voltage switching (ZVS)

Manuscript received Mar. 30, 2017; accepted Nov. 4, 2017

Recommended for publication by Associate Editor Yan Xing.

^†Corresponding Author: shiyong@sust.edu.cn Tel: +86-029-8616-8631, Fax: +82-029-8616-8631, Shaanxi Univ. of Sci. Tech.

College of Electrical & Information Engineering, Shaanxi University of Science & Technology, China

I. INTRODUCTION

High input isolated dc-dc converters can be used in many industry applications, such as dc-dc converters for microgrids, distributed power systems, renewable energy power systems and big data centers [1]-[4]. To achieve high system efficiency performance, the DC link voltages of these converters may reach 800V, and sometimes may be even higher than 1000V [2]. To match the voltage rating of the primary switches with widely used low voltage power devices, a lot of three-level (TL) dc-dc converters (TLCs) have been proposed and analyzed [5]. In 1992, the first TLC was reported in [6], which obtains one-half of the voltage stress on each of the primary switches due to the series connected structure. A TLC with no clamping diodes was proposed in [7], which features a simple and compact primary circuit with the same output performance when compared to that of diode-clamped TLC. However, this converter is not suitable for large power applications due to serious input current discontinuity. Some basic TLCs were analyzed and compared in [8]. A full bridge (FB) TLC with a simplified switching scheme was reported in [9], and the primary switches in this converter can obtain zero-voltage switching (ZVS) or zero-current switching (ZCS) in a wide load range. A number of new TLCs were proposed in [10]-[12], which have different advantages. Soft switching schemes of the diode clamped TLC were discussed in [13], and some new wide range soft switching TLCs were also proposed. An asymmetric voltage distribution ZVZCS TLC was proposed in [14], in which hybrids of MOSFETs and IGBTs are used as primary switches because of different voltage distributions on the switching pairs. In [15], a wide range soft switching three-phase TLC was reported, which is well suitable for large power applications. A fault detection and protection scheme for a TLC was discussed in [16]. To reduce the volume of the passive components, some new TLCs with TL secondary rectified voltage waveforms were proposed and discussed in [17]-[19]. All of above mentioned references have made good contributions to this topic.

In [10] and [13], several diode-clamped zero-voltage and zero-current switching (ZVZCS) TLCs were proposed and discussed. These TLCs have some common advantages, such as a wide soft switching load range and a simple switching scheme. However, limitations still exist. For the primary current diode cutting-off ZVZCS TLC in [13], two series diodes, referred to as cutting-off diodes, are added to block the reverse primary current, which causes more conduction loss. In addition, the cutting-off diodes are directly inserted into the circuit loop of the primary switches and the input capacitors, which increases the parasitic inductance of the circuit loop. Therefore, large snubber capacitors are needed to absorb the reverse recovery energy during the turn-off instant. A large number of snubber capacitors increases the system volume and causes some heat problems. Thus, the power rating of the primary diode cutting-off ZVZCS TLCs may be limited. For the secondary clamping ZVZCS TLCs in [10] and [13], some secondary reset devices are used to control the current reset instant, and the voltage of the clamping capacitor is applied to the leakage inductance of the transformer to reset the primary current. However, the added active or passive power devices are switched in the hard switching mode, which results in auxiliary switching loss. Furthermore, the current ratings of the active switch and the clamping capacitor are identical to the output current. Thus, this converter is not suitable for large power dc-dc conversions, especially for low output voltage and high output current applications. Hence, it is still a valuable task to find a new ZVZCS TLC for large power applications without the abovementioned problems.

In this paper, a novel active controlled primary current cutting-off ZVZCS PS PWM TLC is proposed. This paper is organized as follows. The configuration and basic operation principle are provided in Section II. Analyzes of the features and a comparison are described in Section III. Experimental results are shown in Section IV. Finally, some conclusions are given in Section V.

II. CONFIGURATION AND OPERATION PRINCIPLE

A. Configuration

Fig. 1 shows the proposed circuit. In the primary side, S₁ to S₄ are series connected, and the OFF voltage on these switches is clamped by D_cl1 and D_cl2. In Fig. 1, the body diodes of S₂ and S₃ are removed since these diodes do not take any effect during operation. However, it should be pointed out that power devices with body diodes can also be used as S₂ and S₃. C_ss is a flying capacitor to assist in the ZVS of the leading-leg switches; C_BL is a blocking capacitor with a specific value to generate the reset voltage of i_p during the free-wheeling stages; S₅ and S₆ are series MOSFETs referred to as cutting-off MOSFETs in this paper, which are used for cutting-off the primary current during the free-wheeling stages; C_in1 and C_in2 are the input capacitors; and L_lk is the leakage inductance. In the secondary side, D_o1 and D_o2 are the rectifier diodes, and the output filter is composed of L_o and C_o. R_o is the load resistor. The dash line rectangle in Fig. 1 is the circuit loop with a low parasitic inductance requirement. The reduced area of the circuit loop in the dash line rectangle results in a low parasitic inductance, which reduces the voltage spike on the primary switches during the turn-off instant.

Fig. 1. Active controlled primary current cutting-off ZVZCS PWM TLC.

B. Operation Principle

Before the analysis, some assumptions are set to simplify the explanation. All of the components in the topology are ideal; C_in1 and C_in2 are large enough, and their voltage ripple can be neglected; C_BL is designed with a specific value to ensure the ZCS of S₂ and S₃; the output filter and load are replaced by a constant current source I_o; the turn ratio in Fig. 1 is k_T; and C_os is the output capacitance of S₁ and S₄. The basic operation principle is provided in Fig. 2. As shown in Fig. 2, four primary switches are switched in the phase-shift (PS) switching scheme. S₁ and S₄ are switched as the leading-leg switches, while S₂ and S₃ are the lagging-leg switches. The duty ratio is represented as D in this paper, and the output voltage is varied from V_in/2k_T to 0 with different values of D. There are 14 operation stages in each switching cycle, and the operation stages in the first half switching cycle are depicted in Fig. 3.

Fig. 2. Basic operation principle.

Fig. 3. Operation stages of the proposed converter: (a) stage 1; (b) stage 2; (c) stage 3; (d) stage 4; (e) stage 5; (f) stage 6; (g) stage 7.

Stage 1 [Fig. 3(a)]: Before t₀, the input powers the load. S₁ and S₂ are ON. D_o2 is conducted while D_o1 is OFF. S₅ and S₆ are ON, and the added conduction loss is very small because S₅ and S₆ have extremely low on-resistances. The voltage on C_BL increases linearly with time and its slope is:

   (1)

During this stage, v_BC=V_in/2-v_CBL; v_rect= (V_in/2-v_CBL)/ k_T; and i_P = I_o/k_T.

Stage 2 [Fig. 3(b), t₀-t₁]: At t₀, S₁ is turned OFF at zero-voltage due to the existence of C₁, v_CBL increases and reaches its peak value V_CBLMAX at the end of this stage, i_P=I_o/k_T, and i_P charges C₁ and discharges C₄ through C_ss linearly with time. This stage continues until v_C1= V_in/2 and v_C4 =0. At the end of this stage, D₄ and D_Cl1 are conducted naturally, the circuit operates in the free-wheeling mode, and both of the rectifier diodes are conducted. S₄ must be gated on to achieve ZVS after t₁.

Stage 3 [Fig. 3 (c), t₁-t₃]: At t₁, D_cl1 and D₄ are ON, and S₄ is turned on with ZVS at t₂. i_p is free-wheeled through D_cl1, S₂ and L_lk; and both of the rectifier diodes are conducted. i_P decreases because v_CBL is directly applied to L_lk, and its expression is:

         (2)

When i_P=0, the operation of this stage is finished, and the interval of this stage is:

        (3)

Stage 4 [Fig. 3(d), t₃-t₄]: At t₃, i_P decays to zero. S₅ is OFF with ZCS. i_P cannot flow through the primary coil in the reverse direction because of D₅. After t₃, i_P is kept zero. Thus, S₂ can achieve ZCS. The voltage of C_BL is kept constant. The voltage on S₅ is V_CBLMAX.

Stage 5 [Fig. 3(e), t₄-t₅]: At t₄, S₂ is turned OFF with ZCS. i_P is kept zero. The voltage of C_BL is kept constant. The voltage on S₅ is V_CBLMAX.

Stage 6 [Fig. 3(f), t₅-t₆]: At t₅, S₅ is switched ON with ZCS, and i_P is kept zero. The voltage of C_BL is kept constant.

Stage 7 [Fig. 3(g), t₆-t₇]: At t₆, S₃ is ON. S₃ can achieve ZCS due to L_lk, S₄ is turned on at t₂, i_P increases linearly with time in the reverse direction, and the circuit is kept in the free-wheeling mode. i_P is:

    (4)

During this stage, the voltage of C_BL can be treated as a constant value. Therefore, the time of this interval is:

      (5)

At t₇, i_P reaches -I_o/k_T, and the free-wheeling mode is over. The primary powers the load. v_BC=-V_in/2-v_CBL; v_rect=-(V_in/2+v_CBL) /k_T; and i_P =-I_o/k_T. After stage 7, the circuit is operated in the second half switching period.

III. TECHNICAL ANALYSIS

A. ZVS of the Leading-Leg Switches

S₁ and S₄ are the leading-leg switches. The leading-leg switches can obtain ZVS in a wide load range because the energy stored in the output inductance can be used. S₄ is selected as an example. The switching instant is shown in Fig. 3(b), and the ZVS criteria for S₄ is:

     (6)

Where L_p^’ is equal to L_lk+k_T²L_o. The minimum load current to realize ZVS for S₄ is:

   (7)

B. ZCS of the Lagging-Leg Switches

S₂ and S₃ are the lagging-leg switches. As verified in [13], with a specific value of C_BL, the lagging switches can obtain ZCS in a wide load range. In addition, the value of C_BL is [13]:

    (8)

Where T_reset is the maximum current reset time, and T_COM is the time to allow the tail current of the IGBTs to decrease to zero. During the designing, the load current is set to the rated output current.

C. ZCS of S₅ and S₆

According to Figs. 2 and 3, S₅ and S₆ can obtain ZCS independent of the load current. S₅ is selected as an example. As shown in Figs. 2 and 3(d), S₅ is turned off at t₃, and i_P is already reset to zero at this instant. Hence, S₅ can achieve zero-current turn OFF. As shown in Figs. 2 and 3(f), S₅ is turned ON at t₅, and i_P is kept zero. Therefore, S₅ can obtain zero-current turn ON.

D. Duty Ratio Loss

The time between t₆ and t₇ in Fig. 2 is defined as the duty ratio loss caused by the leakage inductance, and the corresponding operation stage is plotted in Fig. 3(g). During this interval, i_P is:

          (9)

In addition, the time of this interval is:

    (10)

D_Loss is:

    (11)

Where D_Loss is the duty ratio loss caused by the leakage inductance.

E. Comparison

The proposed converter is compared to conventional ZVZCS TLCs, and the circuits for comparison are presented in Fig. 4. The comparison is based on the following specifications. The input voltage is 600-800V. The output voltage is 12V, and the output current is 500A. The switching frequency is 20-kHz. V_CBLMAX is 50V. 600V/75A IGBTs are used as primary switches. The k_T in each converter is 24:1.

Table I shows the added components and added cost as well as a performance comparison. In the proposed converter, two MOSFETs (IPT020N10N3) with extremely low on resistances are required to reset the primary current. In Fig. 4(a), two diodes are series connected with S₂ and S₃. However, since the power losses of these diodes are considerably larger than those of the MOSFETs in the proposed converter, four diodes are required as cutting-off diodes in the converter of Fig. 4(a). As a result of the high current rating of the secondary reset components, the number of active switches and reset capacitors of the converter in Fig. 4(b) are the largest among the three converters. As depicted in Table I, the added cost of the proposed converter is minimum among the three converters.

Fig. 4. Conventional ZVZCS TLC. (a) Diode cut-off. (b) Secondary side active reset.

(a)	(b)

TABLE I ADDED COMPONENTS, ADDED COST AND A PERFORMANCE COMPARISON

Item	Proposed	Fig. 4 (a)	Fig. 4 (b)
Added power electronics devices	Cutting-off MOSFETs (2* IPT020N10N3)	Cutting-off diodes (4* MMF100F20B)	Active reset MOSFETs (5* T020N10N3)
Added passive components	Blocking capacitor (4㎌/50A)	Blocking capacitor (4㎌/50A)	Reset capacitor (10*0.1㎌/100A)
Added cost	$15	$30	$75
Added conduction loss	5W	67W	20W
Added Switching loss	None	None	10W
Parasitic inductance of circuit loop in dash line rectangle	27nH	105nH	27nH

The parasitic inductance among the dc input bus bar and the IGBTs is a key point in high input and high frequency dc-dc power conversion. A large parasitic inductance causes a large over-shoot voltage on the IGBTs during turn-off switching instants, which demands a large value of snubber capacitors to reduce the voltage spike. In addition, snubber capacitors with a large value handle more resonant energy, which causes a thermal problem and reduces the expected lifetime of these capacitors. Hence, the parasitic inductance among the dc input bus bar and the IGBTs should be as low as possible to ensure the safe operation of high input and high frequency dc-dc converters. The dash line rectangles in Figs. 1 and 4 are circuit loops with low parasitic inductance requirements, and the parasitic inductances include the inner parasitic inductances of IGBTs and the parasitic inductances among the input capacitors, lamination bus bar and IGBTs. The layouts of the IGBTs and lamination bus bar of the proposed converter and the converters in Fig. 4 are illustrated in Fig. 5. Since the configurations of the primary clamping circuits are identical in these converters, the clamping devices of the primary side are not shown in Fig. 5 for the sake of simplicity. It is clearly the area of a circuit loop with low parasitic inductance requirements in the proposed converter, and the converter in Fig. 4(b) is much lower than that of Fig. 4(a). The values of the parasitic inductances of Fig. 5(a) and (b) are simulated by Ansoft Maxwell, and the parasitic inductance of Fig. 5(a) is about 27nH. However, the total parasitic inductance of Fig. 5(b) is about 105nH. Table I illustrates an added conduction loss comparison. Since two MOSFETs with extremely low on-resistances are used, the total added conduction loss of the proposed converter is much lower than that of Fig. 4.

Fig. 5. Layouts of the IGBTs and lamination bus bars for: (a) proposed converter and Fig. 4(b), (b) Fig. 4(a).

(a)

(b)

From the above analyses, it can be concluded that the proposed converter has some clear advantages such as a low parasitic inductance among the dc input bus bar and IGBTs, low added cost, easy designing and manufacturing of the lamination bus bar, smaller value and current stress of the snubber capacitors of the IGBTs, and low added conduction loss.

IV. EXPERIMENTAL RESULTS

A 6-kW laboratory prototype has been built to verify the operation principle of the proposed converter. The main parameters of the prototype are listed in Table II. The switching frequency is set to 20kHz as an example, and the switching frequency for a real product can be further increased. The voltage distribution among the primary switches is similar to those of the converters of [10] and [13]. It is demonstrated in [10] and [13] that the OFF voltage on the primary switches in those converters is even during operation. Therefore, a voltage waveform of the primary switches is not provided in this paper for the sake of simplicity.

TABLE II MAIN PARAMETERS OF THE PROTOTYPE

Item	Parameters
Input	600-800V
Output	12V/500A
Switching frequency	20-kHz
IGBT	MMG75S060B6EN
CBL	3㎌/30A
Primary current sensor	25A/100mA
MOSFET driver	MIC4451
Lm	50mH
Llk	10㎌
Core type	Toroidal
kT	24:1
Conductor area of primary coils	8mm2(enameled wire)
Conductor area of primary coils	125mm2(copper bar)
S5 and S6	IPT020N10N3
Rectifier diodes	MMF400S040DK2B
Synchronous MOSFETs In efficiency test	IPT020N10N3
Lo	2㎌

Fig. 6 shows the control signals of S₁, S₃, S₄ and S₅. After S₁ is turned OFF, as illustrated in Fig. 6, S₅ is turned off with ZCS at t₁. Before S₃ is turned on, as depicted in Fig. 6, S₅ is turned on with ZCS at t₂.

Fig. 6. Control signals of S₁, S₃, S₄ and S₅.

As shown in Fig. 7, v_BC is not a constant value during the power transfer stages because the voltage of the blocking capacitor changes linearly. The dash line circles in Fig. 7 illustrate the primary reset voltage caused by C_BL. As shown in Fig. 8, i_P is reset to zero during the freewheeling stages. Thus, the lagging-leg switches can obtain ZCS, and the primary circling current is minimized.

Fig. 7. Waveform of v_BC.

Fig. 8. Waveform of i_P.

As shown in Fig. 9, v_CBL increases or decreases linearly during the power transfer stages, and is kept constant during the free-wheeling stages. The voltage of v_S5+v_S6 is provided in Fig. 10, and it can be concluded that the voltage stress of each cutting-off switch is V_CBLMAX. Since V_CBLMAX in the prototype is only 50V, MOSFETs with low voltage ratings and extremely low on-resistances can be used as cutting-off switches. Waveforms of v_Do1 and i_Lo are depicted in Figs. 11 and 12.

Fig. 9. Waveform of v_CBL.

Fig. 10. Waveforms of v_S5 and v_S6.

Fig. 11. Waveform of v_Do1.

Fig. 12. Waveform of i_Lo.

The soft switching characteristics are depicted in Fig. 13 to Fig. 17. With the parameters of the prototype, the ZVS load ranges of S₁ and S₄ are from 10A to the rated current, and the ZCS load ranges of S₂ and S₃ are below the rated output current. As illustrated in Fig. 13, S₅ is switched ON at t₁, and i_P is kept zero. Therefore, S₅ can obtain zero-current turn on. As shown in Fig. 13, S₆ is switched OFF at t₂, and i_P has already been reset to zero. Thus, S₆ can obtain zero-current turn OFF. As shown in Fig. 14, v_CE (S₃) reaches V_in at t₁. However, i_P is still zero. Thus, it can be concluded that S₃ can obtain ZCS. As shown in Fig. 15, v_GE (S₁) reaches zero at t₁. However, v_GE (S₁) still has a negative value. Thus, S₁ can obtain ZVS operation. From Figs. 16 and 17, it can be concluded that S₄ can obtain ZVS operation, and S₂ can obtain ZCS operation.

Fig. 13. ZCS of S₅ and S₆.

Fig. 14. ZCS of S₃.

Fig. 15. ZVS of S₁.

Fig. 16. Waveforms of v_S4 and i_S4.

Fig. 17. Waveforms of v_S2 and i_S2.

In the efficiency test, the converter in Fig. 4(a) is also tested for comparison. Efficiency results are provided in Fig. 18 and the efficiency of the proposed converter with a synchronous rectifier is shown in Fig. 18. As synchronous rectifier is a well proven technology in power electronics. Thus, the operation principle is not provided here for the sake of the simplicity, and the components used in the synchronous rectifier are depicted in Table II.

Fig. 18. Efficiency comparison results.

The primary switches, rectifier diodes and output filters used in Figs. 1 and 4(a) are identical to the parameters in Table II. 4×MMF100F20B are used as cutting-off diodes in Fig. 4(a). The power loss of the rectifier, the auxiliary power to the controller and the driver are taken into account in the efficiency test. As shown in Fig. 18, the efficiency of the proposed converter is a little higher than that of the converter in Fig. 4 due to a reduced added conduction loss. The output voltage is only 12V, as shown in Fig. 18. Thus, a synchronous rectifier may be a better choice. The main power loss distribution with 400A load current is depicted in Fig. 19. Fig. 20 shows a photo of the prototype.

Fig. 19. Main power loss distribution with a 400A load current.

Fig. 20. Photo of the prototype.

V. CONCLUSIONS

A novel active controlled primary current cut-off ZVZCS TLC is proposed in this paper. The theoretical analysis is verified with a 6-kW laboratory prototype. The improvements of the proposed converter are listed as follows: the leading-leg switches can obtain zero-voltage switching (ZVS) and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range; two MOSFETs with extreme low on-resistances are used as primary current active controlled cutting-off components, and the maximum added conduction loss is only about 0.05% of the rate power; the active controlled cutting-off MOSFETs are switched ON and OFF with ZCS, and there are no added switching losses; and the added MOSFETs are not series connected in the circuit loop of the dc lamination input bus bar and IGBTs, which results in lower parasitic inductances among the dc input lamination bus bar and IGBTs. Finally, the cost of the added components is only about 1.25% of the total cost. Therefore, the proposed converter is a promising solution for high input and high frequency large power dc-dc conversion.

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Yong Shi was born in Henan, China, in 1974. He received his M.S. and Ph.D. degrees in Electrical Engineering from Xi’an Jiaotong University, Xi’an, China, in 2002 and 2005, respectively. From 2007 to 2016, he was a Senior Engineer with the Xi’an Action Power Electrical Co. Ltd., Xi’an, China. In 2016, he joined the Shaanxi University of Science & Technology, Xi’an, China, where he is presently working as a Professor in the College of Electrical & Information Engineering. He has published over 30 papers on subjects related to power electronics in journals and conference proceedings. His current research interests include soft-switching dc/dc converters, power factor correction converters, matrix converters, and multilevel converters.