https://doi.org/10.6113/JPE.2018.18.2.383

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Isolated PFC Converter Based on an ADAB Structure with Harmonic Modulation for EV Chargers

Seung-Won Choi^*, Yoon-Jae Kim^*, Il-Oun Lee^*, and Jun-Young Lee^†

^†,*Dept. of Electrical Eng., Myong-Ji University, Yong-In, Korea

Abstract

This paper presents an isolated power factor correction converter for general-purpose electric vehicle chargers with a wide output voltage range. The converter is based on an asymmetrical dual active bridge structure so that the voltage stress of switching devices can be eliminated by transferring the transformer leakage inductance to the circuit parameters. Harmonic and output controls are performed by secondary switches, and primary switches are only operated at a fixed frequency with a 50% duty ratio. A harmonic modulation technique is also adopted to obtain a near-unity power factor without input current monitoring. The feasibility of the proposed charger is verified with a 3.3 kW prototype.

Key words: Battery charger, Electric vehicles, PFC converter

Manuscript received Aug. 25, 2017; accepted Nov. 18, 2017

Recommended for publication by Associate Editor Yan Xing.

^†Corresponding Author: pdpljy@mju.ac.kr Tel: +82-330-6357, Fax: +82-330-6977, Myong-Ji University

^*Dept. of Electrical Eng., Myong-Ji University, Korea

I. INTRODUCTION

New transportation methods are required to solve air pollution and reduce greenhouse gas emission, and vehicle electrification has been proposed as a solution. Various types of plug-in vehicles (xEVs) are available, and examples include battery electric vehicles (BEVs), hybrid EVs, plug-in hybrid EVs, and fuel-cell EVs (FCEV). These vehicles can also be classified as long-range and neighborhood EVs. Except for FCEV, most xEVs use battery packs as power sources, and they are designed with various battery voltages depending on battery usage [1]-[3]. A dedicated design is possible because on-board chargers mounted on vehicles deal with a specified battery only. However, off-board chargers utilized for electric bicycles and various vehicles should possess a wide output voltage range [4], [5]. In the near future, general-purpose on-board chargers will be required due to the increase in the production of xEVs. In single-phase applications, on-board and off-board chargers have a common conventional two-stage structure composed of a non-isolated boost converter as a harmonic pre-regulator, and various isolated DC/DC converters are used for electrical isolation and charging control [6], [7]. The most popular topology for isolated DC/DC converters is the phase-shift full-bridge (PSFB) converter that involves the “buck-type” operation; hence, it is applicable for general-purpose chargers due to its wide output voltage range. However, the PSFB converter cannot achieve high efficiency due to disadvantages, such as voltage stress of secondary circuits, large circulating current, narrow zero-voltage-switching (ZVS) range, and loss of snubber circuits [8]-[11]. Many resonant topologies have been introduced, and high efficiencies have also been reported due to the good characteristics, such as soft switching, low electrical stress in the rectifier, and absence of additional snubber circuits, of these topologies. However, they do not have wide output voltage ranges, and they are adequate for a charger design dedicated to a specified battery only [12]-[17]. Moreover, pulse-width modulation (PWM) resonant converters, which possess the same structure as series resonant converters (SRC) but adopt the PWM operation, can produce output voltages larger than those of resonant converters given an appropriate design. However, widening the output voltage range to be used for general-purpose chargers is difficult [18]. To obtain a wide output voltage range that is sufficient for general-purpose chargers, a two-stage structure composed of isolated power factor correction (PFC) and non-isolated DC/DC converters can be considered. Given that non-isolated converters can be designed to achieve high efficiency, the entire efficiency of the charger is determined by the efficiency of the isolated PFC converter. Most of the topologies available for isolated PFC converters use a current-fed structure. However, this structure suffers from serious voltage spikes in the primary switches caused by transformer leakage inductance, and auxiliary snubber circuits are required to suppress the voltage spikes. High- voltage-rating devices are still required, which pose an obstacle to obtaining good efficiency and increased switching frequency [19]-[25]. Another method for isolated PFC converters is the valley-fill circuit based on SRC. This method has good topological merits due to the voltage-fed structure, but it suffers from high current stress caused by resonant operation and has various problems caused by a low switching frequency at a light load [26]. Several isolated PFC approaches that use an asymmetrical dual active bridge (ADAB) converter have been presented; the ADAB structure has various operational modes [27]. Among these modes, the “boost discontinuous conduction mode (DCM) operation” is adequate in reducing the switching loss of the primary switch due to ZV-ZCS switching characteristics and can provide the availability of IGBT and MOSFET as switching devices. However, this operational mode has the disadvantages of low power factor and high switching loss of the secondary switch, which pose obstacles to high-power designs, such as EV battery chargers.

This paper presents an isolated PFC converter design based on the ADAB structure. By operating the converter under the boost-DCM operation, the primary switches can be operated at a fixed frequency with a 50% duty ratio, which leads to good switching conditions of zero-voltage turn-on and zero- current turn-off. All harmonic and output controls are performed by secondary switches, and the harmonic modulation technique [28] is adopted to obtain a near-unity power factor without input current monitoring. It provides a simple control scheme so that a simple digital controller is available. To verify the feasibility of the proposed circuit, the circuit is implemented and tested using a 3.3 kW charger.

II. PROPOSED CONVERTER

Fig. 1 presents a schematic of the charger composed of the proposed isolated PFC converter with harmonic modulation technique and a buck converter for battery charging control. Galvanic isolation and harmonic regulation are accomplished in the PFC stage, and charging control is performed by the simple non-isolated buck converter. Primary switches M₁–M₄ are high-frequency inverter-operated at a fixed frequency and a 50% duty ratio. All controls of the output voltage and line current regulations of the PFC stage are performed only by secondary switches M₅ and M₆. A detailed operational analysis is provided as follows.

Fig. 1. Schematic of a charger composed of the proposed isolated PFC converter with harmonic modulation and a buck converter.

A. Mode Analysis of the Proposed PFC Converter

Fig. 2 shows the key waveforms of the proposed PFC converter, and Fig. 3 presents its operational mode diagrams. Prior to the analysis, the following assumptions are made.

Fig. 2. Key waveforms of the proposed PFC converter.

Fig. 3. Mode diagrams of the proposed PFC converter.

- Link voltage refers to the primary side v_L/n_T being always higher than the rectified input voltage v_in, where n_T is the transformer turns ratio.

- Transformer secondary-side current i_s is zero before mode 1.

- DC-blocking capacitor C_p is sufficiently large to be ignored.

Mode 1 (t₀ ≤ t < t₁): When M₁, M₂, M₅, and M₆ are turned on at t₀ simultaneously, primary current i_p flows through M₁, M₂, inductor L_p, and the transformer primary side. Secondary current i_s flows through M₅, M₆-body diode, and the transformer secondary side. Given that the transformer secondary side is shorted by M₅ and M₆, i_s is increased from zero with the slope of V_in/(n_TL_p), and magnetizing current i_Lm is kept constant with the initial condition of i_Lm(t₀). i_p is equal to the sum of i_Lm, and the secondary current refers to the primary n_Ti_s. They can be expressed as

           (1)

                    (2)

      (3)

Mode 2 (t_{1 ≤} t < t₂): When M₅ and M₆ are turned off, mode 2 begins. The current path in the primary side during mode 2 is maintained as that of mode 1, but the current path in the secondary side forms through D₅ and M₆-body diode. Accordingly, the voltage applied across the transformer primary side v_p becomes V_L/n_T, and i_s decreases with the slope of (v_in-V_L/n_T)/(n_TL_p). During mode 2, i_s, i_Lm, and i_p can be expressed as follows:

                  (4)

   (5)

   (6)

where d_p is the duty ratio of M₅ and M₆. Mode 2 continues until i_s is reduced to zero, and its time duration can be derived from Eq. (4) as follows:

       (7)

where d_p2 is the time ratio of mode 2.

Mode 3 (t₂ ≤ t < t₃): During this mode, only the magnetizing current circulates through M₁ and M₃, as shown in the mode diagram of mode 3 in Fig. 2. v_p is changed to input voltage v_in. Hence, i_s, i_Lm, and i_p can be expressed as

                              (8)

     (9)

The initial condition of i_Lm in this mode can be derived from Eqs. (5) and (7) as follows:

        (10)

Modes 4 and 5 (t_{3 ≤} t < t₅): When the primary switches of M₁ and M₂ are turned off, the magnetizing current is used for the potential exchange of all drain-to-source voltages in primary switches. After completing the potential change, the magnetizing current starts to flow through the body diodes of M₃ and M₄ so that the ZVS condition can be achieved. Assuming that the total duration of modes 4 and 5 (i.e., the dead time between upper and lower switches) is short enough that the magnetizing current is maintained at a constant value, i_Lm during these two modes can be written as

          (11)

Under this assumption, the initial condition of i_Lm(t₀) can be derived using Eqs. (9), (10), and (11) as follows:

     (12)

B. Harmonic Controller in the Proposed PFC Converter

Given that the magnetizing current is the circulating current whose value averaged over the switching cycle is zero, it does not affect the switching average value of input current i_in. Thus, analysis of the input current waveform can be performed by removing the magnetizing current. Fig. 4 shows the input current excluding the magnetizing current in the proposed converter. The peak and switching average values of input currents i_in,pk and i_in,av can be derived as

                  (13)

    (14)

Fig. 4. Input current, excluding the magnetizing current, during one switching cycle.

Fig. 5(a) presents the inductor current envelope and the line current waveform of conventional DCM operation whose d_p is constant. The envelope of the input current follows the input voltage waveform, but the switching average value of the input current that is equal to the rectified line current is distorted. This characteristic is similar to that of a conventional DCM PFC converter. To obtain a pure sinusoidal line current waveform, the power factor should be unity, that is, the output power is equal to the apparent input power. This condition can be expressed as

          (15)

Fig. 5. Inductor current envelope and line current waveform of conventional DCM operation (a) and those adopting a harmonic controller (b).

Considering that I_ac,rmsV_ac,rms is equal to I_in,pkV_in,pk/2, I_in,pk can be derived as

           (16)

Thus, the line current for the unity power factor is derived as follows:

     (17)

where is the angular frequency of line voltage. If the switching average value of input current i_in,av in Eq. (14) is equal to the absolute value of i_ac in Eq. (17), then the line current can have a unity power factor, which can be accomplished by modulating duty ratio d_p. Given that v_in can be written as , the duty ratio for the unity power factor can be derived from Eqs. (14) and (17) as follows:

      (18)

The modulated duty ratio is composed of a constant value of D_p generated by the voltage controller and modulation factor M_f for improving the power factor. Fig. 5(b) shows a case that adopts this technique. As shown in the figure, sinusoidal line current can be obtained by modulating d_p.

III. LOSS ANALYSIS AND DESIGN

A. Effective Parasitic Capacitances of Switching Devices

Effective capacitances of semiconductor devices, such as drain-source capacitance of MOSFET and junction capacitance of diodes, should be derived as a function of the voltage applied across the semiconductor devices to analyze the performance of the proposed converter. The drain-source capacitance of MOSFET varies in accordance with blocking voltage v_ds and is approximately expressed as

                         (19)

where C_T is the drain-source capacitance at test voltage V_T. The energy stored in the drain-source capacitance while the drain-source voltage rises from 0 to V_ds is

       (20)

From Eq. (20), the effective capacitances of MOSFET when the drain-source voltage is increased from 0 to V_ds can be derived as

   (21)

Simply, the drain-source capacitance calculated at the center of varying voltages can be used for effective capacitance, which is

      (22)

where V₁ and V₂ denote the start and end voltages, respectively. By using Eq. (22), the effective drain-source capacitances of MOSFET when the drain-source voltage is increased from 0 to V_ds can be written as follows:

         (23)

C_dse in Eq. (23) is only 6% larger than that in Eq. (21). Hence, Eq. (23) can be used to determine the effective capacitances and is more useful when V₁ is not zero. The effective junction capacitance of diodes can also be determined with Eq. (23).

B. L_p for DCM Operation

To guarantee the DCM operation of the transformer primary current, the following condition should be satisfied:

   (24)

By using this inequality and the modulated duty ratio given in Eq. (18), L_p that meets the DCM condition can be written as

      (25)

The worst case occurs at the maximum output power P_o,max and peak line voltage V_in,pk. Thus, the maximum inductor value to meet the DCM condition over the entire line and load voltages can be derived as

     (26)

C. L_m Selection for Soft Switching

Fig. 6 presents the equivalent circuit during dead times between gate signals of the primary side switches under the assumption that the input and output capacitors of C_in and C_L are sufficiently large to be shorted during dead times. Given that the magnetizing current during dead times between gate signals of upper and lower switches T_dead is used for ZVS currents of primary and secondary side switches, the ZVS condition can be written as

       (27)

Fig. 6. Equivalent circuit during dead times between gate signals of the primary side switches.

Hence, L_m for ZVS can be calculated as

         (28)

Considering that the drain-source voltages of all primary switches experience the voltage change of zero to v_in or v_in to zero, the effective capacitance of primary switches C_dse1 can be established as

      (29)

The change in the drain-source voltage of the primary switches appears on the transformer secondary side and can be expressed with a variable voltage source that varies between +n_Tv_in and –n_Tv_in, as shown in Fig. 7. The voltage applied across secondary devices during dead times can be derived as

   (30)

   (31)

Fig. 7. Equivalent circuit in the secondary side when the drain- source voltages of all primary switches change from zero to v_in or from v_in to zero.

In cases where complete ZVS is accomplished, transformer secondary voltage v_s is changed between +n_Tv_in and –n_Tv_in so that the center voltage experienced by secondary devices is V_L/2. Therefore, the effective capacitances of secondary MOSFETs C_dse2 and diodes C_je2 can be written as follows:

      (32)

     (33)

where C_Tj is the junction capacitance at test voltage V_Tj. Investigation of Eqs. (28), (29), (32), and (33) indicates that L_m,max is dependent on the line voltage, and a very small magnetizing inductance is required to meet ZVS under the entire line voltage magnitude. Thus, an appropriate ZVS start voltage V_is defined by the minimum input voltage to meet the ZVS of primary switches should be selected by considering the effect of the switching loss caused by the output capacitances of switching devices.

D. Loss Analysis

Assuming that the switching frequency is sufficiently high that all parameters during the switching cycle are regarded as time-invariant ones, loss analysis can be performed at each switching cycle.

1) Losses of Primary Side Switches

The switching losses in the primary switches are caused by the device turn-off time t_f and the drain-source capacitance of MOSFET because the transformer primary current has a DCM operation. The switching loss due to the drain-source capacitance of MOSFET P_Cds1[n] and that due to turn-off time P_off1[n] generated by a single switch in the n_th switching cycle can be written as follows:

       (34)

       (35)

where 

N is the total switching number of the PFC converter during half of the line cycle T_L/2 and is calculated by int(T_L/T_s/2). Assuming that L_m is sufficiently large that the magnetizing current is ignored, the RMS switch current in the n_th switching cycle can be derived as follows:

      (36)

where 

With this expression, the conduction loss generated by a single switch in the n_th switching cycle can be written as follows:

           (37)

Therefore, the total loss of the primary switches over the entire line cycle can be derived as

      (38)

2) Losses of Secondary Side Switches

Fig. 2 depicts the voltages applied across the secondary switches and diodes in key waveforms. The voltages experience many potential changes during the single switching period, but potential changes at t₀ and t₁ contribute to the switching losses because others are not significant. From Eq. (19), the effective capacitances of secondary switches at t₀ C_dse20 and at t₁ C_dse21 can be written as

    (39)

   (40)

The switching loss of a single secondary switch caused by the drain-source capacitance of MOSFET P_Cds2[n] in the n_th switching cycle can be written as follows:

        (41)

The switching loss of a single secondary switch caused by turn-off time P_off2[n] is

   (42)

The conduction loss of MOSFET is produced by the on-resistance and on-drop voltage of the body diode. According to Fig. 2, the conduction loss of a single secondary switch in the n_th switching cycle can be derived as follows:

   (43)

where 

Thus, the total loss of secondary switches over the entire line cycle can be derived as

          (44)

3) Losses of Secondary Side Diodes

Diode loss is composed of the switching loss due to junction capacitance and the conduction loss due to on-drop voltage. Similar to the case of MOSFET, the dominant switching loss occurs at t₀ and t₁. The effective capacitances of diodes at t₀ C_je20 and at t₁ C_je21 can be written as

    (45)

                      (46)

The switching loss of a single diode caused by junction capacitance P_Cj2[n] in the n_th switching cycle can be written as follows:

      (47)

Given that the switching average current of diodes is

        (48)

the conduction loss generated by a single diode in the n_th switching cycle can be written as follows:

              (49)

Therefore, the total loss of diodes over the entire line cycle can be derived as

          (50)

4) Losses of Transformer and Inductor

The core loss occurring in the n_th switching cycle can be written as

      (51)

where B_T[n] is the flux swing in kilo-Gauss and V_eT denotes the core volume in cm³ [29]. In addition, a, c, and d represent coefficients based on the core materials provided by the core manufacturers. The flux swing of the transformer core B_T[n] is proportional to d_p2[n]T_s and can be written as follows:

            (52)

where B_T,design denotes the flux swing designed at specific time T_design. The primary and secondary RMS currents of the transformer are written as

                     (53)

                   (54)

so the copper loss in the n_th switching cycle can be derived with the primary and secondary winding resistances of R_p and R_s as follows:

         (55)

Similarly, the core and copper losses of the primary inductor in the n_th switching cycle can be derived with the core volume V_ei in cm³, the flux swing B_i[n] in kilo-Gauss, and the winding resistance of inductor R_L. They are expressed as

        (56)

                (57)

where 

and f_e is the effective operating frequency of the primary inductor, which is equal to 2f_s. B_i,design denotes the flux swing designed at specific inductor current I_design. Therefore, the total loss of the transformer and the primary inductor over the entire line cycle is

          (58)

5) Conduction Loss of Bridge Diode

The conduction loss of the bridge diode with the on-drop voltage of V_on,BR in the n_th switching cycle can be expressed as

       (59)

and the switching average value of input current is expressed as

      (60)

Thus, the conduction loss of the bridge diode can be determined as follows:

      (61)

6) Peak Current of the Primary Inductor

By referring to Fig. 4, the peak current of the primary inductor in the proposed converter with the harmonic modulator can be written as

    (62)

where L_p is the value selected by Eq. (26). If the converter is under the conventional DCM operation without the harmonic modulator, then the operational duty ratio is a constant value over the entire line cycle, which can be derived as follows:

         (63)

By using the DCM condition given by Eqs. (24) and (63), the primary inductor for the conventional DCM operation L_pc can be derived as

       (64)

where R_o is the effective load resistor of the PFC converter. Thus, the peak current of the primary inductor in the conventional case i_pc,pk can be obtained as follows:

    (65)

The next chapter shows that the harmonic modulator contributes to the reduction of the current stress of switching devices because a high value can be used for the primary inductor and a low operational duty ratio can be obtained at the peak line voltage where the maximum current stress occurs.

IV. DESIGN AND EXPERIMENTAL RESULTS

A prototype PFC converter is designed with the following specifications.

 Grid characteristics: 3.3 kW/15 A/60 Hz

 Maximum output power: 3.3 kW

 Input voltage: 220 V_rms±15%

 Output voltage: 500 V

Fig. 8 presents the experimental prototype for validation excluding the output electrolytic capacitor. Table 1 shows the key component list of the prototype PFC converter together with the buck converter for test use. In this design, the ZVS start voltage V_is is set to 60 V, and L_m is calculated as 492 μH from Eqs. (28), (29), (32), and (33) and the selected switching devices in Table 1. For the implementation, 500 μH is used.

Fig. 8. Experimental prototype for performance validation.

TABLE I KEY COMPONENT LIST OF THE PROTOTYPE CONVERTER

Component	Value
M1~M7	IPW65R041CFD×1
D1~D3	FFH50US60S×1
CL	1020μF EL capacitor//50uF film capacitor
Cp	8μF
fs	50kHz
Lp	14.3μH (Core: PQ40/40)
Lb	900μH (Core: CH467125×2)
Transformer	Lm =500μH/Llkg=5.7μH/nT =0.89 (Core: 47228EC)
Controller	DSP TMS320F28335

Given that the peak value of the input voltage occurs at the maximum input voltage of 253 V_rms, L_p is calculated as 20.4 μH. Considering the leakage inductance of the transformer, 14.3 μH is used for L_p. Fig. 9(a) presents the measured waveforms of line voltage v_ac, line current i_ac, primary current i_p, and modulation factor M_f in accordance with load and line voltage variations. Fig. 9(b) displays the output voltage of the PFC converter v_L and the DC-blocking capacitor voltage v_cp. Modulation factor M_f is plotted using a digital-to-analog converter in the DSP controller. The figure shows that clean sinusoidal current waveforms can be obtained under wide load ranges by changing operational duty ratios continuously in accordance with M_f. The maximum current of the primary inductor at V_ac=220 V_rms is calculated as 45.6 A by using the designed parameters and Eq. (62). The measured current of Fig. 9 also has a similar value. If the converter is designed to have the conventional DCM operation without the harmonic modulator, then the primary inductor and operational duty ratio are calculated as 9.4 μH and 0.258 from Eqs. (63) and (64), respectively. Accordingly, the maximum current of the primary inductor becomes 169.7 A, which is much larger than that of the proposed converter with the harmonic modulator. Moreover, the prototype design guarantees normal operation under the given line voltage range. Fig. 10 presents the switching waveforms in accordance with load changes. They agree well with the theoretical analysis, except for the parasitic resonance due to pattern inductances in the printed circuit board. Fig. 11 shows the ZVS status in the primary switches in accordance with the input voltage magnitudes. In the figure, turn-on and turn-off instants of M₁ are indicated with arrows. ZVS is well accomplished from the designed ZVS start voltage. Fig. 12 displays the measured waveforms of the buck converter. The cascaded structure of the proposed PFC converter and the buck converter can cope with a wide output voltage range. Fig. 13 presents the measured power factor and efficiency plots in accordance with load variations. A high power factor can be obtained under a wide load range, and the power factor is over 0.983 at the output power of more than 1 kW. In addition, the efficiency is recorded as 95.6% at V_ac=220 V_rms and P_o=3.3 kW, and the maximum efficiency of 96.2% occurs at V_ac=253 V_rms and P_o=3.0 kW. The overall efficiency including the buck converter can be obtained as 94.8% at V_ac=220 V_rms and P_o=3.3 kW. Fig. 14 shows the measured harmonics and total harmonic distortion (THD) of the input current at the rated condition. THD is well regulated below 5%. Fig. 15 depicts the loss distribution of the proposed PFC converter calculated using the loss equations in Section III. The calculated efficiency is 94.5% at V_ac=220 V_rms and P_o=3.3 kW, which is similar to the measured efficiency. The switching device losses are calculated as approximately 139.5 W. The conduction losses of the primary switches and bridge diode and the switching losses of the secondary switches account for 70% of the switching device losses. The loss of the transformer and primary inductor is 49.7 W, which accounts for approximately 26.3% of the total loss of 189.2 W. Table II presents performance comparisons between the proposed PFC converter and recently reported topologies. The table shows that the proposed PFC converter is not inferior to recent ones in terms of structure and efficiency. Table 3 displays the efficiency comparison at the charger level. The overall efficiencies of the single-phase chargers in [31] and [32] were not provided, but they can be expected using the PFC converter efficiency of 97.6%, which is the measured data in reference [19]. Using the data, the overall efficiencies of the chargers in [31] and [32] are expected to be 95.1% and 95.7%, respectively. Investigation of the tables indicates that the proposed PFC converter and the charger using PFC and buck converters are not inferior to recent ones in terms of structure and efficiency.

Fig. 9. Measured waveforms in accordance with load and line voltage variations.

(a)

(b)

Fig. 10. Switching waveforms in accordance with load changes at V_ac=220 V_rms/V_L=500 V.

Fig. 11. ZVS status of primary switches in accordance with input voltage magnitudes.

Fig. 12. Measured waveforms of the buck converter.

Fig. 13. Measured power factor and efficiency plots in accordance with load variations.

Fig. 14. Measured harmonics and total harmonic distortion (THD) of the input current at the rated condition.

Fig. 15. Calculated losses at V_ac=220 V_rms/P_o=3.3 kW.

TABLE II PERFORMANCE COMPARISON TABLE

	CF-FB PWM [21]	CF-FB PWM [22]	CF-FB PWM [23]	CF-FB PWM [24]	VF-FB PFM SRC [26]	Proposed
Po	1kW	1kW	3kW	3kW	1.7kW	3.3kW
Vac (Vac,max)	220V (240V)	220V ( - )	220V ( - )	208V ( - )	220V (242V)	220V (253V)
Vo	380V	384V	400V	400V	62-82V	500V
fs	37.5kHz	87kHz	50kHz	10kHz	Max. 125kHz	50kHz
Switching device structure (Except for bridge diode)	4 switch (1200V MOSFET) 5 diode (FRD)	6 switch (500V MOSFET) 4 diode (FRD)	8 switch (600V MOSFET) 4 diode (FRD)	5 switch (650V IGBT) 9 diode (FRD)	6 switch (600V IGBT) 8 diode (FRD)	6 switch (650V MOSFET) 2 diode (FRD)
Transformer (Structure)	43:40 ( - )	1:1 ( - )	2:1 ( - )	58:66 (Two EE85)	1:1 (Two PQ4040)	1:1.1 (47228EC)
Inductor	1.3mH	500μH	350μH×2	650μH	5.5μH×2	17.5μH
Full load efficiency	89.3% @ 220V/1kW	93.6% @ 220V/1kW	Not provided	92.7% @ 208V/3kW	92.1% @ 220V/1.7kW	95.6% @ 220V/3.3kW
Power Factor @ 220V	> 0.985@ over 500W	> 0.995@ over 400W	> 0.99	> 0.984 @ over 874W	0.992 @ .7kW	> 0.990 @ over 1kW
Control method	Current control + Voltage control	Current control + Voltage control	Current control + Voltage control	Current control + Voltage control	Voltage control + Valley-fill control	Voltage control + Harmonic control

TABLE III EFFICIENCY COMPARISON BETWEEN THE PROPOSED CHARGER AND PREVIOUS WORK

Ref #	Topology	Power conversion type	Po	Battery charging voltage range	Efficiency @ Battery Voltage
					DC/DC stage	Charger
[30]	Hybrid (LLC+FB)	DC/DC	3.3kW	250V~450V	97.4%@450V	-
[31]	3-level LLC	DC/DC	6.6kW	225V~ 378V	98.1%@368V	-
[32]	LLC	DC/DC for 3ϕ use(Vin=750V)	20kW	300V~550V	98.2%@550V	-
[18]	Resonant PWM	DC/DC	6.6kW	250V~415V	97.4%@360V	95.1%@360V
[28]	DCM PFC+LLC+Buck	AC/DC	6.6kW	250V~450V	97.2%@400V	94.8%@400V
[33]	SEPIC+LLC	AC/DC	1kW	100V~420V	97.1%@420V	93.5%@420V
Proposed	Isolated PFC+Buck	AC/DC	3.3kW	50V~450V	99.1%@450V	94.8%@450V

V. CONCLUSIONS

Another candidate for an isolated PFC converter that can be used for EV chargers is proposed based on the ADAB structure. This candidate is unaffected by the parasitic inductance of the transformer due to the voltage-fed structure. The operation is based on DCM, and the harmonic modulation method is applied to overcome the low power factor featured in general DCM operations. All operations, including harmonic regulation and output control, are performed only by secondary switches with a simple control algorithm, which provides another advantage in terms of controller and circuit design. The design equations are established from the operational analysis, and several loss equations are derived for the quantitative analysis of efficiency. Analysis of the operating characteristics of a 3.3 kW prototype shows that a power factor of over 0.983 is recorded at over 1 kW, and efficiency is recorded as approximately 95.6% at V_ac=220 V_rms and P_o=3.3 kW. Therefore, the proposed circuit can be used in general-purpose battery chargers by configuring it with a simple non-isolated converter.

ACKNOWLEDGMENT

This work was supported by grants from Korea Institute of Energy Technology Evaluation and Planning (No. 201620 20107590) and Korea Evaluation Institute of Industrial Technology (No. 10076430) funded by the government of Korea (MOTIE).

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Seung-Won Choi was born in Seoul, Republic of Korea, in 1975. He received his B.S. and M.S. degrees in electric engineering from Kyung Hee University, Suwon, in 2000. From 2000 to 2005, he worked as a researcher in the Train Computer Management System Development Team, Hunter Technology Inc. From 2006 to 2007, he served as a research engineer in the Memory Tester Development Team, TSE-21 Inc. He worked as a senior research engineer in the Motion Control Team for Tester, Emotiontek Inc. He also worked as a deputy general manager in the Advanced Research Team for Automotive, Woory Cooperation Inc. He is currently working for his Ph.D. degree at Myongji University. His current research interests are in the areas of power electronics application, which include DC/DC bi-directional converters, AC/DC PFC converters, and battery chargers.

Yoon-Jae Kim was born in Busan, Republic of Korea, in 1985. He received his B.S. degree in electrical engineering from Gwangwoon University, Seoul, in 2012. From 2012 to 2015, he worked as a researcher in Motor Driver Development Group, Justek Inc., where he was involved in circuit and product development. He is currently working for his M.S. degree at Myongji University. His current research interests are in the areas of power electronics application, which include DC/DC bi-directional converters, AC/DC PFC converters, and battery chargers.

Il-Oun Lee received his B.S degree in electrical and electronic engineering from Kyungpook National University, Taegu, Korea, in 2000; his M.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2002; and his Ph.D. degree from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2013. From 2003 to 2008, he served as an R&D engineer in the Plasma Display Panel Development Group, Samsung SDI, Korea. From 2008 to 2013, he was a senior engineer in the Power Advanced Development Group, Samsung Electro-Mechanics Co. Ltd., Korea. From 2013 to 2015, he worked as a senior researcher in the Energy Saving Lab., Korea Institute of Energy Research (KIER), Daejeon, Korea. From 2015 to 2017, he worked as an associate professor in the School of Electrical and Electronic Engineering, Keimyung University, Daegu, Korea. In 2017, he joined the Department of Electrical Engineering, Myongji University in Yongin, Korea, as an associate professor. His current research interests include DC/DC converters, PFC AC/DC converters, LED drivers, battery chargers for EVs, digital display power systems, and digital control approaches for DC/DC converters.

Jun-Young Lee received his B.S. degree in electrical engineering from Korea University, Seoul, in 1993 and his M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Taejon, Korea, in 1996 and 2001, respectively. From 2001 to 2005, he worked as a manager in the Plasma Display Panel Development Group, Samsung SDI, where he was involved in circuit and product development. From 2005 to 2008, he worked as a faculty member in the School of Electronics and Computer Engineering, Dankook University. In 2008, he joined the School of Electrical Engineering, Myongji University, as a professor. His research interests are in the areas of power electronics, which include converter topology design, soft switching techniques, plasma power, soft switching inverters, and battery charging systems.