https://doi.org/10.6113/JPE.2018.18.2.418

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Development of a Switched Diode Asymmetric Multilevel Inverter Topology

D. Karthikeyan^*, Vijayakumar Krishnasamy^†, and Mohd. Ali Jagabar Sathik^*

^†,*Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology, Kattankulathur, India

Abstract

This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

Key words: Asymmetric cascaded multilevel inverter, Nearest level modulation, Reduced switches, Total harmonic distortion

Manuscript received Jan. 30, 2017; accepted Oct. 18, 2017

Recommended for publication by Associate Editor Yun Zhang.

^†Corresponding Author: kvijay_srm@rediffmail.com Tel: +20-1282404905, Arab Academy Sci., Tech. Marit. Transp.

*Dept. of Electrical Electron. Eng., SRM Inst. Sci. Tech., India

Ⅰ. INTRODUCTION

In recent decades, multilevel inverters have come to play a major role and have received a lot of attention from industries in the field of power electronics, due to their modularity and high power capability. There are a number of conventional multilevel inverters. (i) The Cascaded H-Bridge (CHB) [1] multilevel inverter topology patent was recorded in 1970 by Baker. The CHB topology has a few advantages such as modularity, soft switching and that fact that it does not require any additional clamping diodes or capacitors. (ii) In 1975, Nabae introduced a Neutral Point Clamp (NPC) multilevel inverter [2]. The NPC has a high efficiency and reactive power control. It is more suitable for the bidirectional power flow applications in HVDC links. (iii) The Flying Capacitor (FC) [3] was introduced to overcome the challenges of balancing the voltage across the series connection of dc-link capacitors. It provides better voltage ride through capability and it can control both the real and reactive power.

The unique drawbacks of conventional multilevel inverters are an increase in the number of switches for increasing the number of levels, which in turn increases the complexity of the installation, the complexity of the switching pattern, the number of gate driver circuits and the size of the inverter layout [4]. Numerous new multilevel inverter topologies have been introduced by researchers to minimize the switch count, gate driver circuits, dc sources and the voltage rating of the switches. In [5], a new cascaded topology was proposed to increase the number of output voltage levels, and various algorithms have been introduced to determine the magnitude of DC sources. However, as the number of levels increases, it is necessary to have different voltage rating for the switches. The ladder structure multilevel inverter topology is presented in [6] with a reduced number of IGBTs and DC sources. A modular structured single dc source multilevel inverter without a transformer and with a low switching frequency is discussed in [7]. A basic module with a capacitor unit is proposed in [8]. This topology has good modularity and is applicable for high voltage applications with a minimized switch count. In [9], a novel transformer based topology was presented for high voltage applications. This topology is configured in an asymmetric method to produce the maximum output voltage levels. However, this topology requires a different transformer turns ratio which makes it difficult to construct. A seven level inverter with a reduced switch count is presented in [10]. A single dc source is used in this topology with three dc-link capacitors and a voltage balancing algorithm for the dc-link capacitor.

In these studies, many new multilevel inverter topologies are presented with the following objectives: a reduced number of switches, a reduced number of sources, an increased output voltage level, etc. In this paper a new structure for an asymmetic multilevel inverter topology is proposed with a reduced number of IGBTs as well as reduced dc sources and low blocking voltages across the switches. This topology is also capable of cascading to generate the maximum number of voltage levels and it is suitable for high voltage and medium power applications. A comparison of the proposed topology with recent multilevel inverters [11]-[20] is also presented.

Ⅱ. PROPOSED FUNDAMENTAL 11-LEVEL INVERTER

A new 11-level multilevel inverter topology with two different configurations: with and without a switched diode is presented. A diagram of the proposed MLI with a switched diode is shown in Fig. 1. This fundamental module is divided into three parts namely the packed H-bridge, the right arm and the left arm. A single dc source is connected in the right arm while the left arm side consists of two dc sources, four dc-link capacitors (C₁-C₂) and (C₃-C₄), switch (S₁) and diode (D₁) as shown in Fig. 1. The packed H-bridge inverter consists of the switches (S₂-S₅), the upper switch (S_U) and the lower switch (S_L). The magnitude of the right arm dc source voltage is V_dc and the left arm dc source’s magnitudes are 2V_dc. The switching sequence used to generate an 11-level voltage is given in Table I. For safe operation and to avoid short circuits, the switch pairs (S₂,S₃), (S₄,S₅) and (S_U, S_L) should not be turned on simultaneously.

Fig. 1. Basic unit of the proposed multilevel inverter.

Various modes of operation for the fundamental 11-level inverter are illustrated in Fig. 2. The switches S₃, S₄ and S_L are turned ON to produce the first output voltage level +V_dc across the load. For level 2, the voltages of the capacitors C₁ and C₄ are added together with a combination of the switches S₂, S₅, D₁ and S_L to supply +2V_dc across the load.

Fig. 2. Various modes of operation for the proposed 11-level inverter.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

(j)

(k)

Level 3 (+3V_dc): Switches S₂, S₄, V_dc, S_L, C₄, D₁ and C₁.

Level 4 (+4V_dc): Switches S₂, S₅, S_L, S₁ and C₁- C₄

Level 5 (+5V_dc): Switches S_1, S₂, S₄, S_L, V_dc and C₁- C₄.

In order to generate the negative cycle output levels of the switches S_U, S₃, S₅ and S₄ are turned on. Similarly, all of the levels are generated by proper switching of the corresponding switches as given in the Table I. In levels 2 and 3, a diode plays a major role in providing the current path. However, the diode is a unidirectional device which allows a current of either positive or negative polarity.

TABLE I SWITCHING SEQUENCE FOR THE PROPOSED 11-LEVEL INVERTER

Output Voltage(VOut)		S1	S2	S3	S4	S5	D1	SU	SL
Positive Level	1Vdc	0	0	1	1	0	0	0	1
	2Vdc	0	1	0	0	1	D1	0	1
	3Vdc	0	1	0	1	0	D1	0	1
	4Vdc	1	1	0	0	1	0	0	1
	5Vdc	1	1	0	1	0	0	0	1
Zero Level	0	0 0	1 0	0 1	1 0	0 1	0 0	1 0	0 1
Negative Level	-1Vdc	0	1	0	0	1	0	1	0
	-2Vdc	0	0	1	1	0	D1	1	0
	-3Vdc	0	0	1	0	1	D1	1	0
	-4Vdc	1	0	1	1	0	0	1	0
	-5Vdc	1	0	1	0	1	0	1	0
* Dead time considered is 4 µs

This leads to the origin of a spike on the output voltage which can be overcome by two different approaches: (i) connecting an LC filter across the load to minimize the voltage spike, and (ii) replacing the diode with a switch containing an anti-parallel diode.

The use of an LC filter design in the first approach is more complicated and the power losses are higher in the passive components when compared to the active devices. Therefore, in this paper the second approach of replacing the diode with a switch is used. A circuit diagram of the proposed 11-level MLI without a switched diode is shown in Fig. 3. In this circuit, the diode (D₁) is replaced by the switch (S₆) to provide a bidirectional current path.

Fig. 3. Proposed multilevel inverter without a switched diode.

To increase the number of levels with a reduced number of switches, a cascaded structure of the basic module can be used as shown in Fig. 4. The required number of switches, gate driver circuits, total standing voltage, number of DC-Link capacitors and number of dc sources are listed in Table II.

Fig. 4. Proposed cascaded multilevel inverter topology.

TABLE II COMPARISON OF THE PROPOSED TOPOLOGY IN TERMS OF THE FUNDAMENTAL MODULE AND THE NUMBER OF LEVELS

Description	Based on Cascaded Topology	Based on desired levels
Number of Level	10n+1	NLevel
Number of Switches	8n	4*(NLevel+1)/6
Number of Diodes	8n	4*(NLevel+1)/6
Number of Gate Driver Circuits	8n	4*(NLevel+1)/6
Number of DC-Link Capacitor	5n	5*(NLevel+1)/2
Number of DC Sources	3n	NLevel+1
Total Standing Voltage(TSV)	24n	2*(NLevel+1)
Where “n” denotes number of module and “NLevel ”denotes Number of level.

To avoid this condition, the voltage balancing circuit presented in [21] is recommended, and is shown in Fig. 5. The voltage balancing circuit is a combination of capacitors and diodes. In Fig. 5(a), the dc source voltage is boosted by a boost converter and this voltage is balanced across the dc-link capacitors. This type of converter is more suitable for photovoltaic applications. Fig. 5(b) shows the absence of boost converters. This is more suitable for regulated dc sources.

Fig. 5. Voltage balancing circuits: (a) for an unregulated dc source (b) for a regulated dc source.

(a)

(b)

Ⅲ. DC- LINK CAPACITOR VOLTAGE BALANCING AND RIPPLE VOLTAGE CALCULATION

Series connected dc-link capacitors do not provide balanced output voltages on the switches, which leads to the production of over voltages on the switches.

The voltage balancing of each capacitor is determined as follows:

The boost converter output voltage is determined by equation (1) with respect to the duty cycle (D) of the converter.

       (1)

The current across the load with respect to the duty cycle is expressed in equation (2):

    (2)

Finally, the “N” number of capacitors is connected in series and the voltage across each of the capacitors is expressed in terms of the duty cycle and the number of capacitor in (3):

     (3)

          (4)

The general expression for the “N” number of dc-link capacitor is expressed in equation (5):

    (5)

Where V_C is the lower voltage of the capacitor, V_d is the assumption of a voltage drop across the switch and diode, N- is the number of dc/dc levels and R_esL is the inductor ESR value.

The expression for the dc-link capacitor voltage for the proposed inverter is presented in equation (6):

          (6)

The capacitance values are designed with reduced voltage ripples and improved efficiency of the inverter [22].

The following factors are considered to measure the power calculation of the proposed multilevel inverter: (i) switching losses (ii) conduction losses and (iii) capacitor losses.

The switching losses mainly depend on the switching frequency and blocking voltage of the switches, and the conduction losses depend on the voltage drop across the switches and the rms current flowing through that particular switch. The capacitor losses depend on the voltage ripples and the ESR (Equivalent Series Resistance) values of the capacitors. The proposed inverter supplies the load power from both the dc source and the dc-link capacitors. The inverter output voltages are kept constant by balancing the voltage magnitude of the dc-link capacitors. However, the load draws a continuous current i₀ and this influences the voltage ripples across the capacitors. The capacitor discharging period C_1,4 starts when the switch S₆ is turned ON and ends when S₆ is turned OFF.

     (7)

Where t₂ is the capacitor C_1-4 start and end time, and 0.01-t₂, (t₉) is the capacitor C_2-3 start and end time of the discharging duration for a half period of the fundamental frequency as shown in Fig. 6. For the fundamental switching method, the time interval is represented as the angle of conduction of the switch S₁, S₆ or S₁ diode pair. In the first configuration (with a switched diode) diode is always in conduction and the second part of equation (7) does not exist, since the proposed modulation technique is a half period method and “t”, the simplified equation for the voltage ripple (ΔV_i) is expressed in (8).

           (8)

Fig. 6. Pulse generation waveform for an 11-level inverter with a DC-link capacitor discharging period.

where θ₁- θ₄ are the switching angles. The amount of charge

 is calculated by the approximate discharge period and is given in equation (9):

   (9)

where “R” is the load resistance (unity power factor) and “a” is the number of capacitors in a basic unit. Finally, the voltage ripple is derived as:

        (10)

The capacitance is inversely proportional to the voltage ripples and directly proportional to the load current. In practical implementation, the capacitor should be able to supply the maximum current with the minimum voltage ripples.

Ⅳ. COMPARISON WITH OTHER RECENT TOPOLOGIES

Recently proposed topologies are designed to minimize the number of switches, the number of dc sources and the voltage stress across the switches. A few of these topologies are considered for comparison with the proposed topology. In Fig. 7(a) multiple dc sources are used and all of the dc sources are connected with a series/parallel combination of switches to produce multiple dc voltages with equal magnitudes. The full bridge inverter is used in the output side to change the polarity of the output voltage.

The maximum blocking voltage for each of the switches connected in cascaded is V_dc. However, the full bridge inverter switches should withstand for the sum of the voltages connected in series (nV_dc) as discussed in [11]. In [12], a new cascaded design for a multilevel inverter is presented as shown in Fig. 7(b), where the basic unit is constructed with six switches and two dc link capacitors with a single dc source. The basic unit is connected in cascaded to produce the maximum output voltage level with a reduced blocking voltage. However, the switches count is still high. Cross connected switches in a packed h-bridge is presented in Fig. 7(c). In this topology, the maximum output voltage level is generated with reduced dc sources, even though the number of switches and blocking voltages are high as detailed in [13].

Fig. 7. Different multilevel inverter topologies with a reduced switch count.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

In Fig. 7(d) and Fig. 7(e) both of the topologies are different in structure. However, in terms of their output voltage level, the number of switches is equal with same blocking voltage [14], [15]. In addition, various multilevel inverter topologies and control techniques are discussed in [16], [17]. A hybrid topology is presented in [18] and its circuit diagram is shown in Fig. 7(f). The hybrid connection of a full bridge inverter with a basic unit is proposed for switch reduction and blocking voltage minimization. However, this topology uses a unidirectional switch which affects the output voltage waveform when the load is highly inductive.

The topology shown in Fig. 7(g) is proposed for a reduced number of dc sources. Each basic unit is connected in series to generate the maximum number of voltage levels for the minimum number of dc sources as presented in [19].

In [20], an E-type topology for the asymmetric configuration is proposed with a reduced switch count. In this topology, both unidirectional and bidirectional switches are used as shown in Fig. 7(h). Many topologies require a larger number of switches with reduced blocking voltages. However, the number of dc sources used is high. Conventional and recent topologies are compared with the proposed topology in table III for various parameters such as the number of switches, number of DC link capacitors, Total Standing Voltage (TSV) and number of dc sources. The proposed topology requires a lower number of switches in terms of the DC link capacitors and a reduced number of DC sources.

TABLE III COMPARISONS OF DIFFERENT MULTILEVEL INVERTER TOPOLOGIES FOR VARIOUS PARAMETERS

	NPC	FC	CHB	[11]	[12]	[14]	[15]	[19]	[20]	Proposed
No. of Switches	2(NL -1)	2(NL -1)	2(NL -1)	NL+3	NL +1	NL +1	NL+1	NL -1	5(NL-1)/6	4(NL+1)/6
No. of DC Link Capacitors	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/3	(NL-1)/2
No. of Switches in terms of DC links	4	2+2/( NL-2)	4	1/3+4/3( NL-1)	2+4/( NL-1)	2+4/( NL-1)	2+4 /( NL-1)	3	5/2	8/5
TSV(Vdc)	2(NL -1)	2(NL -1)	2(NL -1)	3(NL -1)	2(NL -1)	2(NL -1)	2(NL -1)	3(NL -1)	10(NL -1)/6	2(NL+1)
Number of Source	1	1	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/2	(NL-1)/3	(NL+1)/4

A. Number of Level Vs Number of Switches:

One of the objectives of the proposed inverter is to reduce the number of power switches, which is plotted in Fig. 8(a). Various metrics are involved to evaluate the reliability of the multilevel inverter. In this, the switch count is one of the major parameters. Existing multilevel inverters CHB, NPC, FC, [11], [12], [14], [15] and [19], [20] use a larger number of switches whereas the proposed topology requires a smaller number of switches. If the number of switches is high, the number of gate driver circuits also increases, which in turn reduces the reliability of the inverter.

B. Number of Level Vs Number of Sources:

The required number of dc sources is another important factor in multilevel inverter. This is due to the fact that the multilevel inverter requires an increased number of dc sources with respect to the number of levels. However, the availability and provision of dc sources are more complicated in some applications such as electric vehicles. The proposed topology uses a reduced number of DC sources to produce the maximum number of levels as shown in Fig. 8(b). In Fig. 7(h), the basic cell requires a maximum of four dc sources to generate a 13-level output with ten switches, whereas proposed topology uses three dc sources to produce the maximum of 11-level outputs with eight switches.

Fig. 8. Various comparison results: (a) N_Level Vs N_Swicthes; (b) N_Level Vs N_Sources; and (c) N_Level Vs TSV.

(a)

(b)

(c)

C. Number of Level Vs Total Standing Voltage:

One of the advantages of multilevel inverters is the minimum voltage stress across the switches. Except for the conventional topologies all of the other recent multilevel inverter topologies have a high standing voltage since the number of switches is inversely proportional to the standing voltage on the switches.

The total standing voltage on the switches is calculated as the sum of the individual blocking voltages on the switches. In Fig. 8(c), the total standing voltage of the proposed topology is higher than that of the conventional topology and [20]. However, it is less than that in [11] and [19]. Here, it is worth mentioning that the proposed topology uses minimum number of switches when compared to the conventional topologies.

Ⅴ. SIMULATION AND EXPERIMENTAL RESULTS

The proposed structure is simulated using Matlab/Simulink software. The Nearest Level Modulation (NLM) method is used to generate the switching pulses, which operate with the fundamental switching frequency (50Hz). The NLM method produces low switching losses and is easy for hardware implementation. The NLM method generates more harmonics in output voltage for lower levels and this is suitable for a higher number of levels [23] due to the low harmonics in higher levels.

The harmonic voltage is expressed in terms of a Fourier series equation as follows:

    (11)

     (12)

where h (the odd order of the harmonic) = 3, 5, 7…. and V_o1 is the fundamental voltage. V_oh is the order of the harmonics. V_o,rms- is the rms value of the output voltage. The magnitude of V_o1 and V_{o, rms} can be calculated using the following relations:

           (13)

           (14)

where θ₁, θ₂… θ_NLevel are switching angles, which are calculated using equation (15):

      (15)

The voltage waveforms across the diode and switch for both of the topologies, for the simulation and the hardware setup are shown in Fig. 9. The first configuration (switched diode based) topology produces voltage spikes due to the non-conduction of the opposite current, whereas in the second configuration (without a switched diode) the voltage spikes are eliminated. Fig. 9(a) shows the conduction current in the forward and reverse directions during the simulations without the use of a switched diode as illustrated in blue. A similar waveform for the experimental results of the voltage is shown in Fig. 9(b). In conclusion, the diode based topology is not suitable for all applications except where a unidirectional current is required.

The proposed 11-level inverter output voltage by simulations for both of the configurations are presented in Fig. 10. For the first configuration (switched diode), due to the diode, voltage spikes are present in every half cycle of the output voltage waveform, as shown in Fig. 10(a), with an increased voltage THD of 9.87 % and current THD of 1.33%. For the second configuration (without switched diode), the simulation results are presented in Fig. 10(b) with voltage and current THDs of 7.61% and 1.11%, respectively.

Fig. 9. Voltage waveform across the diode and switch: (a) simulation results; (b) experimental results.

(a)

Times(s) (b)

Fig. 10. Simulation results of: (a) the first configuration output voltage and current waveform with a FFT spectrum; (b) the second configuration output voltage and current waveform with a FFT Spectrum.

(a)

(b)

In the experimental test, the value of the right arm dc source is 30V and the left arm dc sources are each 60V. The R-L load with R=80 Ω and L=100 mH is used for this topology and the values of the dc-link capacitors C₁-C₄ are 100µF. The second method (without a switched diode) circuit diagram is used to balance the dc-link capacitor voltages, and the balanced voltages are illustrated in Fig. 11(a). According to the proposed circuit diagram, the levels are: 0, ±30V, ±60V… ±120V, ±150V. In the experimental test, eight IGBTs (BUP400D) with V_CE = 600V and I_C = 22A and eight gate driver circuits (HCPL316j) are used. The blocking voltages of the switches S_L=S_U=150V, S₆=S₁=60V, S₃=S₂= 120V and S₅=S₄=30V as shown in Fig. 11(b). For both of the configurations the voltage and current waveforms obtained from the experimental setup are given in Fig. 12 and Fig. 14. The FFT spectrum, obtained from the power quality analyzer, for both of the configurations are given in Fig. 13 and Fig. 15, respectively.

Fig. 11. (a) Balanced input voltage by balancing the circuits; and (b) blocking voltage across various switches in an 11-level inverter.

(a)

(b)

Fig. 12. Output voltage and current waveforms of switched-diode configuration.

Fig. 13. Experimental results of a switched-diode with a voltage FFT spectrum and power quality analyzer output.

Fig. 14. Output voltage and current waveforms of the second configuration.

Fig. 15. Experimental results of the second configuration with a voltage FFT spectrum and power quality analyzer output.

For the first configuration the RMS value of the output voltage is 114.04V and the output power is 118.37W, whereas for the second configuration (without a switched diode), the RMS value of output voltage is 102.89V and the output power is 113.84 W. Similarly the voltage and current THDs for the first configuration are 10.54% and 6.53 %, whereas for the second configuration they are 7.712% and 2.876%, respectively. From these results it is evident that replacing a diode by a switch eliminates the spikes in the voltage waveforms [refer to Fig. 12 and Fig. 14]. Hence, the second configuration (without a switched diode) produces a better quality output when compared to the first configuration (with a switched diode).

A summary of the results obtained for the proposed configurations for the simulation and hardware setup are shown in Table IV. The RMS voltage and output power of the first configuration is higher than that of the second configuration. However, its overall efficiency is low. A photograph of the experimental setup is shown in Fig. 16.

Fig. 16. Photograph of the experimental model.

TABLE IV SUMMARY OF BOTH CONFIGURATIONS OF THE PROPOSED TOPOLOGY

Configuration	Results	Vin	R (Ω)	L (mH)	Vrms (V)	Irms (A)	V THD (%)	I THD (%)	Pin (W)	Pout (W)	Efficiency η (%)
First Configuration (With a Switched Diode)	Simulation	150V	80	100	107.56	1.25	9.87	1.33	134.45	124.1	92.30
	Experimental	150V	80	100	114.8	1.14	10.54	6.35	130.87	118.37	90.45
Second Configuration (Without a Switched Diode)	Simulation	150V	80	100	107.22	1.24	7.61	1.11	132.95	125.8	94.65
	Experimental	150V	80	100	102.89	1.17	7.71	2.87	120.38	113.40	94.20

Ⅵ. CONCLUSION

A new multilevel inverter structure with two different configurations is described in this paper. The proposed configurations generates an 11-level output voltage with a reduced number of power electronic components. The proposed topology can be cascaded for high voltage applications with a low voltage stress and low power electronic devices. It is confirmed that the proposed configuration generate a higher number of output voltage levels when compared to some of the other multilevel inverters presented in this paper. The first configuration (with a switched diode) has a spike in the output voltage and has a higher voltage and current THD, whereas the second configuration (without a switched diode) has a better output voltage without a spike and the voltage and current THD is low. Therefore, the second configuration with a cascaded structure is recommended for high voltage applications.

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D. Karthikeyan received his B.E. degree from the Department of Electrical and Electronics Engineering of A.I.H.T College, Chennai, India (affiliated with Anna University, Chennai, India), in 2009; and his M.Tech. degree in Power Electronics and Drives from SRMIST (Formerly SRM University), Kattankulathur, India, in 2013, where he is presently working towards his Ph.D. degree in Multiport Converters. He is presently working as Assistant Professor in the Department of Electrical Engineering SRMIST (Formerly SRM University), Kattankulathur and Chennai, India. His current research interests include power electronic multilevel inverters, AC drives and DC drives. He is a Member of various professional societies such as the IEEE and ISCA.

Vijayakumar Krishnasamy received his B.E. and M.E. degrees from Annamalai University, Annamalai Nagar, India; and his Ph.D. degree from SRMIST (Formerly SRM University), Kattankulathur, India. He is presently working as a Professor and as the Head of the Department of Electrical and Electronics Engineering of SRMIST (Formerly SRM University). His current research interests include power system modeling, power electronics converters for grid connected PV systems, computational intelligence applications in power systems, FACTS devices and power quality. He has been awarded a Best Teacher Award in his department for the academic years 2004 and 2006. He is a Member of various professional societies such as the IEEE, IET, FIE, ISTE and ISCA.

Mohd. Ali Jagabar Sathik was born in Madukkur, India, in 1979. He received his B.E. degree in Electronics from the Madurai Kamarajar University, Madurai, India, in 2002; and his M.E. and Ph.D. degrees from the Faculty of Electrical Engineering, Anna University, Chennai, India, in 2004 and 2016, respectively. He is presently with the Faculty of Electrical Engineering, SRMIST (Formerly SRM University), Chennai, India. He received a Research Excellence Award in 2017 from the Indus Foundation, Hyderabad, India. He has published papers for both national/international conferences and journals proceedings. His current research interests include the control of power electronic converters, multilevel converters, the application of power electronics to renewable energy systems, energy efficiency, harmonics, power quality, and FACTS devices. He is a Member of various professional societies such as the IEEE and ISTE.