https://doi.org/10.6113/JPE.2018.18.2.627

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Zero-Current Phenomena Analysis of the Single IGBT Open Circuit Faults in Two-Level and Three-Level SVGs

Ke Wang^†, Hong-Lu Zhao^*, Yi Tang^*, Xiao Zhang^*, and Chuan-Jin Zhang^*

^†,*School of Electrical and Power Engineering, China University of Mining and Technology, Xuzhou, China

Abstract

The fact that the reliability of IGBTs has become a more and more significant aspect of power converters has resulted in an increase in the research on the open circuit (OC) fault location of IGBTs. When an OC fault occurs, a zero-current phenomena exists and frequently appears, which can be found in a lot of the existing literature. In fact, fault variables have a very high correlation with the zero-current interval. In some cases, zero-current interval actually decides the most significant fault feature. However, very few of the previous studies really explain or prove the zero-current phenomena of the fault current. In this paper, the zero-current phenomena is explained and verified through mathematical derivation, based on two-level and three-level NPC static var generators (SVGs). Mathematical models of single OC fault are deduced and it is concluded that a zero-current interval with a certain length follows the OC faults for both two-level and NPC three-level SVGs. Both inductive and capacitive reactive power situations are considered. The unbalanced load situation is discussed. In addition, simulation and experimental results are presented to verify the correctness of the theoretical analysis.

Key words: Fault diagnosis, IGBT OC fault, NPC 3-Level, SVG, 2-level, Zero-current

Manuscript received May 23, 2017; accepted Nov. 4, 2017

Recommended for publication by Associate Editor Kyo-Beum Lee.

^†Corresponding Author: kewang_china@cumt.edu.cn Tel: +86-13952171593, China Univ. of Mining and Tech.

*School of Electrical and Power Eng., China Univ. of Mining and Tech., China

I. INTRODUCTION

The IGBT, as one of the most successful power switching devices, is widely used in converter applications. IGBTs normally operate at a high switching frequency and have a high stability requirement [1]. Once a semiconductor device fails, the system is damaged, which results in serious losses.

Short-circuit (SC) and open-circuit (OC) faults are the two most common faults for IGBTs. When compared with SC faults [2], which are usually destructive and result in a direct shut down of the system, OC faults are more likely to go undetected, but significantly reduce the system performance. In order to reduce the impact of an OC fault on the system, many studies have been done [3], [4]. They mainly include two aspects: fault location and fault tolerance.

The goal of fault location is to lock OC faulty IGBT with minimal time, minimum cost, and maximum stability. Generally speaking, current-based and voltage-based methods are the two most common OC fault diagnosis strategies.

A number of current-based proposals have been presented in the literature. The current Park’s Vector method was proposed in [5], [6]. However, it requires very complex pattern recognition algorithms, which are not suitable for integration into drive controllers. The average current Park’s Vector method was proposed in [7]. Methods based on an analysis of the current space vector trajectory diameter were discussed in [8], [9]. To overcome the defects of load dependence and sensitivity to transients, a normalized average current method was proposed in [10], and the absolute values of the normalized average currents were considered in [11]. A combined method based on both a derivative of the current Park’s vector phase and the current polarity was proposed in [12]. It possesses excellent immunity to false alarms. Current- based methods are independent of system parameters and no additional sensors are needed. However, the corresponding diagnostic time is generally longer than a supply period.

Voltage-based methods have a faster response than current- based methods [13], [14]. However, they usually need additional detection hardware, which increases the drive costs and complexity. A direct comparison between the measured voltages and the reference values was presented in [15] and a time delay was introduced to prevent false alarms. A FPGA based fault location approach with detection times shorter than 10 µs was introduced in [16]. Alternatively, a low-cost proposal based on indirect voltage measurement using high- speed photocouplers was presented in [17]. However, well- defined time delays dependent on the nature of the power converter are still required.

In addition, some other methods, such as the wave-let fuzzy algorithm [18], wavelet-neural network [19] and rule-based expert systems [20] can also be used for OC fault diagnosis. For expert systems, user input can be a combination of system parameters, such as three phase currents, inverter pole voltage, phase voltage, switch voltages, DC link current and user inputs.

The goal of fault tolerance is to ensure that a system continues to operate and maintain a good performance through software and hardware strategies before an open-circuit fault is repaired. Fault tolerance consists of fault isolation and fault reconfiguration, which is based on hardware redundancy and fault-tolerant control.

Previous studies provide a large number of methods for fault redundancy. These methods can be classified into four categories: switch-level, leg-level, module-level and system- level. For switch-level solutions, inherently redundant switching states methods [21], dc-bus midpoint installation methods [22] and redundant parallel or series switch installation methods [23] are proposed. In leg-level solutions, the main approach is to add redundant legs in parallel or series connection to the main legs [24]. When choosing redundant parallel methods, a compromise between system cost and performance must be considered.

In terms of the OC fault diagnosis and tolerance for converters in the literature, when focusing on the existing designs for two-level or three-level converters, it can be found that a zero current phenomena exists and frequently appears in the OC fault condition. When an OC fault occurs, the fault phase current is greatly distorted, through random increases and decreases. The fault phase current can even drop to zero in some cases and stay there for a period of time. This phenomena can be found in many of the existing studies [17], [25]-[29], regardless of whether they are designed for motor drive applications or grid connected inverters.

The zero current phenomena should be taken seriously. Meanwhile, almost all of the existing papers just focus on how to locate OC faults and very few of them value the importance of the zero current. In fact, many of the fault variables presented in existing papers have a great correlation with the zero-current interval. In some cases, the zero-current interval actually decides the most significant fault feature. For example, for the excellent average current method in [10], the proposed decision function is greatly increase in the zero-current interval. In [28], a good strategy for OC fault detection is proposed based on the average current Park’s vector method. If the zero current phenomena occurs or the current values are close to zero, the average line current vector greatly increases and becomes higher than the threshold. In [29], the diagnostic variables d_n and a_n are also greatly determined, since is close to zero in the zero- current interval. By observing many of the fault current waveforms in the literature, it is worth noting that all of the results of multiplication involved with the fault phase current i are zero when it comes to the zero-current interval, such as:

.

For OC fault diagnosis, especially for current-based OC fault location, the zero-current interval corresponds to the most significant fault feature. This leads to a number of questions. Why does the zero current phenomena occur? When will zero current occur? And how long will the zero current phenomena last? Therefore, learning the rules of the zero current in an OC fault is meaningful and important to the understanding of OC faults and OC fault location methods.

Some studies discussed how the fault current changes after an OC fault such as in two-level converters [27], [30]-[32] and in three-level converters [33]-[40]. However no existing papers have really explained the zero-current phenomena.

The innovations in this paper are as follows:

- Zero-current phenomena is explained and verified through mathematical derivations based on two-level and three-level NPC SVG.

- It is concluded that the zero-current phenomena must occur after an IGBT OC fault as long as the converters work under the pure reactive power condition. It is verified that a zero-current interval with a certain length follows OC faults for both two-level and NPC three-level SVGs as shown in Table III.

- Mathematical models of a single OC fault are given in this paper. Mathematical expressions of the fault phase current in a single OC fault are also presented.

- Both capacitive and inductive reactive power condition are considered. In addition, the unbalanced load condition is discussed.

In addition, a clear definition of the polluted-area and zero- current interval are given. Simulation and experimental results are presented to verify the correctness of the analysis. This analysis method also applies to other rectifier occasions.

This paper is organized as follows. In Section II, the zero- current after an OC fault is analyzed based on a two-level static var generator. Both inductive and capacitive reactive power situations are considered. Then, the zero-current after an OC fault is analyzed based on a NPC three-level static var generator in Section III. Similarly, both inductive and capacitive reactive power situations are considered. The unbalanced load situation is discussed in Section IV. Experimental results are illustrated in Section V to verify the correctness of the simulations. Finally, some conclusions are summarized in Section VI.

II. ZERO-CURRENT ANALYSIS OF AN OC FAULT IN A TWO-LEVEL SVG

The two-level SVG topology is represented in Fig. 1. For each leg (A or B or C), there are two IGBTs and two Diodes, which are defined as S_X1, S_X2, D_X1 and D_X2. In this paper, X∈(A, B, C). The output current i_X of leg X is shown in Fig. 1, with a reference direction.

Fig. 1. Schematic of a two-level SVG.

The pulse state is given by:

    (1)

A. Inductive Reactive Power Condition

Assuming that pure inductive reactive power is generated for a SVG system, the three phase current i_A, i_B and i_C are fundamental sinusoidal shaped with 90 degrees delays of the grid voltages e_A, e_B and e_C, respectively. If an OC fault occurs, the fault phase current is greatly distorted. A typical example of a S_A1 OC fault in the inductive reactive power condition is introduced in Fig. 2, which shows i_A and e_A in both the normal and fault conditions. It can be seen that the positive half-cycle of the current i_A has been seriously affected.

Fig. 2. Fault phase current i_A before and after a S_A1 OC fault.

As shown in Fig. 2, the area of i_A≥0 (shadow area) is defined as the current-polluted area in a S_A1 OC fault. The reason is as follows. If i_A<0, regardless of whether S_A=1 or S_A=0, i_A does not flow through S_A1, which means that the failure of S_A1 has no effect on the system. In the current- polluted area (area i_A≥0) only, the current failed to flow through S_A1 to the bus “+” under the condition of S_A=1, resulting in the current distortion phenomena.

In addition, in the current-polluted area, the current does not flow through S_A2 or D_A1 due to the unidirectional conductance. Then, D_A2 provides an unique current path for i_A unless phase A is isolated (i_A=0). Therefore, a system with a S_A1 OC fault can be simplified as shown in Fig. 3.

Fig. 3. Simplified schematic of a two-level SVG in a S_A1 OC fault.

Ignoring the on-state voltage drop of the IGBT and diode, the mathematical model of SVG in the current-polluted area can be expressed as (2)-(5):

   (2)

   (3)

    (4)

      (5)

Assuming that , and , it can be deduced by (2)-(5) that:

   (6)

As shown in (6), the sign of the current rate of change di_A/dt is determined by S_B, S_C, u_dc and e_A, among which u_dc can be considered as a stable constant, and e_A can be expressed as:

      (7)

Let f=(S_B+S_C)·u_dc/3. If S_B=S_C=0, then f=0. If S_B=1,S_C=0 or if S_B=0,S_C=1, then f=u_dc/3. If S_B=1,S_C=1, then f=2·u_dc/3. For a clearer explanation, the curves of e_A and –f are shown in Fig. 4(a). Assuming that 1.7·U_m<u_dc<3·U_m, which is usually employed for SVG applications, the intersections P of the curves are: P₁(θ₁=90°), P₂(θ₂=arccos(-u_dc/(3·U_m)) and P₃(θ₃=180°).

By comparing the values of e_A and –f in Fig. 4(a), the sign of di_A/dt in (6) is easily obtained, as follows:

Fig. 4. S_A1 OC fault in the inductive power condition for a two-level SVG: (a) comparison between e_A and –f; (b) effect of (S_B,S_C) on the sign of di_A/dt.

(a)

(b)

In the interval θ:(θ₀-θ₁), for the pulse states (S_B,S_C), di_A/dt<0.

In the interval θ:(θ₁-θ₂), for the pulse state (S_B=0,S_C=0), di_A/dt>0; and for the other three pulse states (S_B,S_C), di_A/dt<0.

In the interval θ:(θ₂-θ₃), for the pulse state (S_B=1,S_C=1), di_A/dt<0; and for the other three pulse states (S_B,S_C), di_A/dt>0.

The effect of (S_B,S_C) on the sign of di_A/dt is displayed more vividly in Fig. 4(b), where it can be seen that the value of i_A keeps decreasing regardless of the states of (S_B,S_C) in the interval θ:(θ₀-θ₁). Since i_A happens to pass through the zero point at θ₀, the value of i_A must be zero in the interval θ:(θ₀-θ₁). Then, the following conclusions can be drawn:

Conclusion I: When a S_A1 OC fault occurs in a two-level SVG in the pure inductive reactive power condition, there must be a zero-current interval with a length of 90°, i.e. 1/4 of a supply period.

In addition, it can be seen that i_A is still difficult to establish in the interval θ:(θ₁-θ₂) of Fig. 4(b), because it is increased only when the pulse state is (S_B=0,S_C=0). The fault phase current does not recover until it enters the interval θ:(θ₂-θ₃).

To verify the validity of Conclusion I, a MATLAB / SIMULINK model has been built. The system parameters involved in the simulation are shown in Table I.

TABLE I SIMULATION PARAMETERS

Parameter	Value
eAB,eBC,eCA	380V(RMS)
iA,iB,iC	28A(RMS)
LA, LB, LC	1mH
udc	720V
Bus capacitance C	4800µF
Switching frequency	5kHz
Sampling frequency	12.5kHz

Simulation results of a S_A1 OC fault are shown in Fig. 5. In Fig. 5(a), (θ₀,θ₁,θ₂,θ₃) are (0°,90°,140.5°,180°). The S_A1 OC fault occurs in the negative half-cycle of the A-phase current. However, i_A is not polluted until it enters the current-polluted area. A zero-current interval with a length of 90° clearly exists in the interval θ:(θ₀-θ₁). Then, i_A recovers in the interval θ:(θ₂-θ₃). Fig. 5(b) shows details of both (S_B,S_C) and i_A in the interval θ:(θ₂-θ₃), where i_A decreases right after the function of the pulse (S_B=1,S_C=1) and increases at the rest values of (S_B,S_C). The simulation results verify the correctness of Conclusion I.

Fig. 5. Simulation results of a S_A1 OC fault in the inductive power condition for a two-level SVG : (a) fault phase current i_A, supply voltage e_A and (S_B,S_C); (b) di_A/dt and (S_B,S_C).

(a)

(b)

For a two-level SVG, this section explains only a S_A1 OC fault. However, it is quite easy to introduce the other five IGBT OC faults with similar conclusions, and that a zero- current interval with a length of 90° must exist in the inductive reactive power condition.

B. Capacitive Reactive Power Condition

When a S_A1 OC fault occurs in a two-level SVG in the capacitive reactive power condition, the fault phase current i_A is still distorted in its positive half cycle, which is also defined as the current-polluted area.

Based on the mathematical models shown in (2)-(5), a comparison of e_A and -f is shown in Fig. 6(a), where e_A is defined as:

    (8)

The three intersections of e_A and –f in Fig. 6(a) are P₁(θ₁=arcsin(-u_dc/(3·U_m))+90°), P₂(θ₂=90°) and P₃(θ₃=180°).

Fig. 6. S_A1 OC fault in the capacitive power condition for a two-level SVG: (a) comparison between e_A and –f; (b) effect of (S_B,S_C) on the sign of di_A/dt.

(a)

(b)

As shown in the interval θ:(θ₂-θ₃) in Fig. 6(b), di_A/dt<0 is true for the values of (S_B,S_C), which means that i_A continues to decrease. Then, Conclusion II is made as follows:

Conclusion II: When a S_A1 OC fault occurs in a two-level SVG in the capacitive reactive power condition, there must be a zero-current interval with a length of 90°.

Simulation results for this case are illustrated in Fig. 7(a) and Fig. 7(b). The simulation has the same system parameters shown in Table 1. Here, (θ₀,θ₁,θ₂,θ₃) are (0°,39.5°,90°,180°). Fig. 7(b) shows real time details of (S_B,S_C) and i_A, where the value of di_A/dt changes according to the trend shown in Fig. 6(b).

Fig. 7. Simulation results of a S_A1 OC fault in the capacitive power condition for a two-level SVG: (a) fault phase current i_A, supply voltage e_A and (S_B,S_C); (b) di_A/dt and (S_B,S_C).

(a)

(b)

Simulation results prove that a zero-current interval with a length of 90° must occur when there is a single IGBT OC fault in both the inductive and capacitive reactive power conditions for a two-level SVG. The only difference is that one of the zero-current intervals occurs at the beginning of the current-polluted area, while the other occurs at the end of the current-polluted area.

III. ZERO-CURRENT ANALYSIS OF AN OC FAULT IN A NPC THREE-LEVEL SVG

The NPC three-level SVG topology is represented in Fig. 8. For each leg (A or B or C), there are 4 IGBTs and 6 Diodes, which are defined as S_X1, S_X2, S_X3, S_X4, D_X1, D_X2, D_X3, D_X4, D_X1-clamp and D_X2-clamp(X∈(A, B, C)). The output current i_X of leg X is shown in Fig. 8, with a reference direction.

Fig. 8. Schematic of a NPC three-level SVG.

The pulse state is given by:

      (9)

For a three-level SVG, only S_A1 and S_A2 OC faults are discussed. However, the other 10 IGBT cases can be similarly deduced.

A. Inductive Reactive Power Condition

When S_A1 experiences an OC fault, if the pulse state S_A=0 or -1, S_A1 is not used and is kept off. If S_A=1 and i_X<0, current flows to the dc bus “+” through D_A1 and D_A2, and system is not affected. If S_A=1 and i_A>0, point A is cut off from the dc bus “+” and finds a new current path of M->D_A1-clamp->S_A2->X. In this case, i_A is polluted.

Similarly, the area of i_A≥0 is defined as the current-polluted area in the presence of a S_A1 OC fault and the system can be simplified as shown in Fig. 9. There are only two possible current paths of i_A in this case, which are indicated by the dashed lines in Fig. 9.

Fig. 9. Simplified schematic of a NPC SVG in the presence of a S_A1 OC fault.

Assuming that u_dc1=u_dc2=u_dc/2 and ignoring the turn-on voltage drop of the IGBT and diode, the mathematical model of a SVG in the current-polluted area can be expressed as (10)-(13):

    (10)

   (11)

   (12)

(S_A1 OC fault of three-level SVG)   (13)

By (10)-(13), (14) can be easily obtained as follows:

          (14)

Let . Then, all of the possible values of –f are shown in Table II.

TABLE II VALUES OF -F

(SA,SB,SC)	-f
(-1,1,1);	-2udc/3
(-1,0,1); (-1,1,0);	-udc/2
(0,1,1); (1,1,1); (-1,-1,1); (-1,0,0); (-1,1,-1);	-udc/3
(0,0,1); (0,1,0); (1,0,1); (1,1,0); (-1,-1,0); (-1,0,-1);	-udc/6
(0,0,0); (0,1,-1); (0,-1,1); (1,-1,1); (1,0,0); (1,1,-1); (-1,-1,-1);	0
(0,0,-1); (0,-1,0); (1,-1,0); (1,0,-1);	udc/6
(0,-1,-1); (1,-1,-1);	udc/3

e_A is defined in (7). The curves of e_A and –f are shown in Fig. 10(a), with six intersections as follows: P₁(θ₁=arcos (u_dc/(3·U_m))), P₂(θ₂=arcos(u_dc/(6·U_m))), P₃(θ₃=90°), P₄(θ₄= arcos(-u_dc/(6·U_m))), P₅(θ₅=arcos(-u_dc/(3·U_m))) and P₆(θ₆=180°).

Fig. 10. S_A1 OC fault in the inductive power condition for a NPC three-level SVG: (a) comparison between e_A and –f; (b) effect of (S_A,S_B,S_C) on the sign of di_A/dt.

(a)

(b)

Then, the effect of each pulse state (S_A,S_B,S_C) on the changing rate of i_A can be determined as shown in Fig. 10(b).

With respect to the 8 pulse vector states of a two-level convertor, a three-level convertor has 27 pulse vector states, making this case more complicated.

It can be seen that in the interval θ:(θ₀-θ₁) of the current-polluted area in Fig. 10(b), for all 27 pulse states, di_A/dt<0 is true. With the fact that i_A happens to pass through the zero point at θ₀, Conclusion III can be made:

Conclusion III: When a S_A1 OC fault occurs in a NPC three-level SVG in the inductive reactive power condition, there must be a zero-current interval with a length of θ. Here, θ=arcos(u_dc/(3·U_m)).

The corresponding simulation results are shown in Fig. 11. Here, the simulation also shares the system parameters shown in Table I, and (θ₀,θ₁,θ₃,θ₆) is (0°,39.5°,90°,180°). The value of θ mentioned in Conclusion III is 39.5° , corresponding to θ:(θ₀-θ₁) in Fig. 11.

Fig. 11. Simulation results of a S_A1 OC fault in the inductive power condition for a NPC three-level SVG .

Next, a S_A2 OC fault will be discussed.

When S_A2 experiences an OC fault, if the pulse state S_A=-1, S_A2 is not used and is kept off. If S_A=0 and i_A<0, current flows to point M through S_A3 and D_A2-clamp, and system is not affected. If S_A=0 and i_A>0, point A is cut off from point M, and current flows following the path of “-”->D_A4->D_A3->A. In this case, i_A is polluted. If S_A=1 and i_A<0, current flows to the point “+” through D_A1 and D_A2, and system is not affected. If S_A=1 and i_A>0, current flows following the path of “-”->D_A4->D_A3->A, and i_A is polluted.

The area of i_A≥0 is defined as the current-polluted area in a S_A2 OC fault and the system can be simplified as shown in Fig. 12.

Fig. 12. Simplified schematic of a NPC three-level SVG in the presence of a S_A2 OC fault.

Similarly, the mathematical model of a SVG in the current-polluted area can be expressed as (15)-(18):

&sp;  (15)

       (16)

       (17)

       (18)

Then, (19) can be easily obtained as follows:

   (19)

Let . In addition, e_A is defined as in (8). The curves of e_A and –f are shown in Fig. 13(a), with four intersections as follows: P₁(θ₁=90°), P₂(θ₂=arccos(-u_dc/(6·U_m))), P₃(arccos(-u_dc/(3·U_m))) and P₄(θ₄=180°).

Fig. 13. S_A2 OC fault in the inductive power condition for a NPC three-level SVG: (a) comparison between e_A and –f; (b) effects of (S_A,S_B,S_C) on the sign of di_A/dt.

(a)

(b)

When S_A2 experiences an OC fault, the effect of each pulse state (S_A,S_B,S_C) on the sign of the changing rate di_A/dt can be determined as shown in Fig. 13(b).

In the interval θ:(θ₀-θ₁) of the current-polluted area, for all 27 pulse states, di_A/dt<0 is true. Conclusion IV can be made:

Conclusion IV: When a S_A2 OC fault occurs in a NPC three-level SVG in the inductive reactive power condition, there must be a zero-current interval with a length of 90°.

Simulation results of a S_A2 OC fault are shown in Fig. 14, where the zero-current interval corresponds to θ:(θ₀-θ₁). Here, (θ₀,θ₁,θ₂,θ₃,θ₄) are (0°,90°,112.7°,140.5°,180°).

Fig. 14. Simulation results of a S_A2 OC fault in the inductive power condition for a NPC three-level SVG.

It can be seen from a comparison between Fig. 14 and Fig. 11 that a S_A2 OC fault has a greater influence on the system than a S_A1 OC fault.

B. Capacitive Reactive Power Condition

When capacitive reactive power is generated in a NPC three-level SVG, the interval-current interval can be similarly deduced.

First, if S_A1 experiences an open circuit fault, e_A in (7) and –f in (14) are drawn in Fig. 15(a), with six intersections as follows: P₁(θ₁=arcsin(-u_dc/(3·U_m))+90°), P₂(θ₂=arcsin(-u_dc/(6·U_m)) + 90°, P₃(θ₃=90°), P₄(θ₄=arcsin(u_dc/(6·U_m))+90°), P₅(θ₅= arcsin(u_dc/(3·U_m))+90°) and P₆(θ₆=180°).

Fig. 15. S_A1 OC fault in the capacitive power condition for a NPC three-level SVG: (a) comparison between e_A and –f; (b) effect of (S_A,S_B,S_C) on the sign of di_A/dt.

(a)

(b)

Then the effect of each pulse state (S_A,S_B,S_C) on the rate of the current i_A can be determined as shown in Fig. 15(b).

Similarly, Conclusion V is drawn:

Conclusion V: When a S_A1 OC fault occurs in a NPC three-level SVG in the capacitive reactive power condition, there must be a zero-current interval with a length of θ. Here, θ=arcos(u_dc/(3·U_m)).

When compared with the inductive power condition, the zero-current interval comes at the end of the current-polluted area, which corresponds to θ:(θ₅-θ₆) in the simulation results presented in Fig. 16.

Fig. 16. Simulation results of a S_A1 OC fault in the capacitive power condition for a NPC three-level SVG.

Next, a S_A2 OC fault will be discussed.

If S_A2 experiences an open circuit fault, e_A in (8) and –f in (19) are drawn in Fig. 17(a), with four intersections as follows: P₁(θ₁=arcsin(-u_dc/(3·U_m))+90°), P₂(θ₂=arcsin(-u_dc/(6·U_m))+ 90°, P₃(θ₃=90°) and P₄(θ₄=180°).

Fig. 17. S_A2 OC fault in the capacitive power condition for a NPC three-level SVG: (a) comparison between e_A and –f; (b) effect of (S_A,S_B,S_C) on the sign of di_A/dt.

(a)

(b)

The effect of each pulse state (S_A,S_B,S_C) on the rate of the current i_A can be determined as shown in Fig. 17(b).

Noticing that in the interval θ:(θ₃-θ₄), di_A/dt<0 is true for all 27 pulse states, Conclusion VI is made:

Conclusion VI: When a S_A2 OC fault occurs in a NPC three-level SVG in the capacitive reactive power condition, there must be a zero-current interval with a length of 90°.

Simulation results for this case are shown in Fig. 18, where the zero-current interval corresponds to θ:(θ₃-θ₄).

Fig. 18. Simulation results of a S_A2 OC fault in the capacitive power condition for a NPC three-level SVG.

In summary, Table III shows the length of the zero-current interval for all single IGBT OC faults. For both inductive and capacitive reactive power conditions, the zero current intervals share the same length. However, they occur at different times which are determined by the phase of the voltage and current.

TABLE III SUMMARY OF THE ZERO-CURRENT INTERVAL FOR ALL CASES

Topology	Fault Location	Length of Zero-Current Interval for both Inductive and Capacitive Power Condition
	SX1	90°(1/4 of supply period)
	SX2
	SX1	arcos(udc/(3·Um))
	SX2	90°(1/4 of supply period)
	SX3
	SX4	arcos(udc/(3·Um))

IV. UNBALANCED LOAD AND INPUT VOLTAGE CASES DISCUSSION

In the unbalanced load situation, the three phase currents can be decomposed into positive sequence current, negative sequence current and zero sequence current . For a three wire system, only positive sequence and negative sequence currents exist. Assuming that e_A=U_m·cos(θ), e_B=U_m·cos(θ-120°) and e_C=U_m·cos(θ+120°), the three phase currents in the normal condition are:

    (20)

Where represents the angle between the positive/ negative sequence current and the input voltage of phase A.

For example, if a S_B1 OC fault occurs in phase B of a two-level SVG, then i_B can be expressed by:

          (21)

Where . Then, the zero current interval of a S_B1 OC fault in the unbalanced load condition for a two-level SVG is shown in Fig. 19.

Fig. 19. Zero current interval in the unbalanced condition for a two-level SVG.

Therefore, when negative sequence currents are involved, the zero current interval is decided by δ. Here, (120°-δ) is the angle between e_X and i_X. For a two-level SVG, the absolute length of the zero current interval of an OC fault is (60°+δ). For a three-level SVG, the zero current interval can be obtained through the same analysis method, which is similar to the above conclusion and not discussed here.

Unbalanced load currents at the same time lead to input voltage unbalance, which is caused by the voltage drop on the line impedance and equivalent impedance of the transformer. In this case, the zero current interval is effected by both the phase deviation of the input voltage e_X (caused by a negative sequence voltage injection) and δ. However, the expression of the unbalanced input voltage is too complicated to deduce. For the light unbalanced input voltage condition, the zero current interval is mainly decided by δ.

V. EXPERIMENTAL VERIFICATION

First, a two-level SVG prototype, shown in Fig. 20(a), is developed to verify Conclusions I and II. Then, a three-level NPC prototype, shown in Fig. 20(b), is developed to verify Conclusions III to VI.

Fig. 20. Experimental prototypes: (a) two-level; (b) NPC three- level.

(a)

(b)

The experimental parameters are listed in Table IV.

TABLE IV EXPERIMENTAL PARAMETERS

	Parameters	Values
Two-level	eAB,eBC,eCA	380V(RMS)
	iA,iB,iC	18A(RMS)
	LA, LB, LC	1.5mH
	udc	720V
	Bus capacitance C	2200µF
	Switching frequency	2.5kHz
	Sampling frequency	12.5kHz
NPC Three-level	eAB,eBC,eCA	380V(RMS)
	iA,iB,iC	14A(RMS)
	LA, LB, LC	2mH
	udc	720V
	Bus capacitance C	6800µF
	Switching frequency	5kHz
	Sampling frequency	10kHz

For both the two-level and three-level SVGs, two typical reactive powers, inductive reactive powers and capacitive reactive powers, are generated to show whether the open-circuit fault current is bound to have a zero-current interval as described in Conclusions I through VI. An OC fault is achieved by unplugging the fiber pulse or by blocking the pulses in the CPLD control unit.

In fact, when the OC fault occurs, the three-phase current is distorted. Here, the focus is on the fault phase current changes, since it is of great regularity.

Experimental results of the two-level SVG are shown in Fig. 21. In Fig. 21(a), an OC fault occurs in the inductive reactive power condition and at the beginning of each positive half- cycle of the fault-phase current, i.e. the current-polluted area. In addition, a zero-current interval of 90 degrees appears, as described in Conclusion I. In Fig. 21(b), an OC fault occurs in the capacitive reactive power condition and at the end of each positive half-cycle of the fault-phase current, i.e. the current- polluted area. In addition, a zero-current interval of 90 degrees appears, as described in Conclusion II.

Fig. 21. S_A1 OC fault for a two-level SVG: (a) inductive reactive power condition; (b) capacitive reactive power condition.

(a)

(b)

Next, experimental results of a NPC three-level SVG are illustrated in Fig. 22.

Fig. 22. OC fault for a two-level SVG: (a) S_A1 OC fault for the inductive reactive power condition; (b) S_A2 OC fault for the inductive reactive power condition; (c) S_A1 OC fault for the capacitive reactive power condition; (d) S_A2 OC fault for the capacitive reactive power condition.

(a)

(b)

(c)

(d)

As shown in Fig. 22, for a three-level SVG, a S_A2 OC fault has a more severe impact on the system than a S_A1 OC fault. Consistent with conclusions III to VI, a 90 degree zero- current interval appears in the S_A2 OC fault, while a 39.5 degree zero-current interval appears in the S_A1 OC fault.

It is worth emphasizing that Conclusions I though VI are independent of the system parameters. As long as the system is running under the pure inductive or capacitive reactive power case, the fault phase current must have a corresponding length of the zero-current interval.

Due to Conclusions I through VI, there is a better understanding of the effects of OC faults on the fault phase current. This is instructive for future OC fault location studies.

VI. CONCLUSIONS

When a single IGBT OC fault occurs in two-level and NPC three-level converters, the three-phase currents are distorted, especially the fault phase current which can drop directly to zero in some cases. A method to effectively analyze the changing rules of fault current has not been discussed in previous studies. In this paper, an effective method based on learning the current change rate is proposed to summarize the rules of fault phase current. Taking a SVG as the research object, a mathematical model under an OC fault is introduced. Then, the influence of the pulse on the sign of the current changing rate is analyzed. Finally, some conclusions are drawn. A zero-current interval with a length of 1/4 of a supply period follows the OC fault in both pure inductive and capacitive reactive power conditions for a two-level SVG. On the other hand, for a three-level SVG, a zero-current interval with length of arcos(u_dc/(3·U_m)) follows S_X1 and S_X4 OC faults and a zero-current interval with a length of 1/4 of a supply period follows S_X2 and S_X3 OC faults. The theoretical analysis and conclusions are instructive for future OC fault location studies.

ACKNOWLEDGMENT

The work described in this paper was fully supported by Special Fund for the Transformation of Scientific and Technological Achievements of Jiangsu Province (No. BA2016017), and Sub Project of the National Key R & D Program (No. 2016YFC0600804).

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Ke Wang was born in Xuzhou, China, in 1985. He received his B.S. degree in Electrical Engineering and Automation, and his M.S. degree in Power Electronics and Drives from the China University of Mining and Technology, Xuzhou, China, in 2005 and 2009, respectively, where he is presently working towards his Ph.D. degree in the School of Electrical and Power Engineering. His current research interests include power quality compensation systems, fault diagnosis and power electronics.

Hong-Lu Zhao was born in Xuzhou, China, in 1994. She received her B.S. degree from the Zhejiang Sci-Tech University, Hangzhou, China, in 2016. She is presently working towards her M.S. degree at the China University of Mining and Technology, Xuzhou, China. Her current research interests include thermal characterization modeling of IGBT power modules and the fault-tolerant control of inverters.

Yi Tang was born in Zhangjiagang, China, in 1957. He received his Ph.D. degree from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 1995. He is presently working as a Professor in the China University of Mining and Technology. His current research interests include power quality and power system analysis.

Xiao Zhang was born in Baoji, China, in 1974. He received his M.S. and Ph.D. degrees from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 2003 and 2012, respectively. In 1997, he joined the China University of Mining and Technology as a Teaching Assistant, where he has been an Associate Professor since 2009. From October 2013 to October 2014, he was a Visiting Professor at Ohio State University, Columbus, OH, USA. His current research interests include power electronic converters, reactive power control, harmonics, power quality compensation systems, and the application of power electronics in renewable energy systems and motor control.

Chuan-Jin Zhang was born in Xuzhou, China, in 1986. He received his B.S. degree from the School of Electrical Engineering, Northeast Dianli University, Jilin, China, in 2009; and his M.S. degree in Power Electronics and Drives from the China University of Mining and Technology, Xuzhou, China, in 2012, where he is presently working towards his Ph.D. degree in the School of Electrical and Power Engineering. His current research interests include power quality compensation systems, motor control and power electronics.