사각형입니다.

https://doi.org/10.6113/JPE.2018.18.3.662

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Novel Single Switch DC-DC Converter for High Step-Up Conversion Ratio


Xuefeng Hu*, Benbao Gao*, Yuanyuan Huang, and Hao Chen*


†,*School of Electrical Engineering, Anhui University of Technology, Ma’anshan, China



Abstract

This paper presents a new structure for a step up dc-dc converter, which has several advantageous features. Firstly, the input dc source and the clamped capacitor are connected in series to transfer energy to the load through dual voltage multiplier cells. Therefore, the proposed converter can produce a very high voltage and a high conversion efficiency. Secondly, a double voltage clamped circuit is introduced to the primary side of the coupled inductor. The energy of the leakage inductance of the coupled inductor is recycled and the inrush current problem of the clamped circuits can be shared equally by two synchronous clamped capacitors. Therefore, the voltage spike of the switch tube is solved and the current stress of the diode is reduced. Thirdly, dual voltage multiplier cells can absorb the leakage inductance energy of the secondary side of the coupled inductor to obtain a higher efficiency. Fourthly, the active switch turns on at almost zero current and the reverse-recovery problem of the diodes is alleviated due to the leakage inductance, which further improves the conversion efficiency. The operating principles and a steady-state analysis of the continuous, discontinuous and boundary conduction modes are discussed in detail. Finally, the validity of this topology is confirmed by experimental results.


Key words: Clamp circuits, DC-DC, Dual voltage multiplier cells, Floating active switch, Switched-coupled-inductor


Manuscript received Aug. 29, 2017; accepted Dec. 13, 2017

Recommended for publication by Associate Editor Honnyong Cha.

Corresponding Author: 2412490363@qq.com Tel: +86-15755390199, Anhui University of Technology

*School of Electrical Engineering, Anhui Univ. of Tech., China



Ⅰ. INTRODUCTION

In recent years, some problems such as fossil energy depletion, global warming and environmental pollution have become more and more serious. Therefore, distributed generation (DG) systems based on renewable energy sources have attracted considerable attention around the world, including photovoltaic (PV) generation systems, wind generation, fuel cell systems, etc. [1]-[8]. However, the output voltage of renewable energy sources is low and variable. Therefore, high step up dc-dc converters with a high efficiency are generally required as the front-end stage for renewable energy generation systems.

Although the basic boost converter theoretically has the function for lifting input voltage, it cannot obtain a very large conversion ratio with a high power and high efficiency due to its extreme duty cycle. This is because the extreme duty cycle causes large conduction losses and a serious diode reverse recovery problem, which leads to a sharp decline in conversion efficiency [9]-[11]. In addition, a forward or flyback dc-dc converter can be used to increase the voltage gain by adjusting the turns ratio of the isolation transformer. However, the primary switch and secondary diode suffer from a high voltage spike, which greatly affects the efficiency of the converter. In order to solve this problem, active-clamp and non-dissipative snubber technologies are employed. However, an extra power switch and driver are needed, and the energy of the primary leakage inductance is still not easy to recycle, which makes the pursuit of a high conversion efficiency very difficult. In recently published studies [12], [13], some high gain boost converters have been presented based on diverse technologies, including the cascaded types, the switched capacitor/inductor types, the voltage-lift types [14]-[19], and the coupled inductor types [20]-[37]. These technologies play a positive role in raising the voltage gain. However, they have their advantages and disadvantages. Therefore, it makes sense to combine several technologies for putting forward high efficiency and high step up converters.

This paper proposes a new single switch dc-dc converter topology that adopts the switched capacitor and coupled inductor techniques. On the basis of a Zeta converter, this topology substitutes a coupled inductor for the input inductance of the Zeta converter. Furthermore, two clamped circuits are introduced to the primary side of the coupled inductor. The single switch dc-dc converter topology, as shown in fig. 1, is configured from a floating active switch S1 and a coupled inductor, two passive clamped circuits, and dual voltage multiplier cells. It should be added that the two passive clamp circuits are composed of the active switch S1, the clamped capacitor C1 and the clamped capacitor C2. In addition, it should be added that dual voltage multiplier cells are composed of the coupled inductor secondary side winding, the capacitor C4, the diode D4, the capacitor C3 and the diode D3. The features of the proposed converter are as follows. 1) Dual passive clamped circuits recycle the leakage inductor energy of the coupled inductor, share the inrush current and clamp the voltage stress of the active switch to a lower level. Moreover, the clamp capacitors are connected in series to discharge for the purpose of extending the voltage gain. 2) The switched capacitors in the voltage multiplier cells are synchronously charged from different flows, and they are discharged in series to obtain a higher voltage gain. 3) Power switch turn on occurs with almost zero current, which significantly reduces the conduction loss. In addition, the current variation ratio (di/dt) presented by all of the diodes is limited due to the leakage inductance of the coupled inductor.


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Fig. 1. Circuit configuration of the proposed converter.



Ⅱ. OPERATIONAL PRINCIPLE OF THE PROPOSED CONVERTER

Fig. 2 shows an equivalent circuit of the proposed converter. The circuit model of the coupled inductor includes the magnetizing inductor Lm, the primary and secondary leakage inductors Lk1 and Lk2, and the ideal transformer primary and secondary windings N1 and N2.


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Fig. 2. Equivalent circuit of the proposed converter.


In order to simplify the circuit analysis, the following assumptions are made.

1) All of the power devices are ideal. However, the leakage inductance of the coupled inductor is taken into consideration.

2) The capacitors C4~Co are sufficiently large. Therefore, the voltages across these capacitors are constant during one period.

3) The turns ratio n of the coupled inductor is equal to N2 / N1.

The working principles of the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) are described as follows.


A. CCM Operation

This section presents the CCM operation principle of the proposed converter. Fig. 3 represents several key waveforms during one switching period. The five operating modes are depicted in Fig. 4.


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Fig. 3. Key waveforms of the proposed converter during the CCM operation.


Mode I [t0-t1]: At t=t0, the switch S1 is turned on, Fig. 4(a) depicts the current flow path of this stage. Only the diode Do is conducting. The diodes D1, D2, D3 and D4 are reverse-biased by VC1+Vin, VC2+Vin, VO-VC4-VC2-VC1-Vin and VO-VC3. It can be seen that the source voltage Vin transfers energy to the magnetizing inductor Lm and the primary leakage inductor Lk1. Meanwhile, the magnetizing inductor Lm is series connected with C3 and C4 to delivering their energy to the charge output capacitor Co and the load R. The secondary leakage inductor current iLk2 of the coupled inductor is decreased linearly. This stage ends when the current iLk1 = iLm at t=t1.


Fig. 4. Current flow paths during one switching period under the CCM operation. (a) Mode I. (b) Mode II. (c) Mode III. (d) Mode IV. (e) Mode V.

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(a)

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(b)

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(c)

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(d)

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(e)


Mode II [t1-t2]: During this time interval, S1 remains turned on, and the diodes D3 and D4 are turned on. The diodes D1 and D2 are still blocked by VC1+Vin and VC2+Vin. The diode Do is blocked by VO-VC3. Fig. 4(b) shows the current flow path of this mode. As can be seen, the inductors Lm and Lk1 are still charged by Vin. In the meantime, some of the energy of the magnetizing inductor Lm is delivered to the secondary side via the coupled inductor to charge the capacitor C4. Moreover, the source energy Vin is serially connected with the capacitor C1, the secondary winding N2 and the capacitor C2 to charge the capacitor C3 through the diode D3. The load energy is supplied by the output capacitor Co. This mode ends when the switch S1 is turned off at t= t2.

Mode III [t2-t3]: At t=t2, the switch S1 is turned off, and the diodes D1, D2 and D4 are turned on. The diodes D3 and Do are reverse-biased by VC3-VC4-VC1 and VO-VC3. The current flow path of this period is shown in Fig. 4(c). Once S1 is switched off, the energy stored in Lk1 is rapidly discharged to the capacitor C1 through the diode D1. Simultaneously, the energy stored in Lk1 is also discharged to the capacitor C2 through the diode D2. Therefore, the capacitor C1 and the capacitor C2 are charged in parallel. At the same time, the secondary leakage inductor Lk2 keeps the same current direction for charging the capacitor C4 through the diode D4. These energy transfers bring about decreases in iLk1 and iLk2 but increases in iLm, because Lk1 and Lk2 are significantly smaller than Lm, and iLk2 rapidly declines. Therefore, the magnetizing inductor Lm receives energy from Lk1, the energy stored in the capacitor Co is discharged to the load R. This mode ends when the current iLk2 drops to zero at t= t3.

Mode IV [t3-t4]: During this interval, S1 is kept turned off. Only the diodes D1, D2 and Do are conducting. The diodes D3 and D4 are blocked by VO-VC4-VC1 and VO-VC3. Fig. 4(d) illustrates the current flow path of this stage. The energy stored in Lm and Lk1 continue to release to the capacitors C1 and C2. The voltage stress of the active switch is limited by the double clamp circuits, and the leakage inductor energy can be effectively recycled. In the meantime, the energy stored in Lm is released to the capacitor Co and R via the secondary side N2 of the coupled inductor, and in series with C3 and C4 to charge the capacitor Co and R. Therefore, the currents of iLk1 and iLm are rapidly decreased but iLk2 is linearly increased. Once the current iLk1 declines to zero, this mode ends at t= t4.

Mode V [t4-t5]: At t=t4, S1 is still turned off. Since iLk1=0 at t=t4, the diodes D1 and D2 are naturally turned off, and only the diode Do is conducting. The current flow path of this period is shown in Fig. 4(e). The magnetizing inductor Lm and the capacitors C3 and C4 are still series connected to deliver their energy to the capacitor Co and R. This mode ends when the switch S1 is turned on at t= t5, which is the start of the next switching period.


B. DCM Operation

The detailed operating principle of the discontinuous conduction mode (DCM) is presented in this section. There are five operating modes during one switching period. Fig. 5 shows key waveforms for some of the components. The operating modes are presented as follows.


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Fig. 5. Key waveforms of the proposed converter during the DCM operation.


Mode I [t0-t1]: At t=t0, S1 is turned on. The diodes D3 and D4 are turned on, and the diodes D1, D2 and Do are turned off. The current flow path is shown in Fig. 6(a). In this mode, iLm, iD2 and iD3 increase because the capacitor C3 is charged from the source energy Vin, and the capacitors C1 and C2. In addition, the magnetizing inductor Lm is receiving energy from Vin. Meanwhile, some of the energy stored in Lm is released to the capacitor C4 through the diode D4. The output capacitor Co provides its energy to the load R. Once the switch S1 is switched off, this mode ends at t= t1.


Fig. 6. Current paths during one switching period under the DCM operation. (a) Mode I. (b) Mode II. (c) Mode III. (d) Mode IV. (e) Mode V.

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(a)

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(b)

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(c)

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(d)

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(e)


Mode II [t1-t2]: At t= t1, S1 is turned off. The diodes D1 and D2 start to turn on, and the diodes D3 and Do are turned off. Fig. 6(b) depicts the current flow path of this period. The energy stored in the coupled inductor is delivered to the capacitors C1 and C2 through the diodes D1 and D2. Meanwhile, the capacitor C4 is still charged by the magnetizing inductor Lm. Thus, the currents of iLm, iD1 and iD2 are linearly decreased. The energy stored in the capacitor Co is released to the load R. This mode ends when the current iD4 reaches zero at t= t2.

Mode III [t2-t3]: In this mode, S1 remains turned off. The diodes D1, D2 and Do start to turn on, and diodes D3 and D4 are turned off. Fig. 6(c) depicts the current flow path of this period. The energy stored in the magnetizing inductor Lm is delivered to the capacitors C1 and C2 through the diodes D1 and D2. At the same time, iDo increases because Lm is in series with C3 and C4 to charge the capacitor Co and R. This mode ends at t= t3 when iD1 = iD2 =0.

Mode IV [t3-t4]: During this interval, S1 remains turned off. Only the diode Do is conducting. The current flow path is shown in Fig. 6(d). The magnetizing inductor Lm continues to linearly discharge. The energies stored in Lm, and the capacitors C3 and C4 are series connected, and release their energy to the capacitor Co and R through the diode Do. This stage ends when the energy stored in the magnetizing inductor Lm is equals to zero at t= t4.

Mode V [t4-t5]: At t= t4, All of the power devices are turned off. Fig. 6(e) illustrates the current flow path of this stage. Because the energy stored in Lm is already depleted, the energy stored in the capacitor Co is released to the load R. This mode ends when the switch S1 is turned on at t= t5, which is the start of the next switching period.



Ⅲ. STEADY-STATE ANALYSIS OF THE PROPOSED CONVERTER


A. CCM Operation

To simplify the steady-state analysis, only modes II and IV are considered for the CCM operation because the times of modes I, III and V are too short to ignore, and all of the leakage inductances of the coupled inductor are neglected.

In mode II, the following equations can be expressed from Fig. 4(b).

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In addition, the voltage of the capacitor C3 can be obtained as:

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During Mode IV, the following equations can be written:

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Applying the inductor volt-second balance principle to the magnetizing inductor Lm and binding the above equations, the voltage across the capacitors C1, C2, C3 and the secondary- side voltage VN2 of the coupled inductor are derived as:

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Substituting (2), (7) and (8) into (5), the dc voltage gain MCCM can be obtained as:

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Fig. 7 shows the voltage gain extension effect with different turns ratios at various duty cycles. In addition, the curve of an approximately straight line accounts for the relationship between the turns ratio and the duty cycle under the voltage gain MCCM=11.


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Fig. 7. Voltage gain of the proposed converter and the turns ratio versus duty cycle when the voltage conversion is 11.


B. Voltage Stress Analysis

During the CCM operation, the voltage and current stresses on the power devices are discussed as follows, and the leakage inductances Lk1 and Lk2 of the coupled inductor are neglected. The voltage stresses on the switch S1 and the diodes D1~Do are given as:

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According to the operating principles, the current ripples on the magnetizing inductor can be derived as:

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The average currents of IC1, IC2, IC3 and IC4 are zero in the steady state. Thus, the average currents that flow through the diodes D1~Do are each equal to the average current of IO. The current stresses on the switch S1 and the diodes D1~Do are expressed as follows:

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Fig. 8 shows the relationship between the normalized power device voltage stresses and the turns ratio of the coupled inductor when D=0.6. It can be seen that the voltage stresses of the power device are always lower than the output voltage. Therefore, a switch with a low resistance RDS (ON) and a high performance can be employed to increase efficiency.


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Fig. 8. Voltage stress curve of power devices when D=0.6.


C. DCM Operation

To simplify the analysis, all of the leakage inductances of the coupled inductor are neglected, and only modes I, III and IV are considered for the DCM operation. When the switch S1 is turned on, the following equations can be written from Fig. 6(a).

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When the switch S1 is turned off, the following equations can be obtained from Fig. 6(c) and Fig. 6(d).

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DLTS is defined as the time during which the current iLm travels from the peak point to zero, when the switch S1 is turned off. By applying the volt-second balance principle to the coupled inductor and binding equations (19)-(23), the voltages of the capacitors C1, C2, C3 and the secondary-side voltage VN2 of the coupled inductor can be obtained as:

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Substituting (20), (25) and (26) into (23), DL can be obtained as:

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According to the steady operating principle, the average currents of ID1 and IDo are equal to the average current of IO, DX which is defined as the duration of the current iD1 decline from the peak value to zero. The peak current of the magnetizing inductor iLmp is given as:

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The average currents of the diodes D1 and Do are expressed as follows:

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From (27) and (28), the following equations are derived as:

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The normalized magnetizing inductor time constant τLm is defined as:

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Since IO=VO/R, by substituting (27), (28) and (33) into (32), the voltage gain of the proposed converter in the DCM can be obtained as:

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Equation (34) can be used to illustrate the DCM voltage gain lines under different τLm. Fig. 9 shows the curve of the voltage gain against the duty cycle under various τLm.


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Fig. 9. Voltage gain versus the duty cycle during the DCM operation under various τLm and during the CCM operation under n=2.


D. BCM Condition

When the proposed converter is operating in the BCM, the voltage gains of MCCM are equal to those of MDCM.

The boundary normalized magnetizing inductor time constant τLmB can be derived from (12) and (34).

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Ⅳ. EXPERIMENTAL RESULTS

In order to verify the effectiveness of the theoretical analysis, a 200W experimental prototype circuit of the proposed converter has been built and tested in the laboratory. The basic parameters of the converter are listed as follows:

1) input voltage Vin: 18-24V;

2) output voltage VO: 200V;

3) maximum output power PO: 200W;

4) switching frequency fs: 40kHz;

5) coupled inductor: EE-55, core pc40, N2/N1=14:7, Lm=66μH, and Lk=2.4μH;

6) power switch S1: IRFB4410PbF;

7) diodes D1/D2: MUR810, D3: MUR840, D4/Do: MUR820;

8) capacitors C1/C2/C4: 100μF/100V, C3: 47μF/200V,

9) CO: 220μF/400V.


Fig. 10(a) shows the gate signal of the switch S1 and the current waveforms of the primary-side current iLk1 and the secondary-side current iLk2 of the coupled inductor. It can be seen that the proposed converter is operated in the CCM operation. It can also be seen that it has five modes during the CCM operation. Fig. 10(b) gives the gate signal of S1 and the current waveforms through the diodes D1 and D2. It can be seen that the currents iD1 and iD2 are nearly synchronous, which confirms that the clamp diodes D1 and D2 are conductive and charged in parallel by the primary leakage inductor Lk1 when the switch S1 is turned off. Fig. 10(c) illustrates the gate signal and waveforms of iD1 and iDo. The diode Do starts to turn on when the current iLk2 declines to zero. In addition, the secondary side of the coupled inductor is series connected with the capacitors C3 and C4 to transfer their energy to the load. Fig. 10(d) shows the gate signal and waveforms of iD3 and iD4. It can be seen that the secondary leakage inductor Lk2 is transferring its energy to the capacitor C4 through the diode D4 when the switch S1 is turned off.


Fig. 10. Experimental current waveforms: (a) vgs, iLk1, iLk2; (b) vgs, iD1, iD2; (c) vgs, iD1, iDo; (d) vgs, iD3, iD4.

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(d)


Fig. 11(a) represents the gate signal of S1 and waveforms including VDS and iDS. Since the switch S1 is turned on, the current of iDS is very small, which makes the switch approximately zero current conduction. In addition, the voltage stress of the switch S1 is only a quarter of the output voltage during the steady-state period, which is about 50V. Therefore, a low voltage rating and low on-state resistance level active switch can be selected for high efficiency. In Fig. 11(b), voltage stress waveforms of the diodes D1, D2 and the output voltage are presented. The measured voltage through the diodes D1 and D2 are found to be about 50V, which is only a quarter of the output voltage. Waveforms of VD1 and VDO are shown in Fig. 11(c). The voltage value of the diode Do is approximately 90V, which lowers to half the output voltage in the steady-state period. Fig. 11(d) illustrates the output voltage and voltage stress of the diodes D3 and D4. The voltage stress of the diode D4 is the same as that of the diode Do, and the value of the diode D3 is about 140V, which shows good agreement with the theoretical analysis. It can be seen that the voltage stresses of these diodes are far lower than the output voltage. Therefore, low-voltage-rated diodes with high performance can be adopted for the presented converter.


Fig. 11. Experimental voltage stress waveforms: (a) vgs, VDS, iDS; (b) VO, VD1, VD2; (c) VO, VD1, VDo; (d) VO, VD3, VD4.

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(d)


Fig. 12 summarizes the efficiency of the proposed converter under various output powers. Under the premise of keeping the output voltage constant, the corresponding output power is achieved by changing the load value. The input voltage and input current are recorded at the same time. Through the efficiency formula operation, the efficiency points of different output powers are obtained. Finally, the efficiency curve is drawn through the efficiency point. The maximum efficiency is up to 95.7%, and the efficiency is about 94.3% at a full-load.


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Fig. 12. Measured efficiency of the proposed converter at various output powers.



Ⅴ. CONCLUSION

A novel DC-DC converter structure is proposed for high voltage gain applications. The clamp capacitor and switch capacitor recycle leakage inductance energy to improve the conversion efficiency and to effectively reduce the peak voltage of the main switch. Moreover, the voltage stresses of the power devices are greatly reduced, and the problem of reverse recovery on the diodes is greatly alleviated. Experimental results have been obtained and they are in agreement with the theoretical analysis. In addition, the topology characteristics of the proposed DC-DC converter have been verified.



ACKNOWLEDGMENT

The authors gratefully acknowledge the National Natural Science Foundation (51577002), the Top-notch Personnel Foundation of the Anhui Higher Education Institutions of China (gxbjZD13), the Natural Science Foundation of Anhui Province of China (1408085ME80), and the Natural Science Foundation of Anhui Education Committee (KJ2012A048) for its financial support.



REFERENCES

[1] H. Kanchev, D. Lu, F. Colas, V. Lazarov, and B. Francois, “Energy management and operational planning of a micro grid with a PV-based active generator for smart grid applications,” IEEE Trans. Ind. Electron., Vol. 58, No. 10, pp. 4583-4592, Oct. 2011.

[2] X. H. Yu, C. Cecati, T. Dillon, and M. G. Simoes, “The new frontier of smart grid,” IEEE Trans. Ind. Electron., Vol. 15, No. 3, pp. 49-63, Sep. 2011.

[3] Bo Yang, W. Li, Y. Zhao, and X. He, “Design and analysis of a grid connected PV power system,” IEEE Trans. Power Electron., Vol. 25, No. 4, pp. 992-1000, Apr. 2010.

[4] S. M. Chen, M. L. Lao, Y. H. Hsieh, T. J. Liang and K. H. Chen, “A novel switched-coupled-inductor DC–DC step-up converter and its derivatives,’’ IEEE Trans. Ind. Appl., Vol. 51, No. 1, pp. 309-314, Jan.-Feb. 2015.

[5] G. C. Silveira, F. L. Tofoli, L. D. S. Bezerra, and R. P. Torrico-Bascopé, “A non isolated DC–DC boost converter with high voltage gain and balance output voltage,’’ IEEE Trans. Ind. Electron., Vol. 61, No. 12, pp. 6739-6746, Dec. 2014.

[6] M. Liserre, T. Sauter, and J. Y. Hung, ‘‘Future energy systems: Integrating renewable energy sources into the smart power grid through industrial electronics,’’ IEEE Ind. Electron. Mag., Vol. 4, No. 1, pp. 18-37, 2010.

[7] Y. Zhao, X. Xiang, C. Li, Y. Gu, W. Li, and X. He, “Single-phase high step-up converter with improved multiplier cell suitable for half-bridge-based PV inverter system,” IEEE Trans. Power Electron., Vol. 29, No. 6, pp. 2807-2816, Jun. 2014.

[8] M. H. Todorovic, L. Palma, and P. N. Enjeti, “Design of a wide input range dc–dc converter with a robust power control scheme suitable for fuel cell power conversion,” IEEE Trans. Ind. Electron., Vol. 55, No. 3, pp. 1247-1255, Mar. 2008.

[9] L. S. Yang, T. J. Liang, and J. F. Chen, “Transformer-less dc–dc converter with high step-up voltage gain,” IEEE Trans. Ind. Electron., Vol. 56, No. 8, pp. 3144-3152, Aug. 2009.

[10] Yan Zhang, Jinjun Liu, Zhuo Dong, “Dynamic Performance Improvement of Diode–capacitor-Based High Step-up DC–DC Converter Through Right-Half-Plane Zero Elimination,” IEEE Trans. Power Electron., Vol. 32, No. 8, pp. 6532-6543, Aug. 2016.

[11] R. J. Wai, C. Y. Lin, C. Y. Lin, R. Y. Duan, and Y. R. Chang, “High efficiency power conversion system for kilowatt- level stand-alone generation unit with low input voltage,” IEEE Trans. Ind. Electron., Vol. 55, No. 10, pp. 3702-3714, Oct. 2008.

[12] S.-K. Changchien, T.-J. Liang, J.-F. Chen, and L.-S. Yang, “Novel high step-up DC–DC converter for fuel cell energy conversion system,” IEEE Trans. Ind. Electron., Vol. 57, No. 6, pp. 2007-2017, Jun. 2010.

[13] N. P. Papanikolaou and E. C. Tatakis, “Active voltage clamp in flyback converters operating in CCM mode under wide load variation,” IEE Trans. Ind. Electron., Vol. 51, No. 3, pp. 632-640, Jun. 2004.

[14] S. Chen, T. Liang, L. Yang, and J. Chen, “A cascaded high step-up dc–dc converter with single switch for microsource applications,” IEEE Trans. Power Electron., Vol. 26, No. 4, pp. 1146-1153, Apr. 2011.

[15] S. V., J. P. F., and Y. L., “Optimization and design of a cascaded DC/DC converter devoted to grid-connected photovoltaic systems,” IEEE Trans. Power Electron., Vol. 27, No. 4, pp. 2018-2027, Apr. 2012.

[16] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Switched- capacitor/switched-inductor structures for getting transformerless hybrid DC–DC PWM converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 55, No. 2, pp. 687-696, Mar. 2008.

[17] F. Zhang, L. Du, F. Z. Peng, and Z. Qian, “A new design method for high power high-efficiency switched-capacitor DC–DC converters,” IEEE Trans. Power Electron., Vol. 23, No. 2, pp. 832-840, Mar. 2008.

[18] F. L. Luo and H. Ye, “Positive output multiple-lift push–pull switched capacitor Luo-converters,” IEEE Trans. Ind. Electron., Vol. 51, No. 3, pp. 594-602, Jun. 2004.

[19] M. Zhu and F. L. Luo, “Voltage-lift-type cuk converters: Topology and analysis,” IET Power Electron., Vol. 2, No. 2, pp. 178-191, Mar. 2009.

[20] J. K. Kim and G. W. Moon, “Derivation, analysis, and comparison of nonisolated single-switch high step-up converters with low voltage stress,” IEEE Trans. Power Electron., Vol. 30, No. 3, pp. 1336-1344, Mar. 2015.

[21] L. S. Yang, T. J. Liang, H. C. Lee, and J. F. Chen, “Novel high step-up DC–DC converter with coupled-inductor and voltage-doubler circuits,” IEEE Trans. Ind. Electron., Vol. 58, No. 9, pp. 4196-4206, Sep. 2011.

[22] F. S. F. Silva, A. A. A Freitas, S. Daher, S. C. Ximenes, S. K. A. Sousa, M. S. Edilson, F. L. M. Antunes, and C. M. T. Cruz, “High gain DC-DC boost converter with a coupling inductor,” Power Electronics Conference. IEEE, pp. 486- 492, 2009.

[23] X. F. Hu and C. Y. Gong, “A high voltage gain DC–DC converter integrating coupled-inductor and diode-capacitor techniques,” IEEE Trans. Power Electron., Vol. 29, No. 2, pp. 789-800, Feb. 2014.

[24] Y. Zhao, W. Li, Y. Deng, and X. He, “High step-up boost converter with passive lossless clamp circuit for non- isolated high step-up applications,” IET Trans. Power Electron., Vol. 4, No. 8, pp. 851-859, Sep. 2011.

[25] X. F. Hu and C. Y. Gong, “A high gain input-parallel output-series DC/DC converter with dual coupled inductors,” IEEE Trans. Power Electron., Vol. 30, No. 3, pp. 1306-1316, Mar. 2015.

[26] B. Axelrod, Y. Beck, and Y. Berkovich, “High step-up DC–DC converter based on the switched-coupled-inductor boost converter and diode-capacitor multiplier: Steady state and dynamics,” IET Power Electron., Vol. 8, No. 8, pp. 1420-1428, Feb. 2015.

[27] X. F. Hu, J. Z. Wang, L. P. Li, and Y. C. Li, “A three- winding coupled-inductor DC–DC converter topology with high voltage gain and reduced switch stress,” IEEE Trans. Power Electron., Vol. 33, No. 2, pp. 1453-1462, Feb. 2018.

[28] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, “Novel high step-up DC-DC converter for distributed generation system,” IEEE Trans. Ind. Electron., Vol. 60, No. 4, pp. 1473-1482, Apr. 2013.

[29] X. F. Hu, L. P. Li and Y. C. Li, and G. Wu, “Input-parallel output-series DC–DC converter for non-isolated high step-up applications,” Electron. Lett., Vol. 52, No. 20, pp. 1715-1717, 2016.

[30] S. M. Chen, T. J. Liang, L. S. Yang, “A boost converter with capacitor multiplier and coupled Inductor for AC module applications,” IEEE Trans. Ind. Electron., Vol. 60, No. 4, pp. 1503-1511, Apr. 2013.

[31] X. F. Hu, G. R. Dai, L. Wang, and C. Gong, “A three-state switching boost converter mixed with magnetic coupling and voltage multiplier techniques for high gain conversion,” IEEE Trans. Power Electron., Vol. 31, No. 4, pp. 2991- 3001, Apr. 2016.

[32] X. F. Hu, M. Zhang, Y. Li, L. Li, and G. Wu, “A ripple- free input current interleaved converter with dual coupled inductors for high step-up applications,” J. Power Electron., Vol. 17, No. 3, pp. 590-600, May 2017.

[33] H. C. Liu, L. C. Wang, F. Li, and Y. Ji, “Bidirectional active clamp DC–DC converter with high conversion ratio,” Electron. Lett., Vol. 53 , No. 22, pp. 1483-1485, 2017.

[34] Y. M. Ye, K. W. E. Cheng, S. Z. Chen, “A high step-up PWM DC-DC converter with coupled-inductor and resonant switched-capacitor,” IEEE Trans. Power Electron., Vol. 32, No. 10, pp. 7739-7749, Oct. 2017.

[35] F. Yang and X. Ruan, “Discontinuous-current mode operation of a two-phase interleaved boost DC–DC converter with coupled inductor,” IEEE Trans. Power Electron. Vol. 33, No. 1, pp. 188-198, Jan. 2018.

[36] G. P. Chen, L. Chen, Y. Deng, X. He, Y. Wang,  J. Zhang, “Single coupled-inductor dual output soft-switching DC–DC converters with improved cross-regulation and reduced components,” IET Power Electron., Vol. 10 , No. 13, pp. 1665-1678, Nov. 2017.

[37] X. Zhang, W. Qian, and Z. Li, “Design and analysis of a novel ZVZCT boost converter with coupling effect,” IEEE Trans. Power Electron., Vol. 32, No. 12, pp. 8992-9000, Dec. 2017.



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Xuefeng Hu was born in Jiangsu Province, China. He received his M.S. degree in Electronic Engineering from the China University of Mining and Technology, Xuzhou, China, in 2001; and his Ph.D. degree in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2014. He is presently working as a Professor in the Anhui Key Laboratory of Power Electronics and Motion Control Technology, College of Electronic Engineering, Anhui University of Technology, Ma'anshan, China. He is the author or coauthor of more than 30 technical papers. His current research interests include renewable energy systems, dc-dc power conversion, the modeling and control of converters, flexible ac transmission systems and distributed power systems.


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Benbao Gao was born in Anhui, China, in 1994. He received his B.S. degree from the Anhui Normal University, Wuhu, China, in 2016. He is presently working towards his M.S. degree in the College of Electrical Engineering, Anhui University of Technology, Ma’anshan, China. His current research interests include power electronics, distributed power systems, and solar and wind power generation.


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Yuanyuan Huang was born in Anhui, China, in 1992. She received her B.S. degree from the Anhui Polytechnic University, Wuhu, China, in 2015. She is presently working towards her M.S. degree in the College of Electrical Engineering, Anhui University of Technology, Ma’anshan, China. Her current research interests include power electronics, dc-dc power conversion, distributed power systems, and solar and wind power generation.


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Hao Chen was born in Anhui, China, in 1991. He received his B.S. degree from the Hefei Normal University, Hefei, China, in 2015. He is presently working towards his M.S. degree in the College of Electrical Engineering, Anhui University of Technology, Ma’anshan, China. His current research interests include power electronics, distributed power systems, and solar and wind power generation.