사각형입니다.

https://doi.org/10.6113/JPE.2018.18.3.672

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Analysis and Optimization of Bidirectional Exponential SC Power Conversion Circuits


Yuanmao Ye, Wei Peng*, Bijia Jiang*, and Xianyong Zhang**


†,*School of Automation, Guangdong University of Technology, Guangzhou, China

**College of Automation, Guangdong Polytechnic Normal University, Guangzhou, China



Abstract

A bidirectional exponential-gain switched-capacitor (SC) DC-DC converter is developed in this paper. When compared with existing exponential SC converters, the number of switches is significantly reduced and its structure is simplified. The voltage transfer features, voltage ripple across capacitors, efficiency and output impedance of the proposed converter are analyzed in detail. Optimization of the output impedance is also discussed and the best type of capacitance distribution is determined. A common function of the voltage gain to the output impedance is found among the proposed converter and other popular SC voltage multipliers. Experimental evaluation is carried out with a 6-24V bidirectional prototype converter.


Key words: DC-DC converters, High voltage gain, Output impedance, Switched capacitor


Manuscript received Sep. 13, 2017; accepted Jan. 9, 2018

Recommended for publication by Associate Editor Chun-An Cheng.

Corresponding Author: eeyeym@gdut.edu.cn Tel: +86-15914689420, Guangdong Univ. of Tech.

*School of Automation, Guangdong University of Technology, China

**College of Automation, Guangdong Polytechnic Normal University, China



Ⅰ. INTRODUCTION

Due to the advantages of the absence of bulky magnetic components and IC compatibility, switched-capacitor (SC) power converters have been recieving a lot of attention from researchers [1]-[22]. The authors of [2]-[7] presented the analysis, design, regulation and control of SC converters in detail, while various modeling methods have been introduced in [8]-[10]. In particular, two-phase SC converters, also known as voltage multipliers [11]-[14], have been widely used in different applications such as flash memory devices, biomedical systems, LCD drivers, etc. [15]-[17]. The most popular SC power converters include the series-parallel (SP) [18], Dickson [13], Fibonacci [19] and exponential-gain SC converters [20], [21].

In this paper, a new exponential-gain SC converter is developed by cascading multiple double-mode switched- capacitor (DMSC) cells. When compared with the existing exponential-gain SC converter shown in Fig. 1, the proposed converter has the advantages of a reduced number of switches and a simple circuit configuration. The voltage transfer features and voltage ripples across the capacitors as well as the power conversion efficiency are analyzed using Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL). The output impedance is also derived in the two cases where the parasitic resistances are considered and ignored.


그림입니다.
원본 그림의 이름: image1.emf
원본 그림의 크기: 가로 644pixel, 세로 522pixel

Fig. 1. Conventional exponential-gain SC converter.


For practical applications, the size and cost of a SC converter is dominated by the total capacitance C and the number of switches. The output impedance is directly related to the total capacitance C and the switching frequency of the SC converter. However, with the difference distribution manner of the total capacitance, the output impedance is varied. In this paper, the effect of the capacitance distribution on the output impedance is discussed, and an optimized capacitance distribution method is developed for the minimum output impedance. This optimized method is further extended to the aforementioned high order SC converters. Compared with other studies, the proposed SC converter has the advantage of a simpler structure.

Based on the theoretical analysis, a 6-24V bidirectional prototype converter is built to evaluate the performance of the proposed exponential-gain converter.



Ⅱ. BIDIRECTIONAL EXPONENTIAL-GAIN SC CONVERTER


A. Circuit Configuration

Fig. 2 shows the proposed bidirectional exponential-gain SC converter. Fig. 2(a) shows the topology which is cascaded by multiple DMSC cells. Each DMSC cell is made up of four transistors and two flying capacitors. VL and VH represent the low and high voltage terminals, respectively. As indicated in Fig. 2(b), there are two clock phases, Φa and Φb, when the switch will be closed. The two phases are fully complementary and equally divide a switching cycle. In practice, a small dead-time is required between the two phases.


Fig. 2. Proposed bidirectional exponential-gain SC converter: (a) Topology; (b) Time slots.

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원본 그림의 이름: image2.emf
원본 그림의 크기: 가로 663pixel, 세로 260pixel

(a)

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원본 그림의 이름: image3.emf
원본 그림의 크기: 가로 377pixel, 세로 133pixel

(b)


B. No-Load Analysis

For sake of convenience, it is assumed that all of the components are ideal, i.e. there is no on-resistance for the switches, and the equivalent series resistance (ESR) for the capacitors are made for the following analysis.


Fig. 3. State circuits of the proposed SC converter: (a) Phase Φa; (b) Phase Φb.

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원본 그림의 이름: image4.emf
원본 그림의 크기: 가로 488pixel, 세로 209pixel

(a)

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원본 그림의 이름: image5.emf
원본 그림의 크기: 가로 486pixel, 세로 209pixel

(b)


Fig. 3 gives the two alternate state circuits for the proposed SC converter. For the clock phase Φa, the positive electrodes of VL, VH and Ci1 (i=1, 2, …, n) are connected together as shown in Fig.3(a). By using the KVL for the whole state circuit, the KVL equation can be obtained as:

Phase Φa: 그림입니다.
원본 그림의 이름: CLP000020b00024.bmp
원본 그림의 크기: 가로 898pixel, 세로 363pixel     (1)

For the clock phase Φb, as shown in Fig.3(b), the negative electrodes of VL, VH and Ci2 (i=1, 2, …, n) are connected together. Similarly, the KVL equation can be obtained as:

Phase Φb: 그림입니다.
원본 그림의 이름: CLP000020b00025.bmp
원본 그림의 크기: 가로 900pixel, 세로 365pixel     (2)

According to equations (1) and (2), the ideal voltage transfer relationship for the proposed SC converter can be derived and is given in:

그림입니다.
원본 그림의 이름: CLP000020b00026.bmp
원본 그림의 크기: 가로 1142pixel, 세로 310pixel      (3)


C. With-Load Analysis

When one terminal (VL or VH) of the proposed converter is used as an input terminal and the other one is connected with a load, current flows form the input terminal to the output node through all of the DMSC cells. Each capacitor operates alternatively in the charging and discharging states during each switching cycle. Considering the on-resistance of the switches and the ESR of the capacitors, state circuits of the proposed exponential-gain SC converter are depicted in Figs. 4(a) and 4(b) for phases Φa and Φb, respectively. Rk1 and Rk2 (k=1, 2, …, n) are the ESR of Ck1 and Ck2, and the on-resistances of the corresponding switches are regarded as a part of them.


Fig. 4. State circuits with parasitic resistances: (a) Phase Φa; (b) Phase Φb.

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원본 그림의 이름: image6.emf
원본 그림의 크기: 가로 788pixel, 세로 326pixel

(a)

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원본 그림의 이름: image7.emf
원본 그림의 크기: 가로 789pixel, 세로 343pixel

(b)


When VL is the input terminal and VH is the output terminal, the SC converter operates in the step-up mode and all of the currents denoted in Figs. 4(a) and 4(b) are positive, and vice-versa. By using the KCL for the state circuits, the KCL equations can be obtained as:

Phase Φa: 그림입니다.
원본 그림의 이름: CLP000020b00027.bmp
원본 그림의 크기: 가로 878pixel, 세로 356pixel   (4)

Phase Φb: 그림입니다.
원본 그림의 이름: CLP000020b00028.bmp
원본 그림의 크기: 가로 879pixel, 세로 355pixel   (5)

In the stable state, the amount of charge flowing into and out of each capacitor should be the same during one switching cycle. Based on the assumptions that the two capacitors employed in each cell are the same and that both are represented by Ck, i.e. Ck1=Ck2=Ck, the relationship of charge flowing into/out of all of the capacitors and through the two terminals can be derived from (4) and (5), which is expressed as:

그림입니다.
원본 그림의 이름: CLP000020b00029.bmp
원본 그림의 크기: 가로 1019pixel, 세로 364pixel          (6)

where △QL and △Q H are the charge flowing through the terminals VL and VH, respectively. In addition, △Qk (k=1, 2, …, n) is the amount of charge transferred into/out of the capacitor Ck, during one switching cycle.

The voltage ripples across the capacitors can be derived from equation (6) and is expressed by:

그림입니다.
원본 그림의 이름: CLP000020b0002a.bmp
원본 그림의 크기: 가로 1258pixel, 세로 385pixel           (7)

where fS is the switching frequency of the converter. In addition, IL and IH are the average currents flowing through the terminals VL and VH, respectively.

Additionally, the power conversion efficiency of the proposed converter can be expressed by using the input energy and output energy during one switching cycle. Therefore, according to (6), the efficiency of the SC converter can be expressed as:

Step-up mode: 그림입니다.
원본 그림의 이름: CLP000020b0002b.bmp
원본 그림의 크기: 가로 612pixel, 세로 183pixel          (8)

Step-down mode: 그림입니다.
원본 그림의 이름: CLP000020b0002c.bmp
원본 그림의 크기: 가로 631pixel, 세로 204pixel       (9)



Ⅲ. MODELING OF THE PROPOSED SC CONVERTER


A. Modeling of a Single DMSC Cell

All of the DMSC cells employed in the proposed converter are made up of two symmetrical phases. There are the same average voltage and ripple, and inverse operation for the two capacitors Ck1 and Ck2. During phase Φa, the voltage across Ck1 increases from VCk_min to VCk_max, while the voltage across Ck2 decreases from VCk_max to VCk_min. On the other hand, the voltage across Ck1 decreases from VCk_max to VCk_min, while the voltage across Ck2 increases from VCk_min to VCk_max during the period of phase Φb. For the two operation stages, the sum voltage Vk=VCk1+VCk2 is almost constant and its ripple is far smaller than that for each of the capacitors and can be neglected. The two states can be generally depicted by Fig. 5(a).


Fig. 5. Single DMSC cell: (a) State circuit; (b) Model.

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원본 그림의 이름: image12.emf
원본 그림의 크기: 가로 469pixel, 세로 245pixel

(a)

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원본 그림의 이름: image13.emf
원본 그림의 크기: 가로 390pixel, 세로 184pixel

(b)


Based on the above analysis, the input and output voltages of the DMSC cell, Vk-1 and Vk, can both be regarded as constant. The operation of the DMSC cell, during half of a switching cycle can be mathematically described as:

그림입니다.
원본 그림의 이름: CLP000020b0002d.bmp
원본 그림의 크기: 가로 1388pixel, 세로 406pixel        (10)

그림입니다.
원본 그림의 이름: CLP000020b0002e.bmp
원본 그림의 크기: 가로 1397pixel, 세로 414pixel       (11)

where ik_cr and ik_dr represent the charging and discharging currents of the capacitors, respectively. Both of them have the same average value Ik since the two phases Φa and Φb are fully complementary and evenly divide a switching cycle. Therefore, the voltage transfer relationship can be derived as:

그림입니다.
원본 그림의 이름: CLP000020b0002f.bmp
원본 그림의 크기: 가로 940pixel, 세로 315pixel    (12)

where fS is the switching frequency. In addition, Ik is the average value of both the charging and discharging currents, ik_cr and ik_dr, and it is the output average current of the DMSC cell.

Therefore, the output impedance of a single DMSC cell for the step-up mode is expressed by:

Step-up mode: 그림입니다.
원본 그림의 이름: CLP000020b00030.bmp
원본 그림의 크기: 가로 745pixel, 세로 309pixel     (13)

Similarly, the output impedance for the step-down mode can be derived as:

Step-down mode: 그림입니다.
원본 그림의 이름: CLP000020b00032.bmp
원본 그림의 크기: 가로 783pixel, 세로 323pixel           (14)

An equivalent model of the single DMSC cell in the proposed converter for bidirectional operation can be generally described as shown in Fig. 5(b).


B. Modeling of the Proposed SC Converter

Considering that the proposed SC converter is cascaded by multiple DMSC cells, the model of the proposed converter can also be developed as shown in the upper half of Fig. 6.


그림입니다.
원본 그림의 이름: image17.emf
원본 그림의 크기: 가로 684pixel, 세로 375pixel

Fig. 6. Model of the proposed converter.


For the step-up operation, the terminal VL is used as the input terminal and the load is connected to the terminal VH.

The voltage transfer relationship can be derived from (12), and is given as:

그림입니다.
원본 그림의 이름: CLP000020b00033.bmp
원본 그림의 크기: 가로 1300pixel, 세로 428pixel     (15)

where Ik and ROk (k=1, 2, …, n) are the average output current and output impedance for each of the SC cells, respectively. In addition, Vn and In are the actual output voltage and current of the proposed converter in the step-up operation. An equivalent model of the proposed converter for the step-up mode can be further developed as shown in the lower half of Fig. 6, and the voltage transfer relationship is developed as:

그림입니다.
원본 그림의 이름: CLP000020b00034.bmp
원본 그림의 크기: 가로 842pixel, 세로 212pixel      (16)

This means the output impedance of the whole SC converter can be expressed as:

그림입니다.
원본 그림의 이름: CLP000020b00035.bmp
원본 그림의 크기: 가로 1350pixel, 세로 329pixel   (17)

Similarly, when VH is used as the input terminal, the voltage transfer relationship and the output impedance for the step-down mode can be developed, and they are given as:

그림입니다.
원본 그림의 이름: CLP000020b00036.bmp
원본 그림의 크기: 가로 908pixel, 세로 171pixel          (18)

그림입니다.
원본 그림의 이름: CLP000020b00037.bmp
원본 그림의 크기: 가로 1326pixel, 세로 333pixel     (19)

In the case of ignoring the impact of the parasitic resistors, the output impedance of (17) and (19) can be simplified as:

그림입니다.
원본 그림의 이름: CLP000020b00038.bmp
원본 그림의 크기: 가로 602pixel, 세로 189pixel    (20)

그림입니다.
원본 그림의 이름: CLP000020b00039.bmp
원본 그림의 크기: 가로 630pixel, 세로 208pixel    (21)

By comparing (17) with (19), (20) and (21), the relationship between the output impedances of both the step-up and step-down operation modes can be expressed as:

그림입니다.
원본 그림의 이름: CLP000020b0003a.bmp
원본 그림의 크기: 가로 490pixel, 세로 178pixel         (22)

Hence, the mode of Fig. 6 can be applied for both the step-up and step-down operation modes of the proposed bidirectional SC converter.



Ⅳ. OPTIMIZATION OF THE OUTPUT IMPEDANCE


A. Impact of the Capacitance Distribution

It can be seen from (20) and (21) that larger capacitances are required for a smaller output impedance. However, in practice, the values of the capacitors cannot be infinitely large and a larger capacitance means a higher cost and a larger size. For the proposed converter, although the two capacitors Ck1 and Ck2 employed in each of the DMSC cells need to be the same, i.e. Ck1=Ck2=Ck, the capacitors for different cells may be varied. Therefore, the method to allocate the total capacitance C to all of the capacitors for the minimum output impedance is a topic that should be explored.

When the total capacitance C is evenly distributed to all of the DMSC cells, the value of each capacitor is Ck=C/2n. According to (7), the voltage ripple across Ck is decreased exponentially, and is given as:

그림입니다.
원본 그림의 이름: CLP000020b0003b.bmp
원본 그림의 크기: 가로 438pixel, 세로 76pixel           (23)

Ignoring the impact of the parasitic resistances, the output impedance for the step-up mode can be calculated according to (20), and is given as:

그림입니다.
원본 그림의 이름: CLP000020b0003c.bmp
원본 그림의 크기: 가로 418pixel, 세로 169pixel    (24)


B. Minimum Output Impedance

In order to obtain the minimum output impedance for the constant total capacitance C, C1 is described as C1=C/2-C2-…-Ck-…-Cn. Substituting this into (20) and letting the partials with respect to the capacitance Ck equal to zero, i.e.

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원본 그림의 이름: CLP000020b0003d.bmp
원본 그림의 크기: 가로 1287pixel, 세로 152pixel    (25)

As a result, the capacitance Ck can be expressed as:

그림입니다.
원본 그림의 이름: CLP000020b0003e.bmp
원본 그림의 크기: 가로 347pixel, 세로 95pixel   (26)

Considering that the total capacitance is C and k is ranged from 1 to n, the capacitance Ck can be further expressed by:

그림입니다.
원본 그림의 이름: CLP000020b0003f.bmp
원본 그림의 크기: 가로 396pixel, 세로 175pixel   (27)

Then the minimum output impedance can be obtained by substituting (27) into (20), and is given as:

그림입니다.
원본 그림의 이름: CLP000020b00040.bmp
원본 그림의 크기: 가로 442pixel, 세로 184pixel          (28)

The analysis above is mainly discussed for the step-up operation mode of the proposed converter. Similarly, according to (22), the minimum output impedance for the step-down operation mode is obtained in the same case.



Ⅴ. COMPARISON WITH OTHER WORKS

In practice, the size and cost of a SC converter is dominated by the total capacitance C and the number of switches. As mentioned before, a smaller output impedance means a higher power efficiency. With the assumption that all of the parasitic resistances are ignored, the output impedance of a SC converter is determined by the switching frequency, the total capacitance C and the capacitance distribution. For different high order SC converters like the SP, Dickson and Fibonacci, there are different capacitance distribution laws for their minimum output impedances.

Table I lists the characteristics of the proposed and other high order SC converters with n stages. These characteristics include the voltage gain m, the best capacitance distribution law, the number of switches, the minimum output impedance and the relationship between the minimum output impedance and the voltage gain. This shows there are the same voltage gains and the same best capacitance distribution law as well as the same minimum output impedance for both the SP and Dickson converters. Common characteristics are also found in both the conventional and proposed exponential-gain SC converters. However, the number of switches required in the Dickson and the proposed converters is far less than that for the SP and conventional exponential-gain converters.

A noticeable characteristic is that there is a common relationship between the minimum output impedance and the voltage gain for all of the high order SC converters listed in Table I. This means that with the same total capacitance C and switching frequency fS, using different topologies to obtain the same voltage gain, the same output impedance and power conversion efficiency ca be developed. The more intuitive relationship is depicted in Fig. 7.


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원본 그림의 크기: 가로 1384pixel, 세로 930pixel

Fig. 7. Output impedance versus the voltage gain when fSC=1(Hz×F).


Additionally, the number of switches required for different DC converters is listed in the fourth column of Table I. In addition, the relationships between the number of switches and the voltage gain are depicted in Fig. 8. This figure shows that the minimum and maximum numbers of switches are required in the proposed exponential-gain and SP converters, for the same voltage gain.


TABLE I CHARACTERISTICS OF DIFFERENT TWO-PHASE SC CONVERTERS

Types of converters

Gain m

Cap. distribution

No. of switch

Output impedance

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원본 그림의 크기: 가로 245pixel, 세로 66pixel

SP

 

n+1

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원본 그림의 이름: CLP000020b00041.bmp
원본 그림의 크기: 가로 184pixel, 세로 132pixel

3n+1

그림입니다.
원본 그림의 이름: CLP000020b00044.bmp
원본 그림의 크기: 가로 137pixel, 세로 166pixel

그림입니다.
원본 그림의 이름: CLP000020b00048.bmp
원본 그림의 크기: 가로 188pixel, 세로 146pixel

Dick.

n+5

Fib.

Fn+1

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원본 그림의 이름: CLP000020b00042.bmp
원본 그림의 크기: 가로 268pixel, 세로 131pixel

3n+1

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원본 그림의 이름: CLP000020b00045.bmp
원본 그림의 크기: 가로 259pixel, 세로 153pixel

Fig.1 

 

2n

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원본 그림의 크기: 가로 289pixel, 세로 140pixel

6n+2

그림입니다.
원본 그림의 이름: CLP000020b00046.bmp
원본 그림의 크기: 가로 206pixel, 세로 155pixel

Fig.2

4n


그림입니다.
원본 그림의 이름: CLP000020b00049.bmp
원본 그림의 크기: 가로 1346pixel, 세로 969pixel

Fig. 8. Number of switches as function of the voltage gain.


Overall, the proposed SC converter is more suitable for high-voltage-gain applications. However, its flexibility is inferior to the Dickson SC converter.



Ⅵ. EXPERIMENTAL RESULTS

In order to analyze the properties of the proposed exponential-gain SC converter, a 6-24V bidirectional prototype has been built by cascading two DMSC cells, as shown in Fig. 9. Eight MOSFETs with on-resistances of 11mΩ are selected for the switches. In the first DMSC cell, both of the capacitors C11 or C12 are made up of two 1000uF/55mΩ electrolytic capacitors connected in parallel. The capacitors C21 and C22 in the second DMSC cell are both single 1000uF/55mΩ electrolytic capacitors. Additionally, a 1000uF electrolytic capacitor is used in the low voltage terminal as a filter. The controller is developed by IR2153 and the isolated gate driver is completed based on pulse transformers. In order to reduce the effect of the ESL and switching losses, the prototype works at a 10 kHz switching frequency. To improve the power density, the isolated pulse transformer driver can be replaced by an optocoupler or another floating gate driver. In addition, ceramic capacitors and a higher switching frequency can be used in practical industrial applications.

그림입니다.
원본 그림의 이름: image41.emf
원본 그림의 크기: 가로 439pixel, 세로 254pixel

Fig. 9. Prototype of a 6-24V bidirectional converter.


When the low voltage terminal of the prototype circuit is connected with a 6V voltage source and the high voltage terminal is connected to an electronic load with constant output current IO=1A, the currents flowing through the capacitors as well as the power source current Iin are captured as shown in Fig. 10(a). Similarly, when the high voltage terminal of the prototype circuit is connected with a 24V voltage source and the low voltage terminal is connected to an electronic load with a constant current 4A, the current waveforms are shown in Fig. 10(b). It can be seen that the average charging and discharging currents are about 2A for C11 and C12, and about 1A for C21 and C22. The average current of the low voltage terminal is almost four times that in the high voltage terminal.


Fig. 10. Current waveforms of the prototype converter: (a) Step-up operation; (b) Step-down operation.

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원본 그림의 이름: image42.emf
원본 그림의 크기: 가로 665pixel, 세로 613pixel

(a)

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원본 그림의 이름: image42.emf
원본 그림의 크기: 가로 665pixel, 세로 613pixel

(b)


As mentioned in (16) and (18), increasing the output current decreases the output voltage. For the bidirectional prototype converter, the load regulations for the step-up and step-down operations are measured as shown in Figs. 11(a) and 11(b), respectively. The output voltage falls from 23.85V when the output current is 0.2A to 22.09V when the output current increases to 3A for the step-up operation. Similarly, it decreases from 5.96V to 5.58V when the output current rises from 1A to 13A, for the step-down operation. The practical output impedances of the prototype converter are 0.64Ω for the step-up mode and 33mΩ for the step-down mode, which are slightly larger than the theoretical values of 0.51Ω and 31mΩ, respectively.


Fig. 11. Output voltage versus output current: (a) Step-up operation (6V to 24V); (b) Step-down operation (24V to 6V).

그림입니다.
원본 그림의 이름: CLP000020b0004b.bmp
원본 그림의 크기: 가로 1471pixel, 세로 702pixel

(a)

그림입니다.
원본 그림의 이름: CLP000020b0004c.bmp
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(b)


Fig. 12 shows output voltage transient waveforms of the prototype operating in the step-up mode when the output current changes between 1A and 2A. As mentioned before, the voltage drop caused by the output impedance of the converter reduces the output voltage while a higher output current means a lower output voltage.


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Fig. 12. Output voltage transient waveform of the prototype versus the output current.


Fig. 13 shows the efficiency of the bidirectional prototype converter with different output powers. This indicated that there is almost the same power conversion efficiency for both the step-up and step-down operation modes under the same output power. In addition, the maximum efficiencies for the step-up and step-down operations are 95.5% and 95.3%, respectively. Both of them are achieved at round 30W output power.


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Fig. 13. Measured efficiency of the prototype converter.



Ⅶ. CONCLUSIONS

A new exponential-gain DC-DC converter for a bidirectional power flow is developed based on the SC technique. The voltage conversion characteristics and model are derived using the KVL and KCL principles for the proposed converter. The effect of the capacitance distribution on the output impedance is discussed. This indicates there is the same minimum output impedance between the proposed converter and other existing two-phase SC converters for the same voltage transfer ratio. Of course, there is a shortcoming in the proposed converter since the input and output terminals cannot share a common neutral. A two-stage prototype converter designed for a 6-24V bidirectional power flow was built based on the theoretical analysis. Experimental results support the theoretical analysis and the practical output impedance since the step-up and step-down operations are both just slightly larger than their theoretical values.



ACKNOWLEDGMENT

This work was supported in part by the Natural Science Foundation of Guangdong Province (No.2017A030313316), in part by the Science and Technology Planning Project of Guangdong Province (No.2017A010102013), and in part by the Guangdong University of Technology under Grant from the Financial and Education Department of Guangdong Province 2016[202]: Key Discipline Construction Program.



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Yuanmao Ye received his B.S. degree from University of Jinan, Jinan, China, in 2007; his M.S. degree from the South China University of Technology, Guangzhou, China, in 2010; and his Ph.D. degree from the Hong Kong Polytechnic University, Hong Kong, China, in 2016. From 2010 to 2014, he was a Researcher in the Department of Electrical Engineering, Hong Kong Polytechnic University. He is presently working as a Professor in the School of Automation, Guangdong University of Technology, Guangzhou, China. His current research interests include various dc-dc power converters, switched-capacitor techniques and their applications, multilevel inverters, power conversion and energy management for smart-grids, protection and control techniques for DC distribution, and wireless charging technique for EVs.


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Wei Peng was born in Hunan, China, in 1995. He received his B.S. degree from the Hunan University of Humanities, Science and Technology, Loudi, China, in 2017. He is presently working towards his M.S. degree at Guangdong University of Technology, Guangzhou, China. His current research interests include multilevel inverters, power converters and intelligent control.


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Bijia Jiang was born in Hunan, China, in 1994. She received her B.S. degree from the Hunan Institute of Engineering, Xiangtan, China, in 2013. She is presently working towards her M.S. degree at the Guangdong University of Technology, Guangzhou, China. Her current research interests include DC/DC converters and the control of DC microgrids.


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Xianyong Zhang received his B.S. degree from the Changchun University of Science and Technology, Changchun, China, in 1999; and his M.S. and Ph.D. degrees from the South China University of Technology, Guangzhou, China, in 2002 and 2007, respectively. From 2007 to 2014, he was with the Solar Power Generation and Microgrid Lab, Guangzhou Institute of Energy Conversion, Chinese Academy of Sciences, Guangzhou, China. He is presently working as an Associate Professor in the College of Automation, Guangdong Polytechnic Normal University, Guangzhou, China. His current research interests include the control and power electronics technology in renewable energy.