사각형입니다.

https://doi.org/10.6113/JPE.2019.19.1.34

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Input Voltage Range Extension Method for Half-Bridge LLC Converters by Using Magamp Auxiliary Post-Regulator


Xiaoguang Jin*, Huipin Lin*, Jun Xu**, and Zhengyu Lu


†,*College of Electrical Engineering, Zhejiang University, Hangzhou, China

**Shanghai Institute of Space Power-Sources, Shanghai, China



Abstract

An improved half-bridge LLC converter with a magamp auxiliary post-regulator is proposed in this paper. The function of the magamp is bypassed when the converter works within the low input-voltage range. Meanwhile, it operates as an auxiliary post-regulator when the input voltage is high. By changing the blocking time of the magamp, the dc gain of the converter can be extended. Hence, the input voltage range of the converter is extended. The realization of proposed topology does not require a complicated circuit. The controller of the magamp can be easily implemented using only passive components, transistors and an OP amp. The generalized operational principle is analyzed and the design criterion for the magamp is presented. Finally, a 25V output, 400W experimental prototype was built and tested for a 160–300V input-voltage range to verify the feasibility of the proposed method.


Key words: LLC converter, Magamp, Post-regulator, Resonance, Wide range


Manuscript received Apr. 28, 2018; accepted Oct. 16, 2018

Recommended for publication by Associate Editor Dukju Ahn.

Corresponding Author: eeluzy@zju.edu.cn Tel: +86- 571-87952707, Zhejiang University

*College of Electrical Engineering, Zhejiang University, China

**Shanghai Institute of Space Power-Sources, China



Ⅰ. INTRODUCTION

LLC series resonant converters are very popular these days in applications such as adapters, PC power supplies and energy storage systems due to its advantages of high efficiency, high power density and simplicity [1]-[4]. Pulse frequency modulation (PFM) is generally used to control LLC converters. Thus, a wide input-voltage range usually requires a wide switching frequency variation range. However, the slope of the gain curve is extremely flat when the converter operates above the resonant frequency f0, i.e., when the input voltage is high, the operating point moves far right away from f0. This leads to a significantly increment of the switching loss, and even the output-voltage of the converter may not be regulated to the demanded range. Therefore, a tradeoff between the frequency variation range and the input voltage range are usually made in the conventional LLC converter design process.

To extend the input-voltage range of an LLC converter, the methods proposed in previous literatures can be cataloged into three groups: 1) precise modeling and parameter optimizing [5]-[7]; 2) multi-stage conversion [8], [9]; 3) topology morphing [10]-[13].

In [5], an accurate LLC converter model is used to estimate the peak gain point, which is useful for wide input-voltage range designs. However, this does not fundamentally change the gain characteristics of an LLC converter. The topology proposed in [8] combines an LLC resonant converter with a boost converter. The LLC converter operates in a relatively narrow frequency range, while the boost converter works with a constant output-voltage. This topology is not conducive to improving the power density of the converter. In [10], the converter works as a full-bridge (FB) LLC converter in the low input-voltage range. Meanwhile, for the high input voltage range, it is changed to a half-bridge (HB) LLC converter. However, its output exhibits severe overshoots/ undershoots at the topology transition instants. The control method proposed in [11] improved the idea in [10] by maintaining a tight regulation of the output during transitions. However, it is not suitable for applications that require a fast feedback response due to its long transition period. The topology reported in [12] employed a bidirectional switch which can halve the input-voltage of the resonant tank when a low voltage gain is needed. However, there are six MOSFETs which increase the complexity and the cost of the circuit. The topology proposed in [13], integrates two half-bridges in series to construct a three-level LLC converter, which can double the input voltage range. However, a potential voltage unbalance on the input capacitors may occur due to the mismatch of the switching periods and/or transformer windings. Furthermore, there is no simple method specifically for HB LLC converters in the literatures.

In order to overcome the problems mentioned above, an input voltage range extension method for HB LLC converters is proposed in this paper using magamp auxiliary post- regulators. The magamp has been well investigated for use in multiple output converters, including LLC converters [14]. In multiple output applications, magamp is used to distribute the conduction time for different outputs. The energy transmission between the primary side and the secondary side is not completely blocked. Unlike [14], for the proposed single output LLC converter, the magamp is used to completely cut off the energy exchange between the primary and secondary sides to change the dc gain curve of the converter. In the low input voltage range, the converter works as a conventional HB LLC converter. In the high input voltage range, the output voltage of the converter can be regulated by changing the blocking time of the magamp with a fixed switching frequency.

This paper is organized as follows. Section II analyzes the operating principle of the proposed converter in detail. Section III presents the characteristics and design consideration of the proposed converter. In section IV, an experimental prototype is built and tested to verify the theoretical analysis. Finally, section V gives the conclusion.



Ⅱ. PROPOSED HB LLC CONVERTER WITH AUXILIARY MAGAMP POST-REGULATOR


A. Limitations of an LLC Converter in Wide Input-Voltage Range Applications

Traditional HB LLC converters usually change the switching frequency to regulate the output against input voltage changes. Frequency control is achieved by operating the switches with a constant duty cycle of approximately 0.5. A proper switching dead-time between the two switches is provided to achieve zero voltage switching (ZVS) [15]. The dc gain curve of an HB LLC converter according to fundamental harmonic approximation (FHA) is shown in Fig. 1. The converter is designed to work in the inductive region where the ZVS of the primary switches can be achieved over the entire input voltage condition. Since the input voltage of the converter is changed and the output current of the converter varies, the dc voltage gain value of the converter is changed. In order to meet the varied gain value, a conventional LLC converter can operate below or above the resonant frequency. As can be seen in Fig. 1, the dc gain increases as the frequency increases and the Q factor decreases, while the dc gain decreases when the frequency increases. The most efficient point occurs around the resonant frequency f0. When the switching frequency fs is lower than f0, the lower fs is, the larger the circulating current is. On the other hand, the switching losses increases as the frequency increases. When the switching frequency is above f0, the rectification diodes D1 and D2 at the secondary side lose the ZCS condition. To meet an optimal frequency, the LLC converter should be operated under a very small frequency range around f0, as illustrated in Fig. 1. On the other hand, a wide input voltage or load-current range requires a wide switching frequency range. In order to reduce the switching frequency variation range, a low K (denoted by h in some studies) [16], i.e., the inductor ratio (Lm /Lr), is typically used in the LLC converter design. However, the inductor Lm decreases as K becomes lower. Since a small Lm means an increase in the conduction loss, it is not beneficial to improve the efficiency of the converter.


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원본 그림의 크기: 가로 1328pixel, 세로 1007pixel

Fig. 1. DC Gain curve of a conventional HB LLC converter.


B. Proposed Topology Description

The proposed HB LLC converter with magamp auxiliary post-regulator (LLC-MAP) is illustrated in Fig. 2(a). When compared with the conventional HB LLC converter, the proposed topology adds two magamps (Sr1 and Sr2) in serial with the rectification diodes D1 and D2 respectively on the secondary side. Moreover, a switch SW and a frequency limiter are added to the feedback loop. The “on/off” status of SW is determined by the switching frequency fs and the upper frequency limit fmax. In practice, fmax is set slightly smaller than f0 to insure ZCS of D1 and D2. In the low input-voltage range, fs is lower than f0 and SW is gated off. Vo is regulated by changing fs the same as the conventional HB LLC converter. This state is called the variable-frequency mode (VF Mode). When the input-voltage increases, fs moves up accordingly to reduce the dc gain of the converter. Once fs meets the upper limit fmax, fs is restricted to the constant value fmax and SW turns on. Then Vo is regulated by the magamp regulator loop at a fixed-frequency as shown in Fig. 2(b). This state is called the magamp-regulation mode (MR Mode).


Fig. 2. Proposed topology: (a) LLC resonant converter with magamp post-regulator; (b) Conceptual control diagram of an LLC-MAP converter.

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(a)

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(b)


C. Operational Principle

As mentioned previously, the proposed LLC-MAP converter has different operational principle during different modes. In the VF mode, the magamps are equivalent to copper wires with very small impedances. The LLC-MAP converter has the same structure as a conventional HB LLC converter. The operational principle is also the same as that of a conventional HB LLC converter.

In the MR mode, as shown in the operational waveforms in Fig. 3, one switching cycle can be divided into eight stages. Equivalent circuits of the stages 1-4 are shown in Fig. 4. For convenience, the following assumptions should be made.


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원본 그림의 크기: 가로 984pixel, 세로 1039pixel

Fig. 3. Principle waveforms of an LLC-MAP converter in the MR mode.


Fig. 4. Equivalent circuits of the proposed LLC-MAP converter: (a) [t0-t1]; (b) [t1-t2]; (c) [t2-t3]; (d) [t3-t4].

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(a)

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(b)

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원본 그림의 크기: 가로 1341pixel, 세로 646pixel

(c)

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원본 그림의 크기: 가로 1345pixel, 세로 653pixel

(d)


1) The output capacitor Co is large enough to neglect the voltage ripple on Vo. Thus, Vo is assumed to be constant.

2) The parasitic capacitors of the primary switches and the junction capacitors of the secondary diodes are not shown in the circuit for the sake of simplicity.

Stage 1 [t0-t1] [see Fig. 4(a)]: Before 그림입니다.
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원본 그림의 크기: 가로 179pixel, 세로 301pixel, the body diode of S1 has conducted. The differential current between im and ir feeds the load through D2. At t=t0, S1 turns on under the ZVS condition. Due to forward biasing of D2, the voltage across Lm is clamped by (-nV0). Resonance occurs between Lr and Cr. The resonance frequency is 그림입니다.
원본 그림의 이름: CLP00000eec0004.bmp
원본 그림의 크기: 가로 427pixel, 세로 83pixel. When im is equal to ir at t1, D2 turns off under the ZCS condition.

Stage 2 [t1-t2] [see Fig. 4(b)]: Sr1 was reset in the previous switching cycle. At t=t1, a voltage (vTsec-Vo) appears across Sr1 and D1 in series. This is in the direction to drive the magamp core up towards the saturated state. There are only very small coercive current flows through Sr1. Thus, Sr1 is equivalent to an “opened” switch. In the meantime, Sr2 is reset by the voltage vTsec. On the primary side, resonance occurs between Cr and (Lm+Lr). The resonance frequency is 그림입니다.
원본 그림의 이름: CLP00000eec0005.bmp
원본 그림의 크기: 가로 600pixel, 세로 84pixel. This stage ends when Sr1 is saturated at t2.

In this stage, the resonant current only circulates through the resonant tank and S1, and there is almost no power transferred to the secondary side. Thus, this stage is named the blocking interval. The blocking time can be expressed as the following expression according to Faraday’s Law:

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where nSr그림입니다.
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Stage 3 [t2-t3] [see Fig. 4(c)]: At t2, Sr1 has been magnetized to the saturated state, and is equivalent to a “closed” switch. D1 is forward biased and the primary side of the transformer is clamped by nVo. Resonance occurs between Lr and Cr. The current ir increases rapidly with a sinusoidal wave type, while im increases linearly. The deference between ir and im is transfered to the secondary side. This stage is terminated at t2 when ir=im.

Stage 4 [t3-t4] [see Fig. 4(d)]: At t3, S1 is turned off. The parasitic capacitance of S1 is charged by the resonant current and the drain-source voltage of S1 increases. In the meantime, the parasitic capacitance of S2 is discharged until its body-diode conducts. Then the ZVS turning on condition for S2 can be achieved.

Due to symmetry, the operation stages 5-8 are the same as 1-4 except that the resonance is initiated by the storage energy in the resonant capacitor Cr.



Ⅲ. CHARACTERISTICS AND DESIGN CONSIDERATIONS


A. DC Voltage Gain

In this paper, the normalized input-to-output dc voltage gain of the LLC-MAP converter is defined as:

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원본 그림의 크기: 가로 279pixel, 세로 150pixel                   (2)

Since the proposed HB LLC converter should operate below or close to the limit frequency fmax in the VF mode, as shown in Fig. 2, the FHA approach can be used for the dc gain analysis of the converter. This means that only the fundamental component of the input square wave is effective for transferring energy to the output. At this state, the dc voltage gain of the LLC-MAP is the same as that of a conventional HB LLC converter as shown in Fig. 5(a).


Fig. 5. Voltage gain curves of: (a) Proposed LLC-MAP converter; (b) Comparison between the LLC-MAP converter and the conventional HB LLC converter.

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원본 그림의 이름: CLP0000103013a1.bmp
원본 그림의 크기: 가로 1276pixel, 세로 992pixel

(a)

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원본 그림의 크기: 가로 1244pixel, 세로 1028pixel

(b)


When the LLC-MAP converter works in the MR mode, the switching frequency is fixed at 그림입니다.
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원본 그림의 크기: 가로 330pixel, 세로 62pixel. It is obvious that M=1 if dB=0, and that M=0 if dB =1. Therefore, it is easy to understand that the output voltage is proportional to dB, and that the voltage gain can be continuously regulated to between 1 and 0 by varying dB between 0 and 1. Next, an accurate derivation of the dc gain is made for the MR mode. Because there are more high-order harmonics that cannot be neglected when the LLC-MAP converter works in the MR mode, the FHA method is not accurate enough. Hence, the steady-state method is employed in the following derivation process. In order to simplify the analysis in this section, normalized variables are used in the following expressions. Define the voltage, current, and frequency bases as:

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원본 그림의 크기: 가로 459pixel, 세로 273pixel                (3)

where the characteristic impedance of the converter is 그림입니다.
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In stage 1, the expressions of ir, im and vC can be normalized as:

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원본 그림의 크기: 가로 768pixel, 세로 440pixel           (4)

Where 그림입니다.
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In stage 2, the expressions of ir, im and vC can be normalized as:

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원본 그림의 크기: 가로 818pixel, 세로 478pixel        (5)

where 그림입니다.
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원본 그림의 크기: 가로 71pixel, 세로 63pixel is the initial phase angle in stage 2. Ir2 is the initial value of ir and im in stage 2.

In stage 3, the expression of ir, im and vC can be normalized as:

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원본 그림의 크기: 가로 796pixel, 세로 463pixel   (6)

where is the initial phase angle in stage 3. Ir3 and Im3 are the initial values of ir and im in stage 3.

For the sake of simplicity, stage 4, which is short enough, is neglected in the dc gain analysis. Each of the operating phases is limited by the boundary conditions at the connection and switching moments of their adjacent phases. The current flows through the inductor and the voltage across the capacitor should maintain continuity between the two stages. Thus, the continuity conditions can be expressed as:

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원본 그림의 크기: 가로 413pixel, 세로 610pixel                     (7)

For periodic operation, the ending values of ir and im in stage 3 should be opposite their initial values in stage 1 due to symmetry in a half cycle, as shown in Fig. 3. Thus, the symmetry conditions are given by:

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원본 그림의 크기: 가로 427pixel, 세로 195pixel                    (8)

Because there is a Vin/2 dc voltage bias on Cr for half-bridge converters, the symmetry condition of vC is:

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원본 그림의 크기: 가로 521pixel, 세로 137pixel               (9)

Only stage 1 and stage 3 are involved in the power delivery between the primary side and the secondary side in a half cycle. Thus, the normalized output power can be expressed as:

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원본 그림의 크기: 가로 1064pixel, 세로 150pixel    (10)

The output power can also be expressed as:

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원본 그림의 크기: 가로 431pixel, 세로 143pixel                           (11)

Substituting (11) into (10) yields:

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원본 그림의 크기: 가로 1023pixel, 세로 149pixel      (12)

Note that 그림입니다.
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원본 그림의 크기: 가로 484pixel, 세로 73pixel. Therefore, it is possible to obtain:

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원본 그림의 크기: 가로 525pixel, 세로 77pixel                         (13)

By combining (4)-(9), (12) and (13) after a proper manipulation, the following simplified constrain equations can be derived:

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원본 그림의 크기: 가로 1391pixel, 세로 926pixel    (14)

There are ten unknown variables (그림입니다.
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원본 그림의 크기: 가로 349pixel, 세로 60pixel, 그림입니다.
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원본 그림의 크기: 가로 349pixel, 세로 60pixel, M and dB) in the above function. Since (14) is a transcendental function, the results of M versus dB cannot be directly obtained. When m=7 and fs*=1, by numerically solving the distribution equation (14) with the fsolve(x) function in MATLAB, the characteristics of M versus dB can be depicted for different values of Q as shown in Fig. 5(a). As can be seen, when dB is zero, the converter works as a traditional HB LLC converter if the initial blocking time of the magamp is neglected. When dB is 1, there is no energy transferred to the load when the transformer works in the open state. The quality factor Q has a slight effect on the dc gain, and the dc gain is mainly determined by dB.

A comparison between the LLC-MAP converter in the MR mode and the conventional LLC converter is illustrated in Fig. 5(b). As can be seen, a much higher frequency is needed in the conventional LLC converter when the same dc gain is required. In addition, it is not sensitive to Q, the output load in other words, when the LLC-MAP converter works in the MR mode.


B. Design of the Magamp Auxiliary Post-Regulator

As shown in Fig. 6(a), a current reset circuit can be adopted for the magamp due to a reduced phase delay and no need for negative voltage power [17]. The blocking time of the magamp is regulated by means of its resetting current Irst, which is proportional to the error voltage vEA. As can be seen in Fig. 6(b), during [t5-t51], the magamp current ir decreases from zero to Irst almost linearly. The diode Dr1 conducts. Therefore, vSr=vTsec. When ir reaches Irst at t=t51, vSr decrease to zero exponentially. The decreasing transient interval is relatively short and can be neglected. The magamp inductor reset is finished at t=t51. The relationship between unsaturated inductance of the magamp 그림입니다.
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원본 그림의 크기: 가로 456pixel, 세로 183pixel                 (15)


Fig. 6. Operating principle of the magamp: (a) Resetting circuit of the magamp; (b) Key waveforms for the magamp regulator.

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(a)

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(b)


where, 그림입니다.
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원본 그림의 크기: 가로 638pixel, 세로 77pixel          (16)

i.e., 그림입니다.
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원본 그림의 크기: 가로 198pixel, 세로 62pixel in Fig. 6(b). It should be noted that, at the blocking interval, vSr=vTsec-Vo should be positive to ensure that the magamp core can reach saturation. The maximum 그림입니다.
원본 그림의 이름: CLP00000eec0030.bmp
원본 그림의 크기: 가로 53pixel, 세로 54pixel can be achieved when vSr=0. A proper magamp core can be selected according to its maximum blocking time and unsaturated inductance.


C. Design of the Feedback Controller

Small signal control block diagrams for the magamp post-regulator in the LLC-MAP converter are illustrated in Fig. 7, where the 그림입니다.
원본 그림의 이름: image52.png
원본 그림의 크기: 가로 163pixel, 세로 218pixel sign denotes the small-signal ac quantity, GR presents the reset circuit transfer function, GM presents the magnetic modulator transfer function, and GF presents the duty cycle to output the voltage transfer function.


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원본 그림의 이름: CLP00000eec0033.bmp
원본 그림의 크기: 가로 1358pixel, 세로 601pixel

Fig. 7. Control block diagram of the magamp post-regulator in the LLC-MAP converter.


According to the specific circuit in Fig. 6(a), by equating the ac perturbation quantities in the small-signal model, the gain of each of the blocks can be exacted as:

그림입니다.
원본 그림의 이름: CLP00000eec0034.bmp
원본 그림의 크기: 가로 764pixel, 세로 175pixel          (17)

그림입니다.
원본 그림의 이름: CLP00000eec0035.bmp
원본 그림의 크기: 가로 489pixel, 세로 173pixel                     (18)

그림입니다.
원본 그림의 이름: CLP00000eec0037.bmp
원본 그림의 크기: 가로 836pixel, 세로 168pixel         (19)

where, 그림입니다.
원본 그림의 이름: CLP00000eec0038.bmp
원본 그림의 크기: 가로 84pixel, 세로 71pixel is the inductance of the saturated magamp. The open loop transfer function of the magamp post-regulator can be expressed as:

그림입니다.
원본 그림의 이름: CLP00000eec0039.bmp
원본 그림의 크기: 가로 742pixel, 세로 156pixel            (20)

Given specific parameters, as shown in Fig. 8, a comparison of the open loop gain curves between the magamp loop and the LLC loop can be obtained by a mathematic tool. As can be seen, the two loops exhibit strong intersections. In other words, the magamp post-regulator can share a controller with the LLC loop. In practice, the compensator parameters need to be selected based on the worst case of the bandwidth.


그림입니다.
원본 그림의 이름: CLP00000eec0036.bmp
원본 그림의 크기: 가로 1499pixel, 세로 740pixel

Fig. 8. Comparison of the open loop gain curves between the magamp loop and the LLC loop.


D. Loss Analysis of the Magamp

As mentioned previously, the output diode turns off under the ZVS condition. The dead-time problem of the magamp is neglectable in the LLC converter [14]. In the VF mode, the reset current is zero and the magamp is equivalent to a short circuit. There is only the copper loss introduced into the converter. The power dissipated in the magamps can then be written as:

그림입니다.
원본 그림의 이름: CLP00000eec003a.bmp
원본 그림의 크기: 가로 513pixel, 세로 162pixel               (21)

where 그림입니다.
원본 그림의 이름: CLP00000eec003b.bmp
원본 그림의 크기: 가로 38pixel, 세로 49pixel is the wire resistivity, MLT is the mean length per turn of the winding, and AW is the size of the wire. Since the winding of the magamp is only a few turns, in the total loss, the copper loss accounts for no more than 0.3% in the experimental prototype.

In the MR mode, the core loss of the magamp should also be considered. It can be expressed as:

그림입니다.
원본 그림의 이름: CLP00000eec003c.bmp
원본 그림의 크기: 가로 635pixel, 세로 90pixel            (22)

where 그림입니다.
원본 그림의 이름: CLP00000eec003d.bmp
원본 그림의 크기: 가로 517pixel, 세로 75pixel, HR is the coercive force needed for the reset, AC is the core cross-sectional area, and lm is the length of the magnetic path. The core loss data in W/kg as a function of the flux density and the frequency can also be found in datasheets in the form of a table or an equation. After giving the specific parameters of the prototype, the loss reaches the maximum proportion, which is about 0.9% at the maximum blocking time.

In the VF mode, the LLC-MAP converter fully inherits the high efficiency advantages of the conventional LLC converter. In the MR mode, despite the conversion efficiency decreases caused by the magamp core loss, a wide input-voltage range can be achieved without varying the switching frequency in a wide range, which reduces the switching losses. Therefore, the efficiency impact of the two magamps is affordable.

In summary, when the input-voltage is within the working range of the traditional LLC, the conversion efficiency of the LLC-MAP is basically the same. When the input voltage is out of the working range of the traditional LLC, the LLC- MAP converter makes a tradeoff for a wider input-voltage range with acceptable losses increase.


E. Performance Comparison

The proposed method gives a hint that the input-voltage range of an LLC converter may also be regulated through the secondary-side post-regulator. Although adding two magamps leads to additional cost, the proposed converter uses two MOSFETs less than the primary-side variable-structure LLC converters presented in [13]-[15]. The price of a magamp in this application is roughly equal to the price of a MOSFET. However, the proposed control circuit only adds several diodes, transistors and resistors to the control circuit, while a more expensive digital processor and isolated MOSFET drivers should be employed in a primary-side variable-structure. Therefore, considering the entire system, the proposed method has a price advantage.

On the other hand, primary-side variable-structures usually suffer from overshoot/undershoot problems on the output during mode transitions. In general, to overcome these problems, some complex algorithms have been applied. In the LLC-MAP converter, the LLC loop and the magamp loop have essentially the same frequency-response characteristics. Both of them can share a feedback controller, which is very simple. This gives the converter the advantage of a fast response. Therefore, during mode transitions, the output voltage can be smoothly regulated.

It should be noted that each of the solutions has advantages and disadvantages. The structure proposed is a good candidate for a wide input analog-controlled LLC converter. The LLC- MAP converter can be combined with a primary-side variable- structure to further extend the operational range in a future work.



Ⅳ. EXPERIMENTAL PERFORMANCE EVALUATION

A laboratory prototype is built to verify the performance of the proposed converter. The main parameters of the prototype are shown as follows: Vin=160-300V, Vo=25V, output power Po=400W and f0=92kHz. The key components of the prototype are shown in Table I. The diameter of the magamp core is 15.5 mm and the height is 5.7 mm. A size comparison between a magamp and a MOSFET with a TO-220 package is shown in Fig. 9.


TABLE I KEY PARAMETERS OF THE CONVERTER

Component

Parameter

Lr

20μH

Cr

150nF

Lm

120μH

S1 and S2

Infineon’s IPP50R199CP

D1 and D2

ST’s STPS41L60CT

n

13:3

Magamp core nSr LLC Controller

VAC W481 11ts TI’s UCC25600


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원본 그림의 이름: image63.jpeg
원본 그림의 크기: 가로 405pixel, 세로 311pixel

Fig. 9. Size comparison between a magamp and a MOSFET.


Fig. 10(a) and Fig. 10(b) show steady state experimental waveforms of the LLC-MAP converter in the VF mode with Vin=160V and Io=16A. As shown in these waveforms, S1 and S2 operate under the ZVS condition and the full ZCS of D1 and D2 have been achieved.


Fig. 10. Switching waveforms in the VF mode: (a) ir, vm, vgs2 and vds2; (b) id2, vd2 and vTsec.

그림입니다.
원본 그림의 이름: CLP00000eec003e.bmp
원본 그림의 크기: 가로 1375pixel, 세로 694pixel

(a)

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원본 그림의 이름: CLP00000eec003f.bmp
원본 그림의 크기: 가로 1373pixel, 세로 686pixel

(b)


Fig. 11(a) and Fig. 11(b) show steady state experimental waveforms in the MR mode with Vin=300V and Io=15A. As can be seen, the blocking ratio dB is 0.35. S1 and S2 operate under the ZVS condition. Since the slope of the current flowing through D2 in the MR mode is greater than that in the VF mode, D2 has a slight reverse recovery current. However, due to the current limiting effect of the primary side resonant inductor Lr, the reverse recovery of D2 is negligibly small. It is still considered that D1 and D2 satisfy the ZCS condition. These waveforms are well matched with the analysis.


Fig. 11. Switching waveforms in the MR mode: (a) ir, vm, vgs2 and vds2; (b) id2, vd2 and vTsec.

그림입니다.
원본 그림의 이름: CLP00000eec0040.bmp
원본 그림의 크기: 가로 1334pixel, 세로 660pixel

(a)

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원본 그림의 이름: CLP00000eec0041.bmp
원본 그림의 크기: 가로 1337pixel, 세로 654pixel

(b)


Dynamic waveforms with input-voltage steps from 160V up to 280V are shown in Fig. 12. The overshoot of the output, which is about 2% of the output regulation, is extremely small. This indicates a good performance between the mode transition periods since the magamp loop and the LLC loop share the same controller.


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원본 그림의 이름: CLP00000eec0042.bmp
원본 그림의 크기: 가로 921pixel, 세로 1001pixel

Fig. 12. Experimental waveforms of mode transitions.


Efficiency curves tested under different loads are shown in Fig. 13. When the input voltage varies from 160V to 300V, the highest efficiency is up to 94.6%. The best efficiency curve is obtained when Vin=210V since both the switching losses and conduction losses achieve an optimal balance. When the input voltage is 160V, the inverter operates in the VF mode within the full load range. Correspondingly, when the input voltage is 300V, the LLC-MAP converter operates in the MR mode within the full range. Moreover, since the conduction loss associated with the circulation current and the loss of the magamp increase when a wide input-voltage range is covered by the MR mode, the curve at 300V is below the one at 210V. However, in practical applications, the converter usually operates at half load or 3/4 load. Even if the input voltage is 300V, the efficiency of the converter is still above 92%.


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원본 그림의 이름: CLP00000eec0043.bmp
원본 그림의 크기: 가로 1472pixel, 세로 729pixel

Fig. 13. Measured efficiency with different values of Vin.


Fig. 14. shows an efficiency comparison between the LLC-MAP converter and the conventional HB LLC converter at a 60% load with the same key parameters. The LLC-MAP converter setting fmax is 100 kHz. Since the maximum frequency of the utilized controller chip is 350 kHz, the upper limit of the operating frequency of the conventional HB LLC converter is about 340 kHz. The measured efficiency of the conventional HB LLC converter is approximately 0.3% higher than the LLC-MAP converter in the VF mode region. This difference can be attributed to the copper loss of the magamp auxiliary post-regulator. At 240V, the efficiency of the conventional HB LLC converter is lower than that of the LLC-MAP converter due to the increasing of the switching loss since the converter operates at a very high frequency. A conventional HB LLC converter cannot regulate the output when the input-voltage is higher than 240V due to limitations on the switching frequency. However, the LLC-MAP converter switches to the MR mode as early as when the input voltage is 230V. In the MR mode region, since Vin increases, tB increases accordingly. As a result, the increment of the core loss of the magamp leads to a reduction in efficiency. However, the overall efficiency is still high. To improve the efficiency, a synchronous rectifier can be used in the converter. It should be noted that this is a compromise between the conversion efficiency and the operational voltage range.


그림입니다.
원본 그림의 이름: CLP00000eec0044.bmp
원본 그림의 크기: 가로 1507pixel, 세로 688pixel

Fig. 14. Efficiency Comparison.


The input-voltage range of the proposed LLC-MAP converter is 1.75 times that of the conventional HB LLC converter. The proposed converter can be combined with the primary-side topology morphing solutions to further extend the operation ranges of the conventional LLC resonant converter.



Ⅴ. CONCLUSIONS

A very simple method for extending the input-voltage range of a HB LLC resonant converter has been proposed and verified in this paper. In comparison with the conventional HB LLC converter, magamp auxiliary post-regulators are added. Duty cycle control of the magamp post-regulator is applied to the converter when a dc gain smaller than unity is needed for the high input-voltage range. This method can narrow the switching-frequency range of a converter. ZVS have been achieved for the primary switches and ZCS has been realized for the secondary diodes. Experimental results from a laboratory prototype verify the effectiveness and feasibility of the proposed solution.



REFERENCES

[1] B. Yang, F. C. Lee, A. J. Zhang, and G. Huang, “LLC resonant converter for front end DC/DC conversion,” in APEC. Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.02CH37335), Vol. 2, pp. 1108-1112, 2002.

[2] W. Sun, H. Wu, H. Hu, and Y. Xing, “Resonant tank design considerations and implementation of a LLC resonant converter with a wide battery voltage range,” J. Power Electron., Vol. 15, No. 6, pp. 1446-1455, Nov. 2015.

[3] H.-P. Park and J.-H. Jung, “Modeling and feedback control of LLC resonant converters at high switching frequency,” J. Power Electron., Vol. 16, No. 3, pp. 849-860, May 2016.

[4] C. H. Park, S. H. Cho, J. Jang, S. K. Pidaparthy, T. Ahn, and B. Choi, “Average current mode control for LLC series resonant DC-to-DC converters,” J. Power Electron., Vol. 14, No. 1, pp. 40-47, Jan. 2014.

[5] X. Fang, H. Hu, Z. J. Shen, and I. Batarseh, “Operation mode analysis and peak gain approximation of the LLC resonant converter,” IEEE Trans. Power Electron., Vol. 27, No. 4, pp. 1985-1995, Apr. 2012.

[6] X. Fang, H. Hu, F. Chen, U. Somani, E. Auadisian, J. Shen, and I. Batarseh, “Efficiency-oriented optimal design of the LLC resonant converter based on peak gain placement,” IEEE Trans. Power Electron., Vol. 28, No. 5, pp. 2285- 2296, May 2013.

[7] Z. Fang, T. Cai, S. Duan, and C. Chen, “Optimal design methodology for LLC resonant converter in battery charging applications based on time-weighted average efficiency,” IEEE Trans. Power Electron., Vol. 30, No. 10, pp. 5469-5483, Oct. 2015.

[8] J. Y. Lee, Y. S. Jeong, and B. M. Han, “An isolated DC/DC converter using high-frequency unregulated llc resonant converter for fuel cell applications,” IEEE Trans. Ind. Electron., Vol. 58, No. 7, pp. 2926-2934, Jul. 2011.

[9] X. Sun, J. Qiu, X. Li, B. Wang, L. Wang, and X. Li, “An improved wide input voltage buck-boost+LLC cascaded converter,” in 2015 IEEE Energy Conversion Congress and Exposition (ECCE), pp. 1473-1478, 2015.

[10] Z. Liang, R. Guo, G. Wang, and A. Huang, “A new wide input range high efficiency photovoltaic inverter,” in 2010 IEEE Energy Conversion Congress and Exposition, pp. 2937-2943, 2010.

[11] M. M. Jovanović and B. T. Irving, “On-the-Fly topology- morphing control – Efficiency optimization method for LLC resonant converters operating in wide input- and/or output-voltage range,” IEEE Trans. Power Electron., Vol. 31, No. 3, pp. 2596-2608, Mar. 2016.

[12] X. Sun, X. Li, Y. Shen, B. Wang, and X. Guo, “Dual- bridge LLC resonant converter with fixed-frequency pwm control for wide input applications,” IEEE Trans. Power Electron., Vol. 32, No. 1, pp. 69-80, Jan. 2017.

[13] S. M. S. I. Shakib and S. Mekhilef, “A frequency adaptive phase shift modulation control based LLC series resonant converter for wide input voltage applications,” IEEE Trans. Power Electron., Vol. 32, No. 11, pp. 8360-8370, Nov. 2017.

[14] L. Hang, S. Wang, Y. Gu, W. Yao, and Z. Lu, “High cross- regulation multioutput series resonant converter with magamp postregulator,” IEEE Trans. Ind. Electron., Vol. 58, No. 9, pp. 3905-3913, Sep. 2011.

[15] U. Kundu, K. Yenduri, and P. Sensarma, “Accurate ZVS analysis for magnetic design and efficiency improvement of full-bridge LLC resonant converter,” IEEE Trans. Power Electron., Vol. 32, No. 3, pp. 1703-1706, Mar. 2017.

[16] B. C. Kim, K. B. Park, C. E. Kim, B. H. Lee, and G. W. Moon, “LLC resonant converter with adaptive link-voltage variation for a high-power-density adapter,” IEEE Trans. Power Electron., Vol. 25, No. 9, pp. 2248-2252, Sep. 2010.

[17] Y.-T. Chen and D. Y. Chen, “Small-signal modeling of magnetic amplifier post regulators with current-mode control,” IEEE Trans. Ind. Electron., Vol. 47, No. 4, pp. 821-831, Aug. 2000.



그림입니다.
원본 그림의 이름: image69.jpeg
원본 그림의 크기: 가로 150pixel, 세로 177pixel

Xiaoguang Jin was born in Hebei, China, in 1983. He received his M.S. degree in Electrical Engineering from Zhejiang University (ZJU), Hangzhou, China, where he is presently working towards his Ph.D. degree in Electrical Engineering. From 2004 to 2008, he worked as a Power Supply Design Engineer with Delta Electronics, China. From 2011 to 2012, he was an Electrical Engineer with One-Cycle-Control Inc., Irvine, CA, USA. His current research interests include the topologies and control of the power converters for datacenters and server power supplies, resonant converters with a wide voltage range and battery management systems.


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원본 그림의 이름: CLP00000eec0045.bmp
원본 그림의 크기: 가로 416pixel, 세로 491pixel

Huipin Lin was born in Ningbo, China, in 1987. He received his B.S. degree in Electrical Engineering from China Jiliang University, Hangzhou, China, in 2009. He is presently working towards his Ph.D. degree at the National Key Laboratory of Power Electronics, Department of Electrical Engineering, Zhejiang University (ZJU), Hangzhou, China. His current research interests include DC/DC converters and their digital control.


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원본 그림의 이름: image70.png
원본 그림의 크기: 가로 190pixel, 세로 253pixel

Jun Xu was born in Taixing, China, in 1981. He received his M.S. degree in Electrical Engineering from Jiangsu University, Zhenjiang, China, in 2006. His current research interests include DC/DC converters and switching power supplies.


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원본 그림의 이름: image71.png
원본 그림의 크기: 가로 180pixel, 세로 262pixel

Zhengyu Lu received his B.S. degree in Industrial Automatic Control from Hohai University, Nanjing, China, in 1982; and his Ph.D. degree in Power Electronics from Zhejiang University (ZJU), Hangzhou, China, in 1987. From 1996 to 1998, he was a Visiting Scholar and Researcher at the University of Birmingham, Birmingham, ENG, UK, and the Imperial College London, London, ENG, UK. He is presently working as a Professor at ZJU and as Director of the China National Power Electronics Laboratory. His current research interests include power converters, scale lower-power distributed renewable energy systems, battery management, motor drivers and power quality.