사각형입니다.

https://doi.org/10.6113/JPE.2019.19.1.58

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Multi-Output LED Driver Integrated with 3-Switch Converter and Passive Current Balance for Portable Applications


Sen Song*, Kai Ni*, Guipeng Chen**, Yihua Hu*, and Dongsheng Yu


*Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, ENG, UK

**School of Aerospace Engineering, Xiamen University, Xiamen, China

School of Electrical and Power Engineering, China University of Mining and Technology, Xuzhou, China



Abstract

This study presents a new portable eight-output light emitting diode (LED) driver. The eight output-channels are divided into two equal groups, and their output powers can be controlled individually by three active switches. In addition, a simple capacitor-based passive current balancing circuit (CBC) is employed in each port to guarantee that the currents of the four LEDs are the same. When compared with the conventionally used separate two-output isolated converters, the proposed one uses one less active switch. Moreover, zero-voltage-switching (ZVS) is achieved, which improves the power efficiency of the driver. Finally, a highly compact prototype is built, which can reach an efficiency of 94.6%.


Key words: Multiple outputs, Passive current balance, Reduced switches, Zero-voltage-switching (ZVS)


Manuscript received Apr. 20, 2018; accepted Nov. 10, 2018

Recommended for publication by Associate Editor Fuxin Liu.

Corresponding Author: dongsiee@163.com Tel: +86 516 83592000, China Univ. Mining & Tech.

*Dept. of Electrical Eng. & Electron., University of Liverpool, UK

**School of Aerospace Engineering, Xiamen University, China



Ⅰ. INTRODUCTION

The light emitting diode (LED) has enormous potential in replacing conventional lamps in residential, automotive, decorative and medical applications due to its advantageous features such as high power density, high luminous efficiency, long lifespan, mercury free nature and quick response [1], [2]. For high illuminance application scenarios, numerous LEDs are connected in series or parallel. For series-connected LEDs, a high voltage stress is caused on the output capacitor and other insulation components. For parallel-connected LEDs, regulating the current through different LED strings requires current balancing technology due to the LED’s current- voltage characteristic and negative temperature coefficient [3].

Achieving a high power efficiency while maintaining high compactness of the whole system is still a challenge for LED drivers. The authors of [4] removed the output capacitor of the buck converter to achieve a high power density, which decreases the power efficiency to under 90%. The authors of [5] used a switched capacitor converter (SCC) to drive LEDs, whose efficiency can only reach around 85%, in spite of the systems simple structure. Fortunately, from the analysis of a SCC [6], [7], significant power losses can be avoided by employing inductors. In [8]-[10], the flyback converter has a simple structure. To increase its power efficiency, different types of snubbers are utilized. However, all of them have their deficiencies. For instance, the active snubber in [8] and the TCR snubber in [9] increase the circuit complexity and cost. The RCD snubber in [10] cannot recycle the leakage inductance power, which leads to hard-switching and causes massive switching losses. With at least two more inductors, the LLC [11], [12] and CLCL topologies [13] can improve the power efficiency by achieving soft-switching operation of the active switches. These projects improve the power efficiency with a sacrifice in terms of compactness, which is not an ideal trade-off.

Current regulating for different LED strings can be achieved by applying active current balancing circuits (CBCs) [14], [15] and passive CBCs [16]-[19]. The active method demands at least one active switch for each output channel, which results in a large switching loss. To avoid high costs and power losses, most current products adopt passive methods, which can be realized by employing inductors [16], [17] or capacitors [18], [19]. The inductor-based method uses transformers to balance the currents through different branches. However, deviations of transformers and the output voltages reduce the balance accuracy. The capacitor-based method can provide precise current balancing with a high power density and a low cost.

This study designs an LED driver with several merits. For instance, it has features such as multi-output, high power efficiency, controllable brightness and reduced component count. With these advantages, the driver is suitable for high power portable applications such as camping lights, vehicle headlights, emergency lights, etc. The topology of the proposed LED driver is shown in Fig. 1.


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원본 그림의 이름: CLP0000093825c1.bmp
원본 그림의 크기: 가로 840pixel, 세로 1032pixel

Fig. 1. Equivalent topology of the proposed LED driver.


This paper is organized as follows. Section II analyses the operation modes of the circuit. Section III discusses some of the main features of the topology. Section IV introduces a design guide for the proposed topology. Section V presents some experiment results. Section VI concludes the paper.



Ⅱ. OPERATION MODE DISCUSSION

The operation principles are discussed in this section. As depicted in Fig. 1, the primary power stage consists of an input DC voltage Vin, three active switches S0~S2, two switched capacitors C1~C2, and two transformers T1~T2 with magnetic inductances Lm1~Lm2 as well as leakage inductances Lk1~Lk2. The three active switches, S0, S1 and S2, control the two output ports: S0&S1 for Port 1, and S0&S2 for Port 2. The two ports are identical CBCs. More precisely, Port 1 has three resonant capacitors Cr10~Cr12, four diodes D11~D14, four output capacitors C11~C14, and four LED-loads LED11~LED14.

Following assumptions are made to simplify the analysis.

1. All of the switches and diodes are ideal.

2. The transformers T1 and T2 are identical, with the same voltage ratio n:1 and secondary side referred leakage inductance Lk.

3. The input voltage is an ideal DC voltage.

4. The capacitance of the resonant capacitors Cr10, Cr11, Cr12, Cr20, Cr21 and Cr22 are equal.
Cr10=Cr11=Cr12=Cr20=Cr21=Cr22=Cr.

5. The voltages of the capacitors C1~C2 are constant.

6. The switches S1 and S2 have the same duty cycle, DS1=DS2=D.

Fig. 2 shows key waveforms corresponding to the eight operating modes depicted in Fig. 3. Vgs0-Vgs2 and Vds0-Vds2 are control signals and drain-to-source voltages of the switches S0-S2 respectively. VT1-VT2 are the primary voltages of the transformers T1-T2; VCr0-VCr2 are the voltages of the three resonant capacitors Cr10-Cr12; and iD11-iD14 are the currents through the diodes D11-D14. The two passive CBCs have similar operations. Thus, the operation of Port2 is not discussed.


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원본 그림의 이름: CLP000009380001.bmp
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Fig. 2. Key waveforms of the proposed LED driver.


Fig. 3. Operation Modes 1-8 of the proposed LED driver: (a) Mode 1 [t0-t1]; (b) Mode 2 [t1-t2]; (c) Mode 3 [t2-t3]; (d) Mode 4 [t3-t4]; (e) Mode 5 [t4-t5]; (f) Mode 6 [t5-t6]; (g) Mode 7 [t6-t7]; (h) Mode 8 [t7-t8].

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원본 그림의 이름: CLP000009380010.bmp
원본 그림의 크기: 가로 745pixel, 세로 647pixel

(a)

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(b)

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원본 그림의 이름: CLP000009380011.bmp
원본 그림의 크기: 가로 743pixel, 세로 646pixel

(c)

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원본 그림의 이름: CLP000009380012.bmp
원본 그림의 크기: 가로 743pixel, 세로 645pixel

(d)

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원본 그림의 이름: CLP000009380013.bmp
원본 그림의 크기: 가로 766pixel, 세로 663pixel

(e)

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원본 그림의 이름: CLP000009380014.bmp
원본 그림의 크기: 가로 771pixel, 세로 663pixel

(f)

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원본 그림의 이름: CLP000009380015.bmp
원본 그림의 크기: 가로 767pixel, 세로 665pixel

(g)

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원본 그림의 이름: CLP000009380016.bmp
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(h)


According to the volt-second balance, the voltage across C1~C2 can be obtained.

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원본 그림의 이름: CLP000009380002.bmp
원본 그림의 크기: 가로 842pixel, 세로 68pixel                (1)

그림입니다.
원본 그림의 이름: CLP000009380003.bmp
원본 그림의 크기: 가로 391pixel, 세로 70pixel                                 (2)

where D = ton/ts and ton are the on-times of the switches S1~S2 in each switching cycle.

Mode 1 [t0–t1]: At time t0, the switch S0 is turned on, and the switch S1 is off. The voltage across the transformer T1 is Vin-Vc. The current through Lm1 keeps increasing linearly until t2.

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원본 그림의 이름: CLP000009380004.bmp
원본 그림의 크기: 가로 618pixel, 세로 163pixel                        (3)

At time t0, the total voltage across Cr10, Cr11 and C11 is lower than that of Cr12 and C14.

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원본 그림의 이름: CLP000009380005.bmp
원본 그림의 크기: 가로 1064pixel, 세로 70pixel       (4)

Therefore, D11 is forward biased to transfer power to the LED11. Then Cr10 and Cr11 are charged. The state equations of this mode are obtained as:

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원본 그림의 이름: CLP000009380006.bmp
원본 그림의 크기: 가로 1081pixel, 세로 731pixel               (5)

With Eq. (5), the secondary side current and the voltages across the capacitors Cr10, Cr11 and Cr12 can be calculated as:

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원본 그림의 이름: CLP000009380007.bmp
원본 그림의 크기: 가로 1319pixel, 세로 506pixel       (6)

where ΔvCr-ini=(Vin-VC)/n-vCr10-vCr11-VC11 is the voltage across the leakage inductance Lk1 at time t0. Zn is the characteristic impedance of the resonant tank formed by Lk1, Cr10 and Cr11; and ωa is the resonant angular frequency. 그림입니다.
원본 그림의 이름: CLP000009380008.bmp
원본 그림의 크기: 가로 401pixel, 세로 79pixel and 그림입니다.
원본 그림의 이름: CLP000009380009.bmp
원본 그림의 크기: 가로 417pixel, 세로 87pixel. At time t1, the total voltage across Cr10, Cr11 and C11 is the same as that of Cr12.

그림입니다.
원본 그림의 이름: CLP00000938000a.bmp
원본 그림의 크기: 가로 979pixel, 세로 65pixel                  (7)

Then, D14 is conducted. The time duration of Mode 1 is determined as:

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원본 그림의 이름: CLP00000938000b.bmp
원본 그림의 크기: 가로 1129pixel, 세로 158pixel            (8)

Mode 2 [t1–t2]: From t1, D14 begins to be forward biased, and the power is transferred to LED11 and LED14. In the secondary circuit, the resonant tank is composed of Cr10, Cr11, Cr12 and Lk1 in this mode. The state equation of Mode 2 is:

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원본 그림의 이름: CLP00000938000e.bmp
원본 그림의 크기: 가로 1165pixel, 세로 755pixel       (9)

According to Eq. (9), the secondary current is1 is derived as:

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원본 그림의 이름: CLP000009380017.bmp
원본 그림의 크기: 가로 1209pixel, 세로 154pixel     (10)

The time duration of Mode 2 is:

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원본 그림의 이름: CLP000009380018.bmp
원본 그림의 크기: 가로 278pixel, 세로 66pixel                                        (11)

where toff is the off-time of the switches S1 and S2; k=sinωaτ1/sinωbτcom, θ=π-ωbτcom is the initial phase of is at t1, 그림입니다.
원본 그림의 이름: CLP000009380019.bmp
원본 그림의 크기: 가로 391pixel, 세로 84pixel is the resonant angular frequency according to Fig. 3(b), and τcom=tcom-t1. Where tcom is the time taken for the resonant tank to achieve completing resonance, and tcom can be derived as:

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원본 그림의 이름: CLP00000938001a.bmp
원본 그림의 크기: 가로 1506pixel, 세로 145pixel    (12)

Mode 3 [t2–t3]: S2 is turned off at time t2. During Mode 3, the parasitic capacitor of S1 is discharged while the parasitic capacitor of S2 is charged. The voltage across S1 drops from Vin to zero to achieve ZVS turn-on. The resonant processes of the power stage are given below.

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원본 그림의 이름: CLP00000938001b.bmp
원본 그림의 크기: 가로 871pixel, 세로 464pixel             (13)

where Cs represents the parasitic capacitance of the active switches.

Modes 4-5 [t3–t5]: At time t3, the switch S1 is turned on with ZVS. During Modes 4-5, the transformer T1 is powered by the capacitor C1, and the polarity of the voltage across T1 is opposite that of Modes 1-3. The current through Lm1 keeps decreasing linearly.

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원본 그림의 이름: CLP00000938001c.bmp
원본 그림의 크기: 가로 650pixel, 세로 144pixel                        (14)

Modes 4-5 are similar to Modes 1-2 except that the three resonant capacitors given the reference of the capacitors here are discharged due to the reversed power flow direction. During Mode 4, D12 is forward biased to transfer power from the input to LED12. At t4, vCr0+vCr2+VC12=vCr1+VC13, and D13 is conducted when power is transferred to LED12 and LED13.

Mode 6 [t5–t6]: S0 is turned off at t5. The energy stored in the parasitic capacitor of S2 is released while the parasitic capacitor of S0 is charged. The resonant process can be expressed as:

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원본 그림의 이름: CLP00000938001d.bmp
원본 그림의 크기: 가로 1214pixel, 세로 154pixel      (15)

Mode 7 [t6t7]: At t6, the switch S2 is turned on with zero voltage. Mode 6 takes a relatively short. Thus, it can be neglected. Mode 7 is a continuation of Mode 5.

Mode 8 [t7–t8]: S1 is turned off at t7. The parasitic capacitor of S0 is discharged while the parasitic capacitor of S1 is charged. The voltage across S0 is decreased with the rising of the voltage across S1. Therefore, at the start of the next switching cycle, S0 can achieve ZVS. The resonant process in Mode 8 can be expressed by the following equations:

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원본 그림의 이름: CLP00000938001e.bmp
원본 그림의 크기: 가로 799pixel, 세로 301pixel                     (16)



Ⅲ. TOPOLOGY CHARACTERISTICS ANALYSIS


A. Passive Current Balancing

By the charge balance of the resonant capacitors, the energy charged to Cr11 through D11 in Modes 1-3 is equal to the energy discharged from Cr11 through D13 in Modes 5-8. Because Modes 3, 6 and 8 are very short, they are ignored in this discussion. The balance of Cr11 is between Modes 1-2, 5 and 7. The average current of D11 and D13 in a switching cycle Ts is:

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원본 그림의 이름: CLP00000938001f.bmp
원본 그림의 크기: 가로 875pixel, 세로 132pixel                (17)

where Q11_ch is the energy charged to Cr11 in Modes 1-2, and Q11_dis is the energy discharged from Cr11 in Modes 5 and 7.

Similarly, the charge balance of Cr10 is achieved through D11 and D12. Cr12 is charged through D14 and discharged through D12. Then, Eq. (18)-(20) are obtained as:

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원본 그림의 이름: CLP000009380020.bmp
원본 그림의 크기: 가로 904pixel, 세로 132pixel               (18)

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원본 그림의 이름: CLP000009380021.bmp
원본 그림의 크기: 가로 908pixel, 세로 139pixel               (19)

Therefore, according to Eq. (17)-(19), the relationship among the average currents of the diodes D11-D14 are shown as:

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원본 그림의 크기: 가로 934pixel, 세로 70pixel              (20)

Additionally, because the output capacitors C11-14 are large enough, the four output currents and the notations of the four currents are equal to the diodes average currents. Hence:

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원본 그림의 이름: CLP000009380023.bmp
원본 그림의 크기: 가로 767pixel, 세로 65pixel                     (21)

Due to the CBC, the currents of the four LED-loads are balanced. Moreover, in accordance with Eq. (17)-(20), the non-ideal factors of Cr10, Cr11 and Cr12 are tolerable.


B. Operation of Resonant Capacitors

According to the operations in Modes 1-2 and 4-7, power is delivered to the four output channels through four paths, which are Cr10-Cr11-LED11, Cr12-LED14, Cr10-Cr12-LED12 and Cr11-LED13. When S1 is open, Cr10-Cr11 and Cr12 are charged. When S1 is closed, Cr10-Cr12 and Cr11 are discharged. Based on the current balancing analysis, the average currents through LED11 and LED14 are equal. Therefore, Eq. (22) is derived.

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원본 그림의 이름: CLP000009380024.bmp
원본 그림의 크기: 가로 1315pixel, 세로 265pixel    (22)

Hence, at time t0, Eq. (4) is verified. After t0, power is delivered to LED11 and then to LED14. Similarly, when S1 is turned on, power is transferred to LED12 and then to LED13.


C. Control System

As illustrated in Fig. 4(a), the currents through all of the LED strings in Port 1 and Port 2 are controlled by the PWM control where two individual proportion-integrator (PI) compensators are adopted. Due to the current balancing characteristic, the currents through the four LED strings in port 1 LED11-LED14 have the same value as io1, and the value of the currents through the four LED strings LED21-LED24 have the same value as io2. To collect the output currents io1 and io2, two sample resistors Rs1 and Rs2 are series connected to one LED string in each port. Thus, io1 and io2 are regulated as Vo1,ref/Rs1 and Vo2,ref/Rs2. The control variables a and b are received from two individual PI compensators according to the error voltage between the reference voltages Vo1,refVo2,ref and the voltages Vo1 and Vo2 across the sample resistors Rs1 and Rs2.


Fig. 4. Control systems: (a) Control system schematic; (b) Control signals for three switches.

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원본 그림의 이름: CLP000009380025.bmp
원본 그림의 크기: 가로 879pixel, 세로 1012pixel

(a)

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원본 그림의 이름: CLP000009380026.bmp
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(b)


As shown in Fig. 4(b), the control signals for the switches S0, S1 and S2 are obtained by comparisons of (a+b, Vt1), (Vt1, a) and (Vt2, b), respectively. DS0, DS1 and DS2 are the duty cycles of the three switches. When compared with the saw tooth Vt1, Vt2 is delayed by a×Ts. To achieve the same operation of two ports, Vo1,ref=Vo2,ref and Rs1 = Rs2 so that the control variables a=b and DS1=DS2. The duty cycles of the three switches can be calculated by (23).

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원본 그림의 이름: CLP000009380029.bmp
원본 그림의 크기: 가로 275pixel, 세로 238pixel                      (23)

To adjust the brightness, the switch S2 can be short-circuited by an external wire so there is no power transferred to Port 2. The variable c becomes zero. Therefore, the LED driver can provide two-stage brightness: 100% when both S1 and S2 are working and 50% when only one of them is operating. Furthermore, the driver provides two-stages brightness and increases reliability due to the two individual PI compensators and two isolated ports.


D. Soft Switching Analysis


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Fig. 5. ZVS turn on of three switches in a simulation.


As illustrated in Fig. 5, all three of the power switches can achieve ZVS turn on. In Mode 3, before the switch S1 is turned on, the energy stored in the parasitic capacitor of the switch S1 is released to zero. Then the body diode of the switch is forward biased to conduct S1 with zero voltage. Furthermore, because Lm1 and Lm2 are large enough, the parasitic capacitor of S1 can be completely discharged. According to Eq. (13), if the dead time tds1 is shorter than t3–t2, S1 can achieve the ZVS operation. Similarly, in Eq. (15)-(16), if the dead time tds2 is shorter than t6–t5, S2 can obtain ZVS. In addition, S0 can achieve ZVS when tds0<t8–t7.

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원본 그림의 이름: CLP00000938002a.bmp
원본 그림의 크기: 가로 793pixel, 세로 580pixel              (24)

where τ3 is the time duration of mode 3; τ6 is the time duration of mode 6; and τ8 is the time duration of mode 8.


E. Expandable Topology

As illustrated in Fig. 6, the converter can be extended in terms of the output channels by adding resonant capacitors. According to the current balancing operation, one phase leg requires one resonant capacitor, e.g. Cr11-Cr12 for phase legs 1-2 respectively, and one more resonant capacitor, e.g. Cr10 is connected between the two phase legs. Hence, by adding 2n-1 resonant capacitors, 2n output channels can be achieved.


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원본 그림의 이름: CLP00000938002b.bmp
원본 그림의 크기: 가로 1543pixel, 세로 744pixel

Fig. 6. Expandable topology.


Ⅳ. DESIGN GUIDE

This section introduces the design considerations including the relationships among the switching frequency, leakage inductor and the resonant capacitors, as well as the operating characteristics of the components.


A. Passive Current Balancing

The average input current can be calculated as:

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원본 그림의 크기: 가로 555pixel, 세로 165pixel          (25)

The output power can be derived as:

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원본 그림의 이름: CLP00000938002d.bmp
원본 그림의 크기: 가로 556pixel, 세로 165pixel          (26)

With the analysis and the trade-off between the power dissipation in the active switches and transformers, the switching frequency is set at 60 kHz in the experiment. To achieve ZVS turn-on of the switches, the on/off time of the switches should be larger than the resonant time based on ωa and ωb. As a result, there is always primary current ip to discharge the parasitic capacitance of the active switches. Moreover, the off-time of the two switches S1 and S2 are shorter than their on-time. Hence, according to (12), the following equation can be obtained:

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원본 그림의 이름: CLP00000938002e.bmp
원본 그림의 크기: 가로 1156pixel, 세로 240pixel      (27)

where A=arccos{[(Vin-VC1)/n-vCr12(t0)-VC14]/ΔvCr-ini.

However, with a large leakage inductance, the secondary current is cannot return to zero immediately after the turn- on/turn-off of active switches. Hence, the leakage inductance is chosen as 9μH, and the 3.3μF resonant capacitance Cr is designed to satisfy Eq. (27).

Based on the primary side referred leakage inductance and switching frequency, the minimum value of the switched capacitors is determined according to:

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원본 그림의 이름: CLP00000938002f.bmp
원본 그림의 크기: 가로 505pixel, 세로 156pixel                            (28)

For the switched capacitors C1-C2, a large capacitance can reduce their voltage ripple. However, to reduce the volume of the proposed converter, the switched capacitors are designed as 20μF.


B. Voltage and Current Stress of Active Switches

The voltage stress of three switches is equal to the input voltage Vin. According to Fig. 3, the current through S1 reaches its maximum value during the interval [t3~t5]. With the primary currents, the current stress of the switch S1 can be obtained as:

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원본 그림의 이름: CLP000009380031.bmp
원본 그림의 크기: 가로 1798pixel, 세로 138pixel       (29)

Due to the large magnetic inductances and the voltage clamping transformers, the currents through the magnetic inductances are ignored. The maximum current of the switch S2 is obtained at time t7, which has the same value as that of S1. The current through S0 is either ip1 or ip2. Therefore, the current stress of the switches can be derived as:

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원본 그림의 이름: CLP000009380032.bmp
원본 그림의 크기: 가로 1003pixel, 세로 368pixel             (30)

where Δv’Cr-ini=-VC1/n-vCr10+vCr12-VC12 indicates the voltage across the leakage inductance Lk1 at time t4.


C. Voltage Variation of Resonant Capacitors

According to Eq. (17)-(19) and (22), Eq. (31) can be derived as:

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원본 그림의 이름: CLP000009380033.bmp
원본 그림의 크기: 가로 1345pixel, 세로 167pixel        (31)

where Δvcr-A and Δvcr-B are the voltage changes of the corresponding switches in modes 1 and 2, respectively. Additionally, in mode 2, iCr12(t)=2iCr10(t)=2iCr11(t). Hence:

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where QB_ch indicates the energy stored in Cr10 or Cr11 in mode 2, and QA_ch is the energy stored in Cr10 or Cr11 in mode 1. Then the relationships among the voltage and energy variations of three resonant capacitors can be obtained by:

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Based on Eq. (8), (10) and (33), the following equation is obtained by:

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With the assumption of Cr10=Cr11=Cr12=Cr, the variables in Eq. (26) can be achieved as θ=1.37rad and k=0.962.



Ⅴ. EXPERIMENT RESULTS

To test and verify the performance of the designed LED driver, a prototype with a 24V DC input is built and displayed in Fig. 7.


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Fig. 7. Prototype of the proposed LED driver.


Table I shows the elements employed in the prototype. The power efficiency of this prototype can reach 94.6% with a 60 kHz switching frequency. Due to the similar operation of the two ports, only the experiment results of the primary power stage and Port 1 are illustrated.


TABLE I EXPERIMENT PARAMETERS

Symbols

Definitions

Values

Vin

Input voltage

24 V

Pout

Output power

100 W

Cr

Resonant capacitor

3.3 μF

Cout

C1i~C2i

Output capacitor

 

440μF

 

C1~C2

Converter capacitor

20μF

Vout

Output voltage

30.8 V

iout

Output current

0.4A

Transformer:

n

Voltage ratio

1:3

Lm

Magnetic inductance

203/201μH

Lk

Leakage inductance

8.27/8.46μH

Core

PQ3525

/

Semiconductor components:

S0~S2

SFP65N06

/

D1i~D2i

MBR20100CT

/


Fig. 8 shows the voltages and primary currents of the two transformers. The obtained experimental waveform is consistent with that in the theoretical analysis. When S1 is closed, the voltage of the transformer T1 is negative as –Vc, and the current ip1 keeps decreasing. When S1 is open, the voltage across the transformer T1 is positive as VinVc, and the current ip1 keeps increasing. Due to the large magnetic inductance, the primary side current ip1 is mainly affected by the secondary side current is1. Moreover, for the same reason, there is a delay for ip1 to return to zero after the switch’s state changed. Port 2 has a similar operation based on the on/off states of the switch S2. Additionally, when S0 is off, the voltages of both transformers are negative.


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Fig. 8. Currents and voltages of the transformers T1~T2.


As illustrated in Fig. 9, the ZVS operations of the active switches are verified. For example, the drain-source ids1 increases to ip2-ip1 after S1 is closed. Meanwhile, when S0 is open, ids1 drops to -ip1. The drain-source current ids flows through the parasitic diode before the turn-on of the corresponding switch and the ZVS turn-on of the switch is achieved. As a result, the switching loss is significantly decreased.


Fig. 9. ZVS operation of three MOSFET switches: (a) S0; (b) S1; (c) S2.

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(a)

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(b)

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(c)


In Fig. 10, the charge and discharge processes of the resonant tank are tested and shown. The two pairs of diodes, D11&D14 and D12&D13 have the same operations. In Fig. 10 (a), D14 is conducted after D11 with a time delay of τ1. Then they are reverse biased at the same time. Additionally, according to Fig. 10(b), Cr10 and Cr11 are charged before Cr12. Then Cr10 and Cr12 are discharged before Cr11. The voltages across Cr11 and Cr12 are always positive. However, for Cr10, the voltage crosses zero at t1 and t4 when the voltages of the two branches are equal. Fig. 10(c) displays the constant balanced output currents of the four output channels in Port 1.


Fig. 10. Current balance operation based on resonant capacitors: (a) currents through the diodes D11-D14; (b) voltages of the resonant capacitors Cr10-Cr12; (c) output currents through the four LED-loads LED11-LED14.

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(a)

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(b)

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(c)


The power efficiency of the LED driver is recorded under different input voltage values as shown in Fig. 11. The red line with diamond markers is obtained when both S1 and S2 are working with 8 LED strings. The blue line with triangle markers is obtained when only S1 is working with 4 LED strings in Port 1. The output power in the case presented by the blue line is half of that of the red line. With 8 LED strings, the efficiency can reach its highest point at 94.6%.


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Fig. 11. Power efficiency curve of the proposed LED driver.


Comparative results in terms of design complexity, power efficiency and output power scale are shown in Table II. The non-isolated LED driver with a switched capacitor [5] has the most straightforward design and smallest number of components. The LED driver with a flyback converter [9] uses only one active switch to achieve high compactness. However, their power efficiency is less than 90%, and they are preferred for low power applications. For high illuminance applications, [13] and [16] can achieve a power efficiency of around 95%. However, two external inductors are applied in [13] to construct the CLCL resonant tank, which increases the design complexity and volume. Thanks to the transformers installed for current balancing among different LED strings, [16] is suitable for high power applications, while the non-ideal factors of these transformers result in a high control complexity. From the aforementioned characteristic analysis, the proposed LED driver can achieve a high efficiency of 94.6% with a reduced component count. Additionally, the current balancing of LED strings is obtained by resonant capacitors whose values do not need to be the same.


TABLE II COMPARISON AMONG THE PROPOSED AND OTHER LED DRIVERS

LED drivers

Design complexity

Power efficiency

Output power

Switched capacitor [5]

Low

83%

Low

Flyback converter [9]

Low

90%

Low

CLCL resonant [13]

Medium

94.5%

High

Inductor-based CBC [16]

High

96.4%

High

Proposed

Low

94.6%

High



Ⅵ. CONCLUSION

This study proposes a novel LED driver designed for portable applications. The primary power stage uses only 3 active switches which is one less than conventionally used separate 2 output isolated converters. The following advantages are achieved.

1. High power efficiency: thanks to the ZVS turn-on and the passive CBCs, high power efficiency of 94.6% is obtained.

2. Low design complexity: the power stage uses only two magnetic components and two capacitors to achieve ZVS for all of the active switches. The current balancing operation is achieved due to the three resonant capacitors. Additionally, when compared with the conventional two isolated output converter, the proposed one uses one fewer active switch.

3. Multiple outputs: due to the two separate ports power stage and the two CBCs, the driver provides eight LED output-channels, which are divided into two parts with the same structure.

Experiment results are presented to verify the ZVS of the active switches, the operation of the two isolated ports and the balanced output currents of the proposed LED driver. This project is suitable for high power portable applications such as camping lights, vehicle lights and emergency lights.



REFERENCES

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[2] M. K. Richard and P. K. Sen, “Compact fluorescent lamps and their effect on power quality and application guidelines,” in Industry Applications Society Annual Meeting (IAS), pp. 1-7, 2010.

[3] X. Liu, Q. Yang, Q. Zhou, J. Xu, and G. Zhou, “Single- stage single-switch four-output resonant LED driver with high power factor and passive current balancing,” IEEE Trans. Power Electron., Vol. 32, No. 6, pp. 4566-4576, Jun. 2017.

[4] M. Al-Absi, Z. Khalifa, and A. Hussein, “A new capacitor- less buck DC-DC converter for LED applications,” Active and Passive Electronic Components, Vol. 2017, Article ID 2365848, 5 pages, 2017.

[5] E. E. dos Santos Filho, P. H. Miranda, E. M. Sá, and F. L. Antunes, “A LED driver with switched capacitor,” IEEE Trans. Ind. Appl., Vol. 50, No. 5, pp. 3046-3054, Sep.-Oct. 2014.

[6] C.-K. Cheung, S.-C. Tan, Y.-M. Lai, and K. T. Chi, “A new visit to an old problem in switched-capacitor converters,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, pp. 3192-3195, 2010.

[7] S.-C. Tan, S. Kiratipongvoot, S. Bronstein, A. Ioinovici, Y. Lai, and K. T. Chi, “Adaptive mixed on-time and switching frequency control of a system of interleaved switched- capacitor converters,” IEEE Trans. Power Electron., Vol. 26, No. 2, pp. 364-380, Feb. 2011.

[8] C.-Y. Wu, T.-F. Wu, J.-R. Tsai, Y.-M. Chen, and C.-C. Chen, “Multistring LED backlight driving system for LCD panels with color sequential display and area control,” IEEE Trans. Ind. Electron., Vol. 55, No. 10, pp. 3791-3800, Oct. 2008.

[9] S. Jung and G.-H. Cho, “Transformer coupled recycle snubber for high-efficiency offline isolated LED driver with on-chip primary-side power regulation,” IEEE Trans. Ind. Electron., Vol. 61, No. 12, pp. 6710-6719, Dec. 2014.

[10] B. Poorali and E. Adib, “Analysis of the integrated SEPIC-flyback converter as a single-stage single-switch power-factor-correction LED driver,” IEEE Trans. Ind. Electron., Vol. 63, No. 6, pp. 3562-3570, Jun. 2016.

[11] Y. Wang, J. Huang, G. Shi, W. Wang, and D. Xu, “A single-stage single-switch LED driver based on the integrated SEPIC circuit and class-E converter,” IEEE Trans. Power Electron., Vol. 31, No. 8, pp. 5814-5824, Aug. 2016.

[12] H. Ma, J.-S. J. Lai, C. Zheng, and P. Sun, “A high-efficiency quasi-single-stage bridgeless electrolytic capacitor-free high-power AC–DC driver for supplying multiple LED strings in parallel,” IEEE Trans. Power Electron., Vol. 31, No. 8, pp. 5825-5836, Aug. 2016.

[13] Y. Wang, Y. Guan, D. Xu, and W. Wang, “A CLCL resonant DC/DC converter for two-stage LED driver system,” IEEE Trans. Ind. Electron., Vol. 63, No. 5, pp. 2883-2891, May 2016.

[14] T.-J. Liang, W.-J. Tseng, J.-F. Chen, and J.-P. Wu, “A novel line frequency multistage conduction LED driver with high power factor,” IEEE Trans. Power Electron., Vol. 30, No. 9, pp. 5103-5115, Sep. 2015.

[15] E. S. Lee, B. H. Choi, D. T. Nguyen, B. G. Choi, and C. T. Rim, “Static regulated multistage semiactive LED drivers for high-efficiency applications,” IEEE Trans. Power Electron., Vol. 31, No. 9, pp. 6543-6552, Sep. 2016.

[16] J. Wang, J. Zhang, X. Wu, Y. Shi, and Z. Qian, “A novel high efficiency and low-cost current balancing method for multi-LED driver,” in Energy Conversion Congress and Exposition (ECCE), pp. 2296-2301, 2011.

[17] J.-I. Baek, J.-K. Kim, J.-B. Lee, H.-S. Youn, and G.-W. Moon, “Integrated asymmetrical half-bridge Zeta (AHBZ) converter for DC/DC stage of LED driver with wide output voltage range and low output current,” IEEE Trans. Ind. Electron., Vol. 62, No. 12, pp. 7489-7498, Dec. 2015.

[18] K. Hwu and W. Jiang, “Nonisolated two-channel LED driver with automatic current balance and zero-voltage switching,” IEEE Trans. Power Electron., Vol. 31, No. 12, pp. 8359-8370, Dec. 2016.

[19] S. M. Baddela and D. S. Zinger, “Parallel connected LEDs operated at high to improve current sharing,” in Industry Applications Conference, 2004. 39th IAS Annual Meeting. Conference Record of the 2004 IEEE, Vol. 3, pp. 1677- 1681, 2004.



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Sen Song was born in Hebei, China. He received his B.S. (with Honors) degrees in Electrical Engineering and Automation from Xi’an Jiaotong-Liverpool University, Suzhou, China, and in Electrical Engineering from the University of Liverpool, Liverpool, ENG, UK, in 2016, where he is presently working towards his Ph.D. degree. His current research interests include power electronic converters and HVDC transmission.


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Kai Ni (S’17) was born in Jiangsu, China. He received his B.S. (with Honors) degrees in Electrical Engineering and Automation from Xi’an Jiaotong-Liverpool University, Suzhou, China, and in Electrical Engineering from the University of Liverpool, Liverpool, ENG, UK, in 2016, where he is presently working towards his Ph.D. degree. His current research interests include the operation and control of asynchronized synchronous machines, power electronic converters and power systems.


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Guipeng Chen received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, Zhejiang University, Hangzhou, China, in 2011 and 2017, respectively. He joined the Fuji Electric Matsumoto Factory as a Summer Intern in 2014, and was invited to the University of Liverpool, Liverpool, ENG, UK, as a Research Assistant for a half-year program in July 2016. He is presently working as a Postdoctoral Researcher in the Instrument Science and Technology Postdoc Center, School of Aerospace Engineering, Xiamen University, Xiamen, China. His current research interests include automatic topology derivations of dc–dc converters and fault-tolerant converters.


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Yihua Hu received his B.S. and Ph.D. degrees from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 2003 and 2011, respectively. From 2011 to 2013, he was a Postdoctoral Fellow in the College of Electrical Engineering, Zhejiang University, Hangzhou, China. From 2013 to 2015, he worked as a Research Associate in the Power Electronics and Motor Drive Group, University of Strathclyde, Glasgow, SCT, UK. He is presently working as a Lecturer in the Department of Electrical Engineering and Electronics, University of Liverpool (UoL), Liverpool, ENG, UK. He has published 60 papers in IEEE Transactions journals. His current research interests include renewable generation, power electronics converters and control, electric vehicles, more electric ship/aircraft, smart energy systems and non-destructive test technology. He is the Associate Editor of the IET Renewable Power Generation, IET Intelligent Transport Systems and Power Electronics and Drives.


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Dongsheng Yu received his B.S. and Ph.D. degrees from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 2005 and 2011, respectively. From 2009 to 2010, he was a Visiting Student at the University of Western Australia, Perth, WA, Australia. From 2014 to 2015, he was an Endeavour Research Fellow at the University of Western Australia. He is presently working as an Associate Professor in the School of Electrical and Power Engineering, China University of Mining and Technology. His current research interests include power electronics, renewable energy, electric drives, nonlinear dynamics and memristive systems. He has published two books and over 50 papers in these areas.