사각형입니다.

https://doi.org/10.6113/JPE.2019.19.1.244

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Fast FCS-MPC-Based SVPWM Method to Reduce Switching States of Multilevel Cascaded H-Bridge STATCOMs


Xiuqin Wang*†, Jiwen Zhao*,**, Qunjing Wang*,**, Guoli Li*,**, and Maosong Zhang*,**


School of Electronics and Information Engineering, Anhui University, Hefei, China

*School of Electrical Engineering and Automation, Anhui University, Hefei, China

**National Engineering Laboratory of Energy-Saving Motor & Control Technology, Anhui University, Hefei, China



Abstract

Finite control set model-predictive control (FCS-MPC) has received increasing attentions due to its outstanding dynamic performance. It is being widely used in power converters and multilevel inverters. However, FCS-MPC requires a lot of calculations, especially for multilevel-cascaded H-bridge (CHB) static synchronous compensators (STATCOMs), since it has to take account of all the feasible voltage vectors of inverters. Hence, an improved five-segment space vector pulse width modulation (SVPWM) method based on the non-orthogonal static reference frames is proposed. The proposed SVPWM method has a lower number of switching states and requires fewer computations than the conventional method. As a result, it makes FCS-MPC more efficient for multilevel cascaded H-bridge STATCOMs. The partial cost function is adopted to sequentially solve for the reference current and capacitor voltage. The proposed FCS-MPC method can reduce the calculation burden of the FCS-MPC strategy, and reduce both the switching frequency and power losses. Simulation and experimental results validate the excellent performance of the proposed method when compared with the conventional approach.


Key words: Finite control set model-predictive control (FCS-MPC), Multilevel cascaded H-bridge (CHB), Space vector pulse width modulation (SVPWM), Static synchronous compensator


Manuscript received Dec. 15, 2017; accepted Oct.15, 2018

Recommended for publication by Associate Editor Kyo-Beum Lee.

Corresponding Author: wangxiuqin@ahu.edu.cn Tel: +86-551-63861845, Fax: +86-551-63861845, Anhui University

*School of Electrical Eng. and Automation, Anhui Univ., China

**Nat’l Eng. Lab. Energy-Saving Motor & Contr. Technol., Anhui Univ., China



Ⅰ. INTRODUCTION

Multilevel inverters provide a cost-effective solution for medium-voltage high-power energy conversion. In the multilevel inverter topology, the cascaded H-bridge (CHB) inverter is a mature and widely used topology [1]. The static synchronous compensator (STATCOM) has been an intensive research topic for power systems to control the power factor, regulate the grid voltage, stabilize the power system, etc. CHB inverters are often chosen to implement STATCOMs in high-voltage and high-power applications on account of their simple structure and modularity [2]. Control algorithms play an important role in implementing high-performance multi-level systems. Model predictive control (MPC) in power electronics is a simple and powerful control strategy that uses a basic yet precise discrete model to represent a power converter with advantages such as, outstanding dynamic performance and multi-objective control.

The idea of MPC is to minimize the cost function of the objectives or the error of the control objectives by selecting the optimal control input in each sampling or control period. In [3], the detailed principle of MPC is described. MPC in power electronics is also called finite control set MPC (FCS- MPC) due to the quantization of the control inputs to the power converter. Different control objectives can be achieved by FCS-MPC. However, a primary drawback of FCS-MPC is its large computational burden. Although the improved computing power of modern digital control platforms enables the development and application of more sophisticated MPC technology to complex power converter topologies [4], a modulator is still required to apply a desired voltage. The modulation method is usually complex when it is implemented for multi-level inverters. In a seven-level (7L) CHB STATCOM, the number of feasible switching states is 343. Moreover, prediction of the control objectives for all of the switching states and their evaluation through cost functions are time consuming. The computational time increases rapidly with additional control objectives, which results in a longer implementation time for the control algorithm. In multilevel CHB STATCOMs, reductions in the control complexity and computational burden has become an important issue for the successful implementation of the FCS-MPC method [5].

Several methods for reducing computation time have been proposed for the FCS-MPC [6]-[11]. An analytic method was proposed to examine the impact of model parametric uncertainties on the prediction error of FCS-MPC for current control in three-phase two-level inverters [6]. However, the mode is not suitable for multi-level inverters. In [7], a field-programmable gate array (FPGA)-based real-time implementation of MPC is presented. However, the optimization and decision-making tasks are time-intensive in implementation. In [8], an FS-PCC method based on a deadbeat solution for three-phase zero-common-mode voltage CHB inverters is proposed. However, a means of balancing the DC side capacitor voltage is not addressed. In [10], an integer least squares method is applied in the multi-step MPC of three-level converters without simulated or experimental results. Moreover, a PWM method for CMV reduction is introduced in [11]. The objective is to balance the dc-link capacitor voltages and to control the flying capacitor voltage. Nevertheless, this method is not applicable to multilevel CHB STATCOMs. The above methods all select a subset of the controllers, with a poorer dynamic response. This is because, in the subsequent sampling period, even a big change can be obtained by the adjacent voltage level of an adjacent CHB STATCOM.

In this paper, an improved SVPWM technique based on FCS-MPC for multilevel CHB inverters to reduce switching states and number of computations is proposed. The partial cost function approach is adopted to sequentially solve the switching states, which can balance dc-link capacitor voltages and track the reference currents. In addition, the proposed five- segment SVPWM based on nonorthogonal static reference frames does not need to calculate trigonometric functions. Thus, the time for the effective calculations decreases. By using these techniques, the dc-link capacitor voltage can be well balanced and the computation time can be reduced. Simulation and experiments were conducted to verify the proposed method.



Ⅱ. CONVENTIONAL FCS-MPC FOR THE CHB STATCOM SYSTEM MODEL


A. CHB STATCOM System Model

Fig. 1 shows a schematic of a three-phase star-connected multilevel CHB STATCOM system. N H-bridge cells are connected in series in each phase, and they are connected to the grid via a series inductor L. In each cell, there are four insulated-gate bipolar transistors (IGBTs) and one dc-link capacitor. The output states for each of the cells can be denoted as an integer variable, Sxi∈{-1,0,1}. Here, it is supposed that the capacitor voltage in each cell is Udc. Then {−1,0,1} represents the H-bridge outputting a positive Udc, 0 and a negative Udc voltage, respectively. In addition, x∈{a, b, c} represents one of the three phases, and i∈{1,2,..n} indicates one of the stages in the cascaded H-bridge string. Then the output voltage for each phase can be defined by:

그림입니다.
원본 그림의 이름: CLP000012140002.bmp
원본 그림의 크기: 가로 662pixel, 세로 88pixel             (1)


그림입니다.
원본 그림의 이름: image1.emf
원본 그림의 크기: 가로 727pixel, 세로 642pixel

Fig. 1. Structure of a multi-level CHB STATCOM.


To avoid an open circuit at the load and a short circuit inside the source, there are 26N admissible switching states for a N H-bridge STATCOM. For example, phase A of a 7L CHB STATCOM has 64 unique switching states, which produces five different voltage levels. Therefore, several duplicate switching states produce the same output voltage level but different impact capacitance voltages. Accordingly, the switching states for each phase switch can be reduced to 3N, as in the 7L CHB STATCOM shown in Table I.


TABLE I SWITCHING STATES FOR A SINGLE-PHASE LEG OF A 7L CHB STATCOM

States

VaN

Function

T1a

T2a

T5a

T6a

T9a

T10a

V1

−3Udc

0

0

1

0

1

0

1

V2

−2Udc

1

0

1

0

1

0

0

V3

−2Udc

1

0

0

0

1

0

1

V4

−2Udc

1

0

1

0

0

0

1

V5

−Udc

2

0

0

0

1

0

0

V6

−Udc

2

0

1

0

0

0

0

V7

−Udc

2

0

0

0

0

0

1

V8

−Udc

2

0

1

1

0

0

1

V9

−Udc

2

1

0

0

1

0

1

V10

−Udc

2

0

1

0

1

1

0

V11

0

3

0

0

0

0

0

0

V12

0

3

0

1

1

0

0

0

V13

0

3

1

0

0

1

0

0

V14

0

3

0

0

1

0

0

1

V15

0

3

1

0

0

0

0

1

V16

0

3

0

0

0

1

1

0

V17

0

3

0

1

0

0

1

0

V18

Udc

4

0

0

1

0

0

0

V19

Udc

4

1

0

0

0

0

0

V20

Udc

4

1

0

1

0

0

1

V21

Udc

4

0

0

0

0

1

0

V22

Udc

4

0

1

1

0

1

0

V23

Udc

4

1

0

0

1

1

0

V24

2Udc

5

1

0

1

0

0

0

V25

2Udc

5

0

0

1

0

1

0

V26

2Udc

5

1

0

0

0

1

0

V27

3Udc

6

1

0

1

0

1

0


Using Kirchhoff’s voltage and current laws, the system model of a CHB STATCOM can be expressed as:

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원본 그림의 이름: CLP000012140003.bmp
원본 그림의 크기: 가로 824pixel, 세로 675pixel        (2)

where, usa, usb and usc are the three-phase grid voltages; 그림입니다.
원본 그림의 이름: CLP000012140004.bmp
원본 그림의 크기: 가로 185pixel, 세로 58pixel are the three-phase currents; the device loss is represented by the equivalent series resistance RS; and uNO is defined as the voltage difference between two neutral points of the device and system voltage.


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원본 그림의 이름: image5.emf
원본 그림의 크기: 가로 686pixel, 세로 520pixel

Fig. 2. Phase model of a CHB STATCOM.


For the CHB STATCOM model shown in Fig. 2, each of the bridge inverter cells can be equivalent to an ac voltage source. In selecting one of the bridge inverter cells as the object of the model, the control of the cells can be simplified to a control circuit model of a single bridge inverter cell, as shown in Fig. 2. The equivalent voltage can be expressed by Kirchhoff’s voltage law as:

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원본 그림의 이름: CLP000012140005.bmp
원본 그림의 크기: 가로 786pixel, 세로 349pixel         (3)

Voltages in a three-phase system can be represented by a rotating vector in the dq coordinate system. The rotating vector can be obtained from the abc coordinates as:

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원본 그림의 이름: CLP000012140006.bmp
원본 그림의 크기: 가로 1426pixel, 세로 214pixel        (4)

where Vd and Vq are the d and q-axis voltages, and θ is the initial phase angle between the rotating coordinate q-axis and the stationary coordinate a-axis, and λ=(2/3)1/2.


B. Conventional FCS-MPC

The conventional FCS-MPC consists of two steps: 1) prediction of the control objective for all of the feasible converter switching states; and 2) evaluation of the predictions in a cost function, as well as selecting the one that minimizes the cost function. In a CHB STATCOM system, the control objectives are to track the reference current, balance the capacitor voltage in each cell, and optimize the switching frequency. With the weighting coefficient method, all of the control objectives can be evaluated by one cost function.

To predict the reference current and capacitor voltage for a given voltage vector, a discrete-time model of a CHB STATCOM is used. To exert a given voltage vector (Vd, Vq) to the inverters in a whole sampling interval Ts, the current of CHB STATCOM at the (k+1)Ts sampling instant can be predicted as:

그림입니다.
원본 그림의 이름: CLP000012140009.bmp
원본 그림의 크기: 가로 1262pixel, 세로 242pixel          (5)

where:

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원본 그림의 이름: CLP000012140008.bmp
원본 그림의 크기: 가로 1466pixel, 세로 328pixel

In (5), id and iq, along with Vd and Vq, are the d and q-axis currents and voltages, respectively. Then the cost function in the standard FCS-MPC can be defined as:

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원본 그림의 이름: CLP00001214000a.bmp
원본 그림의 크기: 가로 1375pixel, 세로 133pixel           (6)

where V*c(k+1) is the reference voltage of the dc-link capacitors, i*d,q(k+1) is the reference current of the dq axis, and g1 and g2 are the weighting coefficients.

Since the number of switching combinations for each of the phases is 3N, the number of total switching combinations in (6) is 33N. Actually, the polarities of the output voltages in any two cells in the same phase must be the same in a real system. Otherwise, the voltages cause extra switching actions. Accordingly, the number of total switching combinations can be reduced to (2N−1)3. If an exhaustive search algorithm is used to solve Eq. (6), all of these combinations should be evaluated, and the computation complexity becomes dependent on time exponentially.



Ⅲ. PROPOSED FCS-MPC FOR CHB STATCOMS

In the conventional FCS-MPC, the multi-objective control problem is transformed into a single-objective problem through weighting coefficients. Although this is valid, a complete enumeration increases the number of computations. In [14], only the non-redundant voltage vectors were analyzed, the periodic index of the exhaustive search method. In fact, one of the factors in [14] is that the computation time for each cycle time is fixed and equal. In this paper, a fast SVPWM method based on FCS-MPC is presented to use redundant vectors to regulate the voltages of the DC-link capacitors and to solve the multi-objective optimization problem.


A. Proposed Cost Function

The idea of the proposed method is to reduce the candidate switching states for the prediction and evaluation in the cost function. For this purpose, the principle of a partially stratified approach is used to divide the conventional cost function into two parts: current tracking and dc-link capacitor voltage balancing. Thus, the optimization problem is divided into two parts. In addition, FCS-MPC is divided into two MPC types: current control MPC and capacitance voltage balance MPC. The weights of the two “new” cost functions are adjusted according to the actual system requirements. The cost function for current control and balancing the capacitor voltage can be defined as:

그림입니다.
원본 그림의 이름: CLP00001214000b.bmp
원본 그림의 크기: 가로 797pixel, 세로 130pixel                             (7)

with:

그림입니다.
원본 그림의 이름: CLP00001214000c.bmp
원본 그림의 크기: 가로 1411pixel, 세로 487pixel     (8)

그림입니다.
원본 그림의 이름: CLP00001214000d.bmp
원본 그림의 크기: 가로 1412pixel, 세로 778pixel      (9)

where:

그림입니다.
원본 그림의 이름: CLP00001214000e.bmp
원본 그림의 크기: 가로 1546pixel, 세로 461pixel

그림입니다.
원본 그림의 이름: CLP000012140010.bmp
원본 그림의 크기: 가로 1122pixel, 세로 333pixel


B. Prediction Vector Selection

The conventional space vector using the orthogonal αβ space coordinate system, where the directions of the α coordinate axis and the a axis are consistent, and the β axis direction is 90 degrees counterclockwise rotation from the a axis. In the αβ coordinate system, it is difficult to get the relationship between the reference space vector Ur and the three sides of the feature triangle. From this point of view, this paper presents the idea of changing the coordinate system.


그림입니다.
원본 그림의 이름: image21.emf
원본 그림의 크기: 가로 262pixel, 세로 219pixel

Fig. 3. Transformations from the abc stationary coordinates to LK stationary coordinates of a 7L CHB STATCOM.


Fig. 3 shows an axis transformation from the abc stationary coordinates to the LK stationary coordinates of a 7L CHB STATCOM, where the L coordinate axis and the α axis are in the same direction, and the K axis direction is 60 degrees counterclockwise rotation from the α axis. Transforming quantities from the abc coordinates into the LK coordinates can be defined in matrix form as:

그림입니다.
원본 그림의 이름: CLP000012140011.bmp
원본 그림의 크기: 가로 1161pixel, 세로 259pixel    (10)

The reference space vector Ur is defined as:

그림입니다.
원본 그림의 이름: CLP000012140012.bmp
원본 그림의 크기: 가로 1194pixel, 세로 169pixel    (11)

The oblique lines L-6, L-5,...L5 and L6 in Fig. 3 are parallel to the K-axis. In the KL coordinate system, each point on the same oblique line has the same projection on the L-axis. The lines can be expressed in simple mathematical expressions as: 그림입니다.
원본 그림의 이름: CLP000012140013.bmp
원본 그림의 크기: 가로 393pixel, 세로 121pixel, 그림입니다.
원본 그림의 이름: CLP000012140014.bmp
원본 그림의 크기: 가로 963pixel, 세로 61pixel. Similarly, the diagonal lines K-6, K-5,...K5 and K6 are parallel to the L-axis and can be expressed in the KL coordinate system as: 그림입니다.
원본 그림의 이름: CLP000012140015.bmp
원본 그림의 크기: 가로 381pixel, 세로 119pixel,그림입니다.
원본 그림의 이름: CLP000012140016.bmp
원본 그림의 크기: 가로 954pixel, 세로 61pixel. If the corresponding space vector for the output state of the inverter-specific is located at the intersection of the oblique lines Lm and Kn, the corresponding characteristic state vector can be expressed as Um,n.


그림입니다.
원본 그림의 이름: image28.emf
원본 그림의 크기: 가로 242pixel, 세로 153pixel

Fig. 4. Vectors employed through a linear combination to generate Vr of the KL coordinates.


The two adjacent oblique lines Lm and Lm+1 with the two adjacent oblique lines Kn and Kn+1 form a diamond. The interior of this diamond contains two characteristic triangles. The vertices of the two feature triangles contain a total of four independent feature state vectors: Um,n, Um,n+1, Um+1,n and Um+1,n+1 as shown in Fig. 4. All of the characteristic triangles can be divided into Type I triangles and Type II triangles. If Ur is in a Type I triangle, then ubc-uab≥(n-m)Udc. If Ur is in a Type II triangle, then ubc-uab≥(n-m)Udc. If Ur is in a Type I triangle, it is synthesized by the eigenvectors Um,n, Um,n+1 and Um+1,n+1, according to the principle of vector synthesis as follows:

그림입니다.
원본 그림의 이름: CLP000012140017.bmp
원본 그림의 크기: 가로 1339pixel, 세로 198pixel      (12)

where tm,n, tm,n+1, tm+1,n+1 are the action times of Um,n, Um,n+1 , Um+1,n+1, respectively. From Eq. (12) it can be obtained that:

그림입니다.
원본 그림의 이름: CLP000012140019.bmp
원본 그림의 크기: 가로 925pixel, 세로 529pixel        (13)

If Ur is in a Type II triangle, it is synthesized by the eigenvector Um,n, Um+1,n and Um+1,n+1. Thus, the action time can be expressed as:

그림입니다.
원본 그림의 이름: CLP00001214001a.bmp
원본 그림의 크기: 가로 927pixel, 세로 526pixel       (14)

Using the five-segment algorithm, the order of switching between Um,n, Um,n+1 and Um+1,n+1 in Fig. 4 is:

그림입니다.
원본 그림의 이름: CLP00001214001b.bmp
원본 그림의 크기: 가로 1205pixel, 세로 70pixel

In a sampling period, waveforms of the phase voltages are obtained by the five-segment SVPWM algorithm and shown in Fig. 5. One of the phase voltages of the three-phase bridge remains unchanged. The other two change two times.


그림입니다.
원본 그림의 이름: CLP000012140018.bmp
원본 그림의 크기: 가로 1493pixel, 세로 503pixel

Fig. 5. Waveforms of the phase voltages are obtained by the five- segment SVPWM algorithm.


The proposed five-segment SVPWM keeps one phase switching unchanged among the three phases in a cycle. During this period, an IGBT of the cell in the middle of this phase can be changed to adjust the voltage of the dc-link capacitor. As a result, the output voltage of this phase is not changed. For example, in Fig. 5, VCa1 can be changed by T2a.

With a focus on the special structure of the FCS-MPC algorithm in a cascaded STATCOM, an improved five -segment SVPWM method based on nonorthogonal static reference coordinates is used. The system obtains the primary predictive switch state combinations Sxi(k+1) according to the switching states Sxi(k) at the time kTs as a unified prediction model to select the switch states. Since it eliminates complex calculations, such as trigonometric functions and square roots, the proposed non-orthogonal coordinate system can reduce the calculations of SVPWM to determine the sector and switching timing. Accordingly, the switch state of a single leg per period is reduced from seven to five, which can also reduce the number of iterations of the new algorithm.


그림입니다.
원본 그림의 이름: CLP00001214001c.bmp
원본 그림의 크기: 가로 1862pixel, 세로 587pixel

Fig. 6. Control diagram of FCS-MPC based on the five-segment SVPWM method.


Fig. 6 shows a control diagram of the proposed FCS-MPC method. The underlying meaning of the voltage balancing of the MPC is to adjust all of the capacitor voltages by selecting optimal switching combinations from all of the redundant vectors. In the proposed method, the optimization can be expressed as:

그림입니다.
원본 그림의 이름: CLP00000e3c475f.bmp
원본 그림의 크기: 가로 479pixel, 세로 315pixel               (15)

Tradeoffs among the system control objectives must be made when the control objectives reside in different cost functions. In this case, current control has the highest priority. Considering the discrete system models in Eq. (3) and the classic control strategies for STATCOMs, the redundant vectors do not affect the currents and can be further utilized to adjust the capacitor voltages at a later time. Therefore, the partial cost function approach can be adopted to sequentially solve the reference currents or load currents and the capacitor voltage control.


C. Control Procedure

To further elucidate the proposed method, the steps for the proposed FCS-MPC for a CHB-STATCOM can be summarized as follows:

Step 1: Measure the currents, the voltages of the grid, the currents of the load and the compensation currents (CHB-STATCOM currents).

Step 2: Employ the optimal vector determined during the previous control interval.

Step 3: Estimate the reactive power.

Step 4: Predict the reference voltage, reference current and dc-link capacitor voltage.

Step 5: Select three active vectors.

Step 6: Predict the switch states, the difference between the reference current and the device current for the selected active vectors, and the redundant voltage vector for the dc-link capacitor voltage.

Step 7: Evaluate the predicted variables through the cost function and determine the vectors that minimize them.

Step 8: Use the proposed five-stage SVPWM algorithm to generate the switching signals of the IGBTs and the execution timing.

Therefore, the total computation burden can be slightly reduced with the partial cost function approach. Moreover, after transforming the optimization problem of FCS-MPC into the optimizations of two simple sub-problems, the proposed five-segment SVPWM method based on nonorthogonal static reference coordination is adopted to reduce the total computation.



Ⅳ. SIMULATION AND EXPERIMENTAL RESULTS


A. Simulation Results

In the MATLAB 2014a environment, a simulation model of the control system of a 7L CHB STATCOM was tested. The simulation parameters are listed in Table II. To provide a fair and valuable reference, all of the simulation results are shown under the same parameters and conditions.


TABLE II PARAMETERS OF 7L CHB STATCOM SYSTEMS

Descriptions

Values

Descriptions

Values

Line-voltage RMS

3.3KV

Parallel resistor

560KΩ

AC voltage frequency

50Hz

Sample period

100 µs

Current reference(peak)

200A

Dead time

4 µs

Cascaded stages

7

AC inductance

2.5mH

DC-link capacitor

9mF

DC voltage reference

1100V


Fig. 7 shows simulation waveforms obtained by the proposed optimization method on a three-phase 7L CHB STATCOM system with a maximum reactive power of 1.2Mvar. Fig. 7(a) shows voltage and compensation current waveforms of a STATCOM. Fig. 7(b) shows system current, load current and compensation current waveforms. In addition, Fig. 7(c) shows the average capacitor voltages of the three phases. Moreover, the capacitor voltages of the H-bridge cells in Phase-A are presented in Fig. 7(d). It can be observed that the capacitor voltage ripple is around ±50V and that the ripple frequency is 100Hz. Both the capacitor voltages in the same phase and between different phases can be well regulated.


Fig. 7. Simulation waveforms of a 7L CHB STATCOM system.

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원본 그림의 이름: image35.png
원본 그림의 크기: 가로 752pixel, 세로 337pixel

(a)

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원본 그림의 크기: 가로 749pixel, 세로 362pixel

(b)

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원본 그림의 이름: image37.png
원본 그림의 크기: 가로 731pixel, 세로 335pixel

(c)

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원본 그림의 이름: image38.png
원본 그림의 크기: 가로 756pixel, 세로 342pixel

(d)


Fig. 8 shows instantaneous compensational current and power factor waveforms of the standard FCS-MPC and the proposed fast FCS-MPC under load currents from 300Ap-p to 500Ap-p. Since the switch states and the switching frequency are reduced, the STATCOM device itself consumes less power. As shown in Fig. 8, the proposed method achieves a higher power factor for the system. Thus, the proposed MPC scheme can improve the overall control performance and response speed of the system under the condition of a good compensation current. In addition, it is strongly suitable for practical applications.


Fig. 8. Simulation waveforms of the conventional FCS-MPC and the proposed fast FCS-MPC for a STATCOM: (a) Power factor; (b) Compensational current.

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B. Experimental Results

To further evaluate the performance of the proposed FCS- MPC method, an experimental platform was established as shown in Fig. 9. The experimental setup mainly consists of nine cells with a 200Arms output current capability running at a 3.3KV grid voltage. Each cell included four IGBTs, a CPLD, four fiber optic transceivers, drive circuits, and a protection circuit. The AD samplings, control algorithms and drive signal generation were implemented in a digital signal processor model FPGA, while a DSP was used to implement the process control and touch screen communication. DSP+ FPGA+CPLD are a good combination among the best solutions for the real-time implementation of the FCS-MPC method since the discrete nature of the predictive controller fits well with the architectures of FPGA and CPLD devices.


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Fig. 9. Experimental setup and controller.


The output currents of a 7L CHB STATCOM are shown in Fig. 10. The output current waveforms of the device are good, and the deviation between the actual output reactive power and the set value is less than 2.5%.


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Fig. 10. Output current waveforms of the device for a STATCOM at the steady state.


In the step response performance test of a STATCOM, the device output current was adjusted from 0A to +150A or −150A. Test waveforms are shown in Fig. 11. The system quickly tracks the load reactive power when the load current suddenly changes. The response time of the traditional MPC algorithm is to 3 ms. Meanwhile, that of the proposed method has a better response time since it is close to 1 ms. This makes the response time of the 7L CHB STATCOM system shorter.


Fig. 11. Output current waveforms from 0A to +150A or −150A of the device for a STATCOM: (a) Conventional FCS-MPC; (b) Proposed fast FCS-MPC.

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Fig. 12 shows load current, grid voltage (the ratio of the potential transformer between the grid and the oscilloscope is 3300V/100V), and compensation current waveforms at full capacitive reactive power. The obtained experiments results show that the device can perform real-time compensation regardless of the inductive reactive power or capacitive reactive power load.


Fig. 12. Current and voltage waveforms of Phase A: (a) Load current and grid voltage of Phase A; (b) Grid voltage and compensation current of Phase A.

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Ⅴ. CONCLUSIONS

A computationally fast FCS-MPC based the five-segment SVPWM for CHB-STATCOMs was proposed in this paper. It reduces the number of voltage vectors for the prediction and evaluation in the cost function without complex calculations in selecting the vector for prediction. A partial cost function approach was used to sequentially solve the current and capacitor voltage control.

The FCS-MPC algorithm was used in the implementation of parallel computing to reduce the time of the calculations performed in the FPGA. Furthermore, output current waveforms with the proposed approach showed good compensation and tracking effects. Moreover, the capacitor voltage can be well balanced during a shorter time, which was validated by both simulation and experimental results.



ACKNOWLEDGMENT

The authors gratefully acknowledge the National Key R&D Project of China (Grant NO.2016YFB0900405) for its financial support.



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Xiuqin Wang was born in Xiaoxian, China. She received her B.S. and M.S. degrees from Anhui University, Hefei, China, in 2011 and 2014, respectively. She is presently working towards her Ph.D. degree in the School of Electrical Engineering and Automation, Anhui University. Her current research interests include high-power electronic systems and power electronics in power systems.


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Jiwen Zhao was born in Dangshan, China. He received his Ph.D. degree from the University of Science and Technology of China, Hefei, China, in 2005. Since May 2006, he has been working in the School of Electrical Engineering and Automation, Anhui University, Hefei, China, where he is presently working as a Professor in the School of Electrical Engineering and Automation. His current research interests include linear motor optimization design, linear motor control and photoelectric detection technology.


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Qunjing Wang was born in Bengbu, China, in1960. He received his Ph.D. degree from the Department of Precision Machinery and Precision Instrumentation, University of Science Technology of China, Hefei, China, in 1998. From 1983 to 2007, he was with the Hefei University of Technology, Hefei, China. Since 2007, he has been working as a Professor and a Vice-President at Anhui University, Hefei, China. In addition, he is serving as a Research Chair Professor in the National Engineering Laboratory of Energy-Saving Motor and Control Techniques, Anhui University; the Power Quality Engineering Research Center of the China Ministry of Education, Anhui University; the Provincial Collaborative Innovation Center of Industrial Energy-Saving and Power Quality Control, Anhui University; and the Energy-Saving Research Institute, Hefei University of Technology. His current research interests include motors and drives, converter technology, power quality, and microgrids.


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Guoli Li was born in Taizhou, China, in 1961. She received her Ph.D. degree from the Hefei Institutes of Physical Science, Chinese Academy of Sciences, Hefei, China, in 2006. From 1983 to 2007, she was with the Hefei University of Technology, Hefei, China. From 1983 to 2007, she was a Professor and a Vice-President at the Zhejiang University of Technology, Zhejiang, China. Since 2010, she has been working as a Professor in the School of Electrical Engineering and Automation, Anhui University, Hefei, China. Her current research interests include motor optimization design and industrial robot design.


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Maosong Zhang was born in Hubei, China, in 1984. He received his B.S. and Ph.D. degrees in Electrical Engineering from Wuhan University, Wuhan, China, in 2006 and 2011, respectively. In 2012, he was a Postdoctoral Researcher in the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI, USA. Since 2013, he has been working as a Lecturer in the College of Electrical Engineering and Automation, Anhui University, Hefei, China. His current research interests include high-power electronic systems and power electronics in power systems.