https://doi.org/10.6113/JPE.2019.19.2.509

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Comparison of Three Active-Frequency-Drift Islanding Detection Methods for Single-Phase Grid-Connected Inverters

Jia-rong Kan^†, Hui Jiang^*, Yu Tang^**, Dong-chun Wu^*, Yun-ya Wu^*, and Jiang Wu^***

^†,*Department of Electrical Engineering, Yancheng Institute of Technology, Yancheng, China

^**Department of Electrical Engineering, Hebei University of Technology, Tianjin, China

^***Suzhou Power Supply Company, National Grid Jiangsu Electric Power Co., Suzhou, China

Abstract

A novel islanding detection method is proposed in this paper. It is based on a frequency drooping PLL, which was presented in a previous work. The cause of errors in the non-detection zone (NDZ) of conventional frequency disturbance islanding detection methods (IDM) is analyzed. A frequency drooping phase-locked-loop (FD-PLL) is introduced into a single-phase grid-connected inverter (SPGCI), which can guarantee that grid current is in phase with the grid voltage. A novel FD-PLL IDM is proposed by improving this PLL. In order to verify the performance of the proposed FD-PLL IDM, a full performance comparison between the proposed IDM and typical existing active frequency drift IDMs is carried out, which includes both dynamic performance and steady performance. With the same NDZ, the total harmonic distortion of the grid-current in the dynamic process and steady state is analyzed. The proposed FD-PLL IDM, regardless of the dynamic or steady process, has the best power quality. Experimental and simulation results verify that the proposed FD-PLL IDM has excellent performance.

Key words: FD-PLL, IDM, NDZ error, Power quality, SFS, Single-phase grid-connected inverter (SPGCI), SMS

Manuscript received Jul. 15, 2018; revised Nov. 10, 2018

Recommended for publication by Associate Editor Kai Sun.

^†Corresponding Author: kanjr@163.com Tel: +86-515-88168194, Fax: +86-515-88168666, Yancheng Inst. Tech.

^*Dept. of Electrical Eng., Yancheng Institute of Technology, China

^**Dept. of Electrical Eng., Hebei University of Technology, China

^***Suzhou power supply company, National grid Jiangsu Electric Power Co., China

Ⅰ. INTRODUCTION

In distributed generation (DG) systems, the islanding protection function is mandated according to IEEE 929 and 1547 standards [1], [2]. If islanding operation occurs and a DG is not broken away from the utility grid in a timely manner, there are a number of negative impacts on the network and the DG itself, such as safety hazards to utility personnel and the public, power quality problems, and serious damage to the utility grid and DG systems [3], [4]. Another condition is when a DG system is operated in the islanding mode after a power failure, which makes it necessary for the DG system to break away from the grid utility [4]. Therefore, researchers have been working to seek an islanding detection method (IDM) without a non-detection zone (NDZ) or with small NDZ [5]. NDZs can be defined as loading conditions for which an IDM fails to operate in a timely manner. However, some IDMs known as ‘no NDZ’ depend on the control performance of a single-phase grid-connected inverter (SPGCI) in practical operation [6].

IDMs can be classified into three categories: ① passive IDMs, ② active IDMs and ③ communication-based IDMs. The conventional passive IDMs generally detect the amplitude or frequency of the voltage at the point of common coupling (PCC) and suffer from a larger NDZ when compared with active IDMs. The novel passive IDM in [7] detects ripple voltage at the switching frequency to determine islanding, which utilizes different impedance characteristics in both the grid-tied mode and the islanding mode. However, accurate and quick detection of ripple voltage at the switching frequency is hard work for digital signal processor (DSP).

The communication-based IDMs modulate the utility voltage signal into the power line through an additional device. Therefore, communication-based IDMs have almost no NDZ. The shortcomings of this method are its high cost and the fact that it is fitted for micro-grids composed of a lot of DG systems [8].

Active IDMs [9] have been widely researched and used due to their small NDZ and low cost. A certain parameter disturbance is injected into the system and then the controller detects the PCC voltage to determine whether the grid is operated under the normal condition. These disturbance parameter injections can be composed of current [10]-[12], active or reactive power [13], [14], frequency [15]-[19], etc. It is believed that frequency parameter disturbances cause the least problems with respect to transient response and power quality at high penetration levels due to the fact that the frequency tends to be a very tightly regulated parameter in power systems when compared with the amplitude and phase [19].

The frequency parameter disturbance active IDMs include active frequency drift (AFD) [15], slide-mode frequency shift (SMS) [16] and Sandia frequency shift (SFS) [17]-[19]. The SMS and SFS methods are widely used due to their small NDZ [15]. The disturbance parameter must be increased if a smaller NDZ is needed, which degrades the power quality of the grid-current [13]. Moreover, some inherent problems [20], such as the phase difference between the grid-voltage and the grid current, affect the accuracy of the NDZ and its causation is analyzed in this paper. To obtain a new active IDM with a small NDZ and a high power quality, a method based on a frequency drooping phase-locked-loop (FD-PLL) has been proposed. When compared with SMS and SFS IDMs, the proposed FD-PLL IDM appears to be less affected by phase differences and the inverter has the best power quality in both the dynamic process and the steady state.

The paper is organized as follows. Section II analyzes the cause of NDZ errors in conventional SMS and SFS IDMs. Section III presents the FD-PLL to overcome the phase detecting time delay, and a phase disturbance is introduced into the FD-PLL to form a new FD-PLL IDM. Section IV analyzes the power quality of a SPGCI controlled by different IDMs with the same NDZ. Simulation results are given in Section V. Finally, some conclusions are given in Section VI.

Ⅱ. NDZ Errors of SMS and SFS IDMs

A. SPGCI and its Control Strategy

According to the IEEE Standard 929–2000, a non-isolated inverter is one that ceases to energize the utility line under certain conditions using a test circuit with a parallel RLC load, as shown in Fig. 1(a), where the DC bus voltage U_D is supplied by a renewable resource, L_f is the filter inductor, u_G and i_G are the grid voltage and current, and u_PCC is the PCC voltage. The SPGCI can achieve a unity power factor through an appropriate control strategy.

Fig. 1. Circuits used for assessing the anti-islanding features of a SPGCI and its control diagram. (a) Circuit topology. (b) Control diagram.

(a)

(b)

Fig. 1(b) shows a control block diagram of a SPGCI with grid voltage feed-forward control, where I_G^* and i_G-u are the amplitude and phase of the reference grid current i_G. In addition, i_G^* is the reference value of i_G, and k_p and k_i are the proportional and integral parameter of the current-loop. Furthermore, K_PWM and K_N are the inverter voltage gain and the grid-voltage feed-forward coefficient, respectively. Note that the PLL detects the frequency of the grid voltage (f_G) and the phase information.

B. Cause of Phase Difference between u_PCC and i_G

If K_N = 1/ K_PWM, the grid current i_G is affected by the grid voltage, and the closed-loop transfer function is as follows:

         (1)

If the PLL can guarantee that the reference current i_G^* is in phase with u_PCC, the phase difference (θ_lag) between u_PCC and i_G can be expressed as (2) after the Laplace variable ‘s’ is substituted by ‘jω’.

       (2)

According to (2), L_f, k_p and k_i can affect the value of θ_lag. In [20], the curves for θ_lag with different parameters are given. Therefore, theoretically, the phase difference between u_PCC and i_G is inevitable without attaching an additional phase compensation method. Moreover, if the phase detection time delay of the PLL is considered, θ_lag cannot be ignored.

C. NDZ Error of SMS IDM

The SMS IDM applies positive feedback to the phase of the voltage at the PCC by changing the phase of i_G^* [15].

          (3)

            (4)

where f_pcc-k−1 is the grid frequency in the last line cycle, f_m is the frequency when the maximum phase shift θ_m occurs, and f_G is the rated frequency of the utility grid.

To the parallel RLC load, its quality factor Q_f and phase angle θ_load are:

                (5)

                      (6)

where f_r is the resonant frequency of the load and its value is .

According to the analysis mentioned in Section II-B, there is a phase difference θ_lag between i_G^* and i_G. Thus:

       (7)

Therefore, θ_lag counteracts a part of the function of θ_SMS. The sketch of the phase angle is shown in Fig. 2 with the parameters shown in Table I. When θ_lag=0, as shown in Fig. 2(a), the PCC frequency may stabilize at point A1 or A2 after islanding occurs, which is determined by the initial polarity of (θ_SMS + θ_load). However, if θ_lag≠0, as shown in Fig. 2(b), the condition is quite different from that of θ_lag=0. When the initial frequency is at point A4 after islanding, the PCC frequency finally stabilizes at point A3 because the initial value of (θ_SMS + θ_{load -}θ_lag) is less than zero. However, when the initial frequency is at point A5, the frequency at the PCC finally stabilizes at point A6 because the initial value of (θ_SMS + θ_load- θ_lag) is greater than zero. It can be seen that the frequency at point A6 is less than that at point A2. The final frequency can be located in the normal frequency range if θ_lag is big enough. This shows that the range of the NDZ can be affected by the phase θ_lag.

TABLE I LOAD AND DISTURBANCE PARAMETERS

Parameter		Value
load		31.1Ω
		0.038Η
		267μF
		2.6
		50Hz
		2°

Fig. 2. Phase angle sketch of different conditions. (a) θ_lag=0°. (b) θ_lag=1°.

(a)

(b)

The rule for plotting the NDZ is (θ_load – θ_lag + θ_SMS)=0. Therefore, according to [6], it is possible to obtain:

       (8)

To achieve the NDZ of the SMS IDM when θ_lag≠0, the islanding frequency is first adjusted to the threshold frequency (49.3 or 50.5). NDZs with θ_lag=0 and θ_lag=2° are shown in Fig. 3. It can be seen that the NDZ of θ_lag=0 is smaller in size than that of θ_lag≠0°. Moreover, the NDZ deviates from the routine analysis in many studies [15] when θ_lag≠0°.

Fig. 3. NDZ with consideration of θ_lag.

D. NDZ error of SFS IDM

The reference current of an inverter using the SFS IDM is:

         (9)

The relationship between the voltage and the current is shown in Fig. 4.

Fig. 4. Current and voltage waveforms in the SFS IDM.

In a half line cycle, the time interval of the zero current is t_z. Therefore, the phase θ_SFS, where the grid current leads the PCC voltage, is equal to . The truncation factor c_f is defined as:

                        (10)

   (11)

According to [17], the truncation factor c_f is:

                          (12)

Therefore, θ_SFS becomes:

                     (13)

Like the condition in the SMS IDM, the rule for plotting the NDZ is that (θ_load–θ_lag+θ_SFS)=0. Thus, the NDZ of the SFS IDM is similar with that of the SMS IDM when θ_lag≠0. Therefore, it is not repeated here.

Ⅲ. FREQUENCY DROOPING PLL AND FD-PLL IDM

A. Frequency Drooping PLL

The error NDZ is caused by the phase angle θ_lag between u_PCC and i_G. This phase angle θ_lag is difficult to eliminate since it is an open-loop controlled parameter. In order to realize θ_lag=0, this parameter must be introduced into the control.

Fig. 5. Control block diagram based on a FD-PLL and an equivalent control block diagram of the FD-PLL. (a) Control block diagram. (b) Equivalent control block.

(a)

(b)

Fig. 5(a) shows the FD-PLL for a SPGCI. When compared with the PLL used in Fig. 1(b), the FD-PLL has the frequency drooping characteristic. Setting γ is that the phase angle where the grid current i_G is ahead of the PCC voltage u_PCC. Therefore:

                         (14)

The frequency of i_G* is determined by the frequency of u_PCC and . In the initial time of every line cycle, can be detected as well as the grid voltage frequency f_PCC in the last cycle. The frequency of i_G* in the following cycle can be determined by (15).

             (15)

Where k_f is drooping coefficient, and is positive when i_G leads u_PCC. If is negative, i.e. u_PCC is phase-leading, the frequency of i_G* in the next line cycle is greater than the frequency of u_PCC according to (15). Thus, is decreased in next line cycle. Finally, trends to zero. When is positive, the operation process can be interpreted in a similar way. Following the function of (15), the current i_G is in phase with u_PCC in steady state without any phase difference.

In order to realize fast phase-tracking, the drooping coefficient k_f should be well designed. The detailed design process can be seen in [20], and its expression is:

                   (16)

In order to ensure the stability of phase-tracking, k_f should be less than the expression in (16).

B. Essence of the FD-PLL

From and f_PCC, the frequency of i_G* in next line cycle can be achieved. Then, at any time t_x, the amount of the phase difference reduction can be expressed as:

        (17)

where t₀ is the initial time of a line cycle. In the steady state, the frequency in the two adjacent line cycles can be viewed as equivalent. Therefore:

                (18)

                (19)

It can be shown that the shrinking of (θ_lag) is the product of 2πk_f and the integral of the last changing with time. Therefore, the essence of the FD-PLL is a phase adjustment control outer-loop, where the feedback variable is and the reference value is zero. An equivalent control block diagram is shown in Fig. 5(b).

C. FD-PLL IDM

The phase difference (θ_lag) can be eliminated by using a FD-PLL. If islanding occurs, (θ_lag) trends to zero since (θ_lag) is a closed-loop feedback parameter as shown in Fig. 5(b). Thus, paralleled RLC loads whose resonant frequency is within the normal frequency range (49.3-50.5) regardless of the quality factor Q_f, are all located in the NDZ (the zones between the dash lines L1 and L2 in Fig. 3). In this case, the NDZ is too large.

According to (3) and (15), the current reference of the improved SMS IDM is:

       (20)

After using (20), the NDZ is in accordance with the normal analysis. However, the disturbed phase angle θ_SMS still affects the quality of the grid current due to the phase changing caused by the frequency fluctuation. The IDM proposed in this paper modulates the phase angle disturbance into frequency regulation to realize a small NDZ, which can avoid the phase hopping of the reference grid current and improve the power quality of the grid current. The reference current of the proposed IDM is:

     (21)

The method in (21) is a FD-PLL IDM. Eq. (21) only adjusts the frequency, which is different than that of the frequency regulation mode in the SFS IDM. In the SFS IDM, the current reference holds zero for a time interval during every positive and negative half cycle. However, the frequency regulation in (21) is similar to that of the frequency drooping control in a microgrid [22] and the reference current is a continuous sinusoidal waveform.

According to (21), ( - θ_SMS) becomes the closed-loop controlled parameter. Thus, ( - θ_SMS) must equal to zero in the steady state. Therefore:

       (22)

The NDZ of the FD-PLL IDM can be obtained according to (22), which is same as that of the SMS IDM analyzed in [15] if θ_lag=0. Although the two IDMs have the same NDZs, the FD-PLL IDM eliminates the effect of the lagging phase angle and improves the power quality of the grid current, which is discussed in Section IV.

Ⅳ. POWER QUALITY ANALYSIS OF THREE DIFFERENT IDMS

A. Dynamic Response Condition

According to Eqns. (3), (9) and (21), Fig. 6 shows an example of the reference current dynamic regulation process of three IDMs when the utility grid frequency fluctuates in the grid-connected mode. Before t_a, the utility grid frequency is at the rated frequency f_G. There is no disturbance at this moment according to (4) and (21). For the sake of a convenient analysis, assume the utility grid frequency becomes f_PCC1 (>f_G) in two successive line cycles after t_a.

Fig. 6. Reference currents and their spectrums in the dynamic regulation process of three IDM methods with the same NDZ. (a) Dynamic waveforms. (b) SFS IDM. (c) SMS IDM. (d) FD-PLL IDM.

(a)

(b)

(c)

(d)

According to the mathematic relationship in Fig. 6(a), the reference equation can be obtained. Equations (23), (24) and (25) are the reference currents of the SFS, SMS, FD-PLL IDMs, respectively.

      (23)

       (24)

    (25)

It can be seen that there is phase hopping in the SFS and SMS IDMs. Meanwhile, in the FD-PLL IDM, the phase changes continuously.

In order to compare the power quality of the three IDMs, the NDZ of these IDMs should be consistent. If the three IDMs have the same NDZ, (26) must be satisfied.

                   (26)

Table II shows a set of data, which nearly meets (26).

TABLE II DATA SET WITH THE SAME NDZ

	SFS	SMS	FD_PLL
Parameters	k=0.1 fG=50Hz	θm=0.0375π fm=51Hz fG=50Hz	θm=0.0375π fm=51Hz fG=50Hz kf =8

In Fig. 6(b) to Fig. 6(d), waveforms and spectrums of the reference current of the three IDMs are plotted according to (23), (24) and (25), respectively. It can be seen that the FD-PLL IDM proposed in this paper has the smallest THD value under the condition of the same NDZ. Therefore, the proposed IDM has the highest power quality in terms of the dynamic process.

B. Steady State

When compared with the dynamic process, the reference currents of the three IDMs in the steady state are relatively simple. It is assumed that the frequency of the grid voltage in the steady state is f_PCC. Eqns. (27) and (28) show the reference current expressions when f_PCC is greater than or less than the rated frequency under the SFS IDM control.

where .

   (27)

                    (28)

According to the abovementioned analysis, the reference currents of the SMS IDM and FD-PLL IDM are equal in the steady state. In other words, the phase angle at the end of the last cycle is equal to the phase angle at the beginning of the next cycle. There is no phase hopping in the steady state under the control of the SMS IDM. The reference current is a continuous function and it is expressed as:

       (29)

According to (27), (28) and (29), the THD values of the reference current under the three IDMs are shown in Fig. 7. It can be seen that there is almost no distortion when the inverter is controlled by the SMS and FD-PLL IDMs. However, the quality of the grid current with the control of the SFS IDM deteriorates when f_PCC is far from the rated frequency and the distortion degree is proportional to the drift value.

Fig. 7. Reference current THD values of the three IDMs in the steady state.

Ⅴ. SIMULATION AND EXPERIMENTAL VERIFICATION

Simulation models of the three IDMs are built using MATLAB/Simulink with the data listed in Table II and a 2kW prototype is established. Not all of the theoretical analysis is verified by experimental results due to laboratory limitations.

Fig. 8 shows frequency varying experimental curves of the three IDMs with the load listed in Table I after islanding occur. All three IDMs can detect the islanding promptly and accurately.

Fig. 8. Frequency changing experimental curves of three IDMs after islanding occurs. (a) SFS. (b) SMS. (c) FD-PLL.

(a)

(b)

(c)

If the utility frequency is at its rated value, no disturbances are added into the grid reference current for the three IDMs. Thus, the power qualities of the grid currents are the same when f_PCC = f_G. However, the power quality changes if the utility grid frequency deviates from its rated value. Fig. 9 shows experimental waveforms of grid currents controlled by the different IDMs when the utility grid frequency is operated at 50.4Hz, which is located in the normal frequency range. It can be seen that grid current quality of the inverter controlled by the SFS IDM is heavily affected by utility grid frequency deviations. There is almost no low-order harmonics in grid currents in the SMS and FD-PLL IDMs. In addition, the THD value (4.7%) is mostly from harmonics near the switching frequency. In the SFS IDM, the disturbance parameter is the length of the zero current. The reference grid current is distorted when the utility grid frequency deviates from its rated value. Meanwhile, in the SMS IDM, the disturbance parameter is the phase angle of i_G* and the value of i_G* at the end of the last cycle is equal to the value of i_G* at the initial time of the next cycle. In the FD-PLL IDM, the phase of i_G* is not determined by the utility voltage, and i_G* is designed continuously in two neighboring line cycles.

Fig. 9. Experimental waveforms of the grid current of three IDMs when the utility grid frequency operates at 50.4Hz. (a) SFS. (b) SMS. (c) FD-PLL.

(a)

(b)

(c)

Fig. 10 shows simulation spectrums of grid currents for the different IDMs with the load listed in Table I when the utility grid frequency hops from 50Hz to 50.4Hz. The power quality of the SMS IDM is heavily affected by frequency hopping. The SFS IDM comes in second and the power quality of FD-PLL IDM appears to be less effected by frequency hopping. The cause and changing processing are analyzed in Section IV, and the simulation results are consistent with the analysis results.

Fig. 10. Waveforms and spectrums of the grid current of three IDMs when the utility grid frequency has a pop change. (a) SFS. (b) SMS. (c) FD-PLL.

(a)

(b)

(c)

A summary of the simulation results for the three IDMs is shown in Fig. 8 and Fig. 9. The FD-PLL IDM proposed in this paper, has the best grid current quality when compared with the SMS IDM and the SFS IDM, regardless of the steady state or dynamic process.

According to the analysis in Section II, the detecting time delay or control parameter effect results in the NDZ error to the SFS and SMS IDMs. However, the phase difference between the grid current and the PCC voltage is detected and it is controlled by a closed-loop. Therefore, the FD-PLL IDM has immunity to the phase detecting delay or control parameter effect. If the load parameter is located in the error zone, for example, f_r=50.2Hz and Q_f=5 (the error point in Fig. 3), the SFS and SMS IDMs cannot detect islanding when θ_lag=2°. However, the FD-PLL can detect islanding regardless of the time delay in the phase detecting process. Fig. 11 shows the frequency varying curves of the three IDMs with θ_lag=0°or θ_lag=2°, which is the same as the theoretical analysis.

Fig. 11. Frequency varying experimental curves of three IDMs with or without a time delay. (a) SFS. (b) SMS. (c) FD-PLL.

(a) (b) (c)

When compared with the SFS and SMS IDMs, the FD-PLL IDM has the best performance, regardless of the islanding detecting accuracy or grid current quality.

Ⅵ. CONCLUSION

The conventional frequency disturbance methods, SMS and SFS IDMs, have a number of shortcomings such as an error detecting NDZ and low power quality. In order to overcome these shortcomings, this paper presents a new IDM based on the FD-PLL, which can overcome the effects of both the phase detection delay and control parameter variations. It can also realize unity power factor at the PCC. The emphasis of this paper is to compare the performance of the proposed IDM with those of existing IDMs. The proposed FD-PLL IDM has the best dynamic performance according to the THD values of a SPGCI under the condition of the same NDZ. The FD-PLL and SMS IDMS have the same steady performance. However, the SFS IDM has the worst performance, regardless of the dynamic or steady performance. Moreover, the FD-PLL IDM can solve the error NDZ problem caused by the phase detection delay or control parameter effect. Simulation and experimental results verify the analysis in this paper. The new FD-PLL IDM can be adopted in renewable energy generation systems.

ACKNOWLEDGMENT

This work was supported by National Nature Science Foundation of China (Grant No.51577164), the Fifth ‘333 Project’ in Jiangsu Province, ‘Six Talent Peaks Project’ in Jiangsu Province(XNY-045) and ‘Qinglan Project’ in Jiangsu Province.

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Jia-rong Kan was born in Jiangsu, China, in 1979. He received his M.S. degree in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2007. He joined the School of Electrical Engineering, Yancheng Institute of Technology, Yancheng, China, in 2007, where he is presently working as an Associate Professor. He is the holder of five patents and is the author or coauthor of more than 40 technical papers. His current research interests include power electronics in renewable energy generation.

Hui Jiang was born in Hunan, China. She received her B.S. degree in Electrical Engineering from the University of South China, Hengyang, China, in 2017. She is presently working towards her M.S. degree at the Hebei University of Technology, Hebei, China. Her current research interests include power electronics and control, which include DC drives and interleaved forward converters for power applications.

Yu Tang received his B.S. and Ph.D. degrees in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2003 and 2008, respectively. He joined the Department of Electrical Engineering, NUAA, in 2008, where he is presently working as an Associate Professor. He has published more than 50 papers in journals and conference proceedings, and holds two Chinese patents. His current research intrests includes power electronics in renewable energy generation.

Dong-chun Wu was born in Jiangsu, China, in 1975. He received his M.S. degree in Material Processing Engineering from Hohai University, Nanjing, China, in 2007. He joined the School of Electrical Engineering, Yancheng Institute of Technology, Yancheng, China, where he is presently working as an Associate Professor. He is the author or coauthor of more than 20 technical papers. His current research interests include power electronics in renewable energy generation and computer control technology.

Yun-ya Wu was born in Jiangsu, China, in 1979. She received her M.S. degree in Computer Technology from the Nanjing University of Science and Technology, Nanjing, China, in 2010. She joined the School of Electrical Engineering, Yancheng Institute of Technology, Yancheng, China, in 2001, where she is presently working as a Lecturer. Her current research interests include control strategies for the grid-connected inverters in microgrids.

Jiang Wu was born in Shandong, China. He received his B.S. degree from Shandong University, Jinan, China, in 2013. From 2013 to 2017, he was a Junior Electrical Engineer for the State Grid of China. From 2017 to 2018, he worked as a Senior Electrical Engineer for the State Grid of China. His current research interests include power electronics and control, which include the fault diagnosis of electrical machines, new energy generation and control technologies, and relay protection technology of power systems.