사각형입니다.

https://doi.org/10.6113/JPE.2019.19.3.645

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Analysis and Implementation of High Step-Up DC/DC Convertor with Modified Super-Lift Technique


Rezvan Fani, Ebrahim Farshidi*, Ehsan Adib**, and Abdolnabi Kosarian*


†,*Department of Electrical Engineering, Faculty of engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran

**Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran



Abstract

In this paper, a new high step up DC/DC converter with a modified super-lift technique is presented. The coupled inductor technique is combined with the super-lift technique to provide a tenfold or more voltage gain with a proper duty cycle and a low turn ratio. Due to a high conversion ratio, the voltage stress on the semiconductor devices is reduced. As a result, low voltage ultra-fast recovery diodes and low on resistance MOSFET can be used, which improves the reverse recovery problems and conduction losses. This converter employs a passive clamp circuit to recycle the energy stored in the leakage inductance. The proposed convertor features a high conversion ratio with a low turn ratio, low voltage stress, low reverse recovery losses, omission of the inrush currents of the switch capacitor loops, high efficiency, small volume and reduced cost. This converter is suitable for renewable energy applications. The operational principle and a steady-state analysis of the proposed converter are presented in details. A 200W, 30V input, 380V output laboratory prototype circuit is implemented to confirm the theoretical analysis.


Key words: Coupled inductor, DC-DC convertors, High step up converter, Non-isolated technique, Super-lift technique


Manuscript received Jun. 17, 2018; accepted Jan. 26, 2019

Recommended for publication by Associate Editor Dukju Ahn.

Corresponding Author: r-fani@stu.scu.ac.ir Tel: +98-61-3333-0011, Fax: +98-61-3333-2024, Shahid Chamran University of Ahvaz

*Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Iran

**Department of Electrical and Computer Engineering, Isfahan University of Technology, Iran



Ⅰ. INTRODUCTION

Nowadays, the utilization of renewable energy sources is expanded more and more due to their clean and cost-effective features [1], [2]. However, renewable energy sources such as photovoltaic panels, fuel cell, etc. provide a low DC voltage (typically lower than 50 V). In order to connect these sources to an AC load or network, the output voltage should be increased to a higher voltage level (typically 300V-400V). The conventional boost converter cannot provide such a high conversion ratio due to the high voltage stress on the switch and extreme operating duty cycle problems [3], [4]. Thus, DC/DC high step up converters are required. These converters are applied in other applications such as high-intensity discharge lamps (HID) for automobile headlamps, battery backup systems for uninterrupted power supplies (UPS) and power supplies in the telecommunication industry [3], [5].

Several techniques having been presented in the literature to provide a high voltage gain such as the voltage-lift or/and voltage-multiplier technique, cascading techniques, employing transformers and coupled inductors, etc. [6], [7]. The voltage- lift or/and voltage-multiplier technique uses a switch capacitor circuit. The parallel charging and series discharging of the capacitors can result in a high voltage gain that is dependent on the number of switches and capacitors [3], [8]. By cascading two step-up converters, a high voltage gain is achievable [9]. The main drawback of this technique is the high voltage and current stress on the switch. Although the voltage stress can be reduced by employing coupled inductors, the conduction losses still increase due to the high current stress of the switch [2]. The other technique employs transformers in the boost converter. Some topologies that utilizes this technique are presented in [10], [11]. In these topologies, the high voltage gain can be adjusted by two degrees of freedom, which are the duty cycle and the turn ratio. The main drawbacks of this technique are a high voltage spike on the switch and losses due to the leakage inductance. In order to solve the high voltage spike problem, employing a snubber circuit and a clamp circuit is unavoidable, which increases the system cost. However, this still leaves the problem of the leakage inductance losses [5]. When galvanic isolation is not required, the use of non-isolated coupled inductors is preferred due to their simpler winding structure, lower conduction losses, and continuous conduction current at the primary winding, which results in a smaller primary winding current ripple and lower input filtering capacitance [7]. This technique can also provide a high voltage gain with two degrees of freedom: the duty cycle and the turn ratio. However, it still suffers from the main drawbacks of transformer-based circuits. The first problem can be solved by employing an active/passive clamp circuit [7], [12], [13] and the leakage inductance losses problem can be alleviated by using a near unity turn ratio. Furthermore, a lower turn ratio results in a lower cost and a smaller core volume.

Recently, some topologies have been presented that combine the coupled inductor technique with other techniques such as cascading, voltage-lift or/and voltage-multiplier, z-source and multilevel techniques. These combinations result in achieving a high voltage gain with a lower turn ratio, which reduces the leakage inductance losses [14]-[17]. In [18]-[21], a synchronous boost converter, flyback converter and voltage multiplier were combined to provide a high step up non-isolated converter. In [22], the coupled inductor technique was combined with the z-source technique. Although a large conversion ratio was achieved, two large inductor cores were required for a 100W prototype circuit, which impress the efficiency in addition to increasing the circuit volume. The other drawbacks of this converter were the high voltage stress of the diodes and the floating output. This topology was improved in [23] by employing a single larger inductor core. Although, the efficiency is improved it is not acceptable, particularly for larger power applications. In [8], the super-lift (SL) technique was introduced. In this technique, a switch capacitor circuit was employed to increase the output voltage of a conventional boost converter stage by stage. The use of more diodes and capacitors resulted in a larger voltage gain. This technique is not appropriate for high step up applications due to the large number of components required to achieve a tenfold voltage gain. However, it can be a good approach in combination with other techniques. In [18], this technique was combined with the coupled inductor technique to achieve a high voltage gain with a proper number of components. The main drawback of the switch capacitor circuits, such as those used in the super-lift technique, is the inrush current event produced in the capacitor charging/discharging loops. The other disadvantage of this converter is the fact that it requires a relatively high turn ratio to achieve a tenfold voltage gain, which increases the core size and leakage inductance while decreasing the efficiency.

In order to solve inrush current problem of the switch capacitor loops and to achieve a tenfold or more voltage gain with a lower turn ratio, a new high step up converter employing coupled inductors and the super-lift technique is proposed.

The main contributions of this paper are as follows.

1) Achieving a high voltage gain with a low turn ratio and a proper duty cycle, which results in low switch voltage stress and better switch parameters.

2) Low voltage stress of the diodes resulting in diodes with low conduction losses and a much lower reverse recovery time.

3) Alleviation of the reverse recovery problem for all of the diodes.

4) A low inrush current through the switch at the turn on instant while charging voltage lifting capacitors.

This paper is organized as follows. In section II, the operating principle of the proposed convertor is expressed. Section III provides an analysis of the steady-state operation and design guidelines. In section IV, the performance of the proposed converter is compared with previous non-isolated converters. Experimental results obtained with a 200W, 30V input 380V output prototype circuit are discussed in section IV. Finally, some conclusions are presented in section V.



Ⅱ. OPERATING PRINCIPLE OF THE PROPOSED CONVERTOR

A schematic of the proposed converter is shown in Fig. 1. This converter consists of one power switch, one coupled inductor, five capacitors and five diodes. The magnetizing inductance Lm, the leakage inductance Lk and an ideal transformer model the coupled inductor. In this converter, the second winding of the coupled inductor is placed in the capacitor charging/discharging loops of the super lift circuit. This modified super-lift module contains the second winding of the coupled inductor. Hence, it creates no inrush current and transfers a high voltage to the output with a proper number of components and a low turn ratio of the coupled inductor.


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원본 그림의 이름: image1.png
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Fig. 1. Schematic of the proposed convertor.


Since the second winding of the coupled inductor is connected to the drain of the switch, a clamp circuit is required to clamp the off-state voltage of the switch and to reduce the voltage stress of the switch. The clamp circuit is also effective in terms of the voltage gain improvement. A passive clamp circuit is used, which consists of one capacitor Cc and one diode Dc. In order to discharge the clamp capacitor, the charging of the capacitor C1 in the super-lift stage is down via clamp capacitor discharging while the switch is on. When the switch is in the on-state, D1 and D3 are conducting and C1 and C3 are charged via Cc and C2, respectively. The Ns leakage inductance make a resonance with the capacitors in the charging/discharging loops. Thus, no inrush current is created.

The magnetizing inductance of the coupled inductors is much larger than the leakage inductance. To simplify the analysis, the secondary side leakage inductance is transferred to the primary side and modeled with Llk. When the switch is in the off-state D2, Do and Dc conduct. Therefore, the leakage energy and the energy stored in C1 and C3 are transferred to C2 and Co, respectively. In addition, the clamp capacitor is charged and clamps the stress voltage of the switch to a proper voltage.

To simplify the analysis, the following assumptions are made.

1) The switch is ideal but its parasitic capacitor is considered.

2) The ESR of the capacitors and inductors and the conduction voltage of the diodes and switch are neglected.

3) The magnetizing inductor Lm is large enough to have a constant current during a switching period.

4) The capacitors are large enough to have a constant voltage during a switching period.

5) K and n are the coupling coefficient of the coupled inductor and the turn ratio of the second winding to the primary winding, where: K≈Lm/(Lm+Llk) and n=Ns/Np.

Based on these assumptions, the operation of the proposed convertor in one switching period is divided into five operating modes. These operating modes are determined from the key waveforms of the proposed converter shown in Fig. 2. The equivalent circuit of the proposed convertor in each operating mode is shown in Fig. 3, and the operation in each mode is described as follows.


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Fig. 2. Typical key waveforms of the proposed convertor.


Fig. 3. Equivalent circuits for each of the operating modes. (a) Mode I. (b) Mode II. (c) Mode III. (d) Mode IV. (e) Mode V.

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(a)

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(b)

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원본 그림의 크기: 가로 925pixel, 세로 315pixel

(c)

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원본 그림의 이름: image10.png
원본 그림의 크기: 가로 925pixel, 세로 315pixel

(d)

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원본 그림의 이름: image11.png
원본 그림의 크기: 가로 925pixel, 세로 315pixel

(e)


1) Mode I [t0, t1]

During this mode, the switch is on. The diodes D1 and D3 are conducting and the other diodes are off. In this mode, the energy is stored in the magnetizing inductor Lm. Simultaneously, the leakage inductance of the second winding Llk2 resonates with the series capacitors C1, Cc and C3, C2. Since the resonance frequency is adjusted to be less than the switching frequency, the charging/discharging currents of C1/Cc and C3/C2 are considered to be linear. The voltage across C1 and C3 can be derived as:

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원본 그림의 이름: image3.png
원본 그림의 크기: 가로 1341pixel, 세로 335pixel                 (1)

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원본 그림의 이름: image4.png
원본 그림의 크기: 가로 1390pixel, 세로 335pixel                (2)

During this mode, the voltage across Lm is (VC1-VCc)/n. Therefore, the magnetizing and leakage inductance currents increase linearly as follows:

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원본 그림의 이름: image5.png
원본 그림의 크기: 가로 2039pixel, 세로 601pixel          (3)

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원본 그림의 이름: image6.png
원본 그림의 크기: 가로 2508pixel, 세로 601pixel    (4)

In this mode, the output capacitor Co is discharged to the load RL. At t1, the switch is turned off and this mode ends.


2) Mode II [t1, t2]

In this mode, Dc is conducting and the leakage inductance current is reduced to the magnetizing inductance current. Since the reverse voltage across Llk is very large, this mode duration is very short.


3) Mode III [t2, t3]

During this mode, the switch is off. The leakage inductance current becomes less than the magnetizing inductance current and the windings currents increase in the reverse direction.

Thus, the leakage inductance current decreases. The diodes D1 and D3 turn off at zero current and the diodes D2, Do and Dc are turned on. In this mode, the clamp capacitor Cc is charged via the leakage inductor of the coupled inductor. Therefore, the current of the clamp diode decreases. In this mode, the currents of the diodes D2 and Do increase since these diodes are in series with the second winding of the coupled inductor. The capacitor C2 is charged via the coupled inductor and C1. In addition, the input energy is transferred to the output via the coupled inductor and C3. At t3, the current of the clamp diode reaches zero. Therefore, Dc is turned off at zero current and this mode ends.


4) Mode IV [t3, t4]

During this mode, the switch is off, diode Dc is turned off and the other diodes remain unchanged. In this mode, the leakage inductance current decreases and the currents of the diodes D2 and Do increase as before. The capacitor C2 continues being charged via the coupled inductor and the capacitor C1. In addition, the input energy continues transferring to the output via the coupled inductor and C3. The voltage across C2 and Co can be derived as:

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원본 그림의 이름: image12.png
원본 그림의 크기: 가로 1875pixel, 세로 335pixel                        (5)

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원본 그림의 이름: image13.png
원본 그림의 크기: 가로 1858pixel, 세로 335pixel                        (6)

During this mode, the voltage across Lm is (VC2- VC1-VCc)/n. Therefore, the magnetizing and leakage inductance currents can be expressed by:

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원본 그림의 이름: image14.png
원본 그림의 크기: 가로 2491pixel, 세로 601pixel                 (7)

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원본 그림의 이름: image15.png
원본 그림의 크기: 가로 2779pixel, 세로 494pixel     (8)

At t4, the switch is turned on and this mode ends.


5) Mode V [t4, t5]

During this mode, the switch is turned on and the diodes remain unchanged. The leakage inductance current increases and the currents of the diodes D2 and Do decrease. The capacitor C2 continues being charged via the coupled inductor and C1, and the input energy continues transferring to the output via the coupled inductor and C3. At t5, the currents of Do and D2 reach zero and this mode ends. Thus, at the end of this mode, the leakage inductance current is equal to the magnetizing inductance current.



Ⅲ. STEADY-STATE ANALYSIS


A. Voltage Gain Analysis

The CCM operation of the proposed converter is studied here. Modes II, III and V are very short intervals in comparison with modes I and IV. Thus, to simplify the analysis only the two larger intervals, i.e. mode I and IV, are considered. In mode I, when the switch is conducting voltage across the magnetizing and leakage inductors, they are written as:

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원본 그림의 이름: image16.png
원본 그림의 크기: 가로 1160pixel, 세로 551pixel                    (9)

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원본 그림의 이름: image17.png
원본 그림의 크기: 가로 1531pixel, 세로 551pixel                (10)

During mode IV, when the switch is in the off-state, the voltage across the magnetizing and leakage inductors are defined by:

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원본 그림의 이름: image18.png
원본 그림의 크기: 가로 1629pixel, 세로 551pixel                (11)

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원본 그림의 이름: image19.png
원본 그림의 크기: 가로 2442pixel, 세로 551pixel      (12)

From equations (1)-(9) and (11), the output voltage is obtained as:

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원본 그림의 이름: image20.png
원본 그림의 크기: 가로 1341pixel, 세로 318pixel                   (13)

From the volt-second balance principle for the magnetizing inductor Lm and the leakage inductor Llk, the following equations can be derived as:

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원본 그림의 이름: image21.png
원본 그림의 크기: 가로 1423pixel, 세로 651pixel                 (14)

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원본 그림의 이름: image22.png
원본 그림의 크기: 가로 1407pixel, 세로 651pixel                 (15)

From equations (9)-(15) and some simplifications, the voltage across the clamp capacitor is obtained as:

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원본 그림의 이름: image23.png
원본 그림의 크기: 가로 1078pixel, 세로 584pixel                    (16)

On the other hand, from the ampere-second balance of the capacitors C1 and C3 in one switching period, the average current of D1 and D3 can be expressed by:

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원본 그림의 이름: image24.png
원본 그림의 크기: 가로 2072pixel, 세로 518pixel         (17)

According to the key waveforms shown in Fig. 2 and equation (17), the output current Io is obtained as:

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원본 그림의 이름: image25.png
원본 그림의 크기: 가로 1661pixel, 세로 601pixel             (18)

where the peak current of the second winding of the coupled inductor In2 (peak) can be written as:

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원본 그림의 이름: image26.png
원본 그림의 크기: 가로 2952pixel, 세로 533pixel   (19)

From equations (16), (18) and (19), the voltage across the capacitor C1 is achieved as:

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원본 그림의 이름: image27.png
원본 그림의 크기: 가로 2590pixel, 세로 584pixel               (20)

From equations (14), (16) and (19), the voltage across the capacitor C2 can be derived as:

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원본 그림의 이름: image28.png
원본 그림의 크기: 가로 2491pixel, 세로 618pixel                (21)

Thus, by substituting equation (21) into (13) the output voltage can be computed as:

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원본 그림의 이름: image29.png
원본 그림의 크기: 가로 2508pixel, 세로 618pixel               (22)

Thus, the voltage gain can be obtained as:

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원본 그림의 이름: image30.png
원본 그림의 크기: 가로 2023pixel, 세로 584pixel                     (23)

where the coefficient α is related to the leakage inductance of the coupled inductor and is obtained from the following equation:

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원본 그림의 이름: image31.png
원본 그림의 크기: 가로 1439pixel, 세로 618pixel                          (24)

By neglecting the leakage inductance, the ideal voltage gain is expressed by:

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원본 그림의 이름: image32.png
원본 그림의 크기: 가로 1472pixel, 세로 584pixel                          (25)


B. Voltage and Current Stress Analysis

By ignoring the leakage inductance, the voltage stresses of the switch and diodes can be written as:

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원본 그림의 이름: image33.png
원본 그림의 크기: 가로 2524pixel, 세로 567pixel               &sp;(26)

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원본 그림의 이름: image34.png
원본 그림의 크기: 가로 2943pixel, 세로 455pixel    (27)

From the ampere-second balance of the capacitors C1 and C3 in one switching period, the average current of D2 and Do can be expressed by:

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원본 그림의 이름: image35.png
원본 그림의 크기: 가로 2179pixel, 세로 518pixel                     (28)

According to the key waveforms of Fig. 2 and equation (28), the output current Io is obtained as:

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원본 그림의 이름: image36.png
원본 그림의 크기: 가로 1826pixel, 세로 601pixel                         (29)

According to (17), (18), (28) and (29), the peak currents of the power devices can be derived as:

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원본 그림의 이름: image37.png
원본 그림의 크기: 가로 1858pixel, 세로 518pixel                         (30)

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원본 그림의 이름: image38.png
원본 그림의 크기: 가로 2146pixel, 세로 584pixel                      (31)

그림입니다.
원본 그림의 이름: CLP00001798440f.bmp
원본 그림의 크기: 가로 1029pixel, 세로 263pixel         (32)

By ignoring the ripple of ilm, the average of the magnetizing inductor Ilm can be expressed by:

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원본 그림의 이름: image41.png
원본 그림의 크기: 가로 3156pixel, 세로 618pixel          (33)

By substituting (33) into (32) and some simplification, the peak current of the switch is obtained as:

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원본 그림의 이름: image42.png
원본 그림의 크기: 가로 2245pixel, 세로 618pixel                     (34)


C. Design Procedure of the Converter Elements

To assure the CCM operation of the proposed converter, the average current of the magnetizing inductor should be more than half of its ripple. This means that:

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원본 그림의 이름: image43.png
원본 그림의 크기: 가로 1209pixel, 세로 518pixel                                 (35)

The ripple of the magnetizing inductance current (Δilm) can be expressed as:

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원본 그림의 이름: image44.png
원본 그림의 크기: 가로 980pixel, 세로 567pixel                                     (36)

Thus, the minimum value of the magnetizing inductor can be computed from equations (25), (33), (35) and (36) as follows:

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원본 그림의 이름: image45.png
원본 그림의 크기: 가로 1875pixel, 세로 701pixel                    (37)

where RL (BCM) is the load resistance in the boundary condition mode (BCM) operation.

Equation (38) expresses the voltage ripple equation of the capacitor, which is used to design the capacitor volume.

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원본 그림의 이름: CLP000017980001.bmp
원본 그림의 크기: 가로 552pixel, 세로 78pixel                (38)

From (38) the capacitors volumes are computed as:

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원본 그림의 이름: CLP000017980002.bmp
원본 그림의 크기: 가로 352pixel, 세로 162pixel                        (39)

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원본 그림의 이름: CLP000017980003.bmp
원본 그림의 크기: 가로 788pixel, 세로 167pixel        (40)

In the proposed converter, each of the capacitors in series with another one resonates with the leakage inductance. In order to reduce the inrush current, this resonant period must be larger than the switching period as per the following equation:

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원본 그림의 이름: image49.png
원본 그림의 크기: 가로 1531pixel, 세로 668pixel                 (41)

where Ci={C1, C3} and Cj={ Cc, C2, Co}.

Therefore, the proper value of the capacitors should provide the terms of equations (40) and (41)

A clamp capacitor is designed to limit the voltage spike of the switch. To achieve this, the resonant period between the clamp capacitor and the leakage inductance should be much greater than the minimum off-time of the switch as per the following equation:

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원본 그림의 이름: image50.png
원본 그림의 크기: 가로 2056pixel, 세로 351pixel           (42)

Hence:

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원본 그림의 이름: image51.png
원본 그림의 크기: 가로 1127pixel, 세로 651pixel                      (43)

The clamp capacitor value should be designed according to both of the conditions assigned in equations (40) and (43).



Ⅳ. PERFORMANCE COMPARISON

The performance of the proposed converter is compared with that of other recent non-isolated single switch topologies [2], [18], [20], [21], [24]-[26] in terms of voltage gain, voltage stress on power devices, component count and efficiency. This comparison is summarized in Table I. The mentioned efficiency is obtained from PSpice simulation results at the same conversion ratio, the same output power and with the same components. The switch voltage stress for all of these converters are more than 100V. Thus, an IRFP250N is employed. However, since the voltage stress of the proposed converter is lower than 100V, an IRFP150N is used. For diodes with low voltage and current stresses, the BYV28-200 is employed; and for diodes with large current and voltage stresses MURXXX series diodes are used. These components are chosen according to PSpice library availability. The efficiency comparison indicates that the proposed converter has a better efficiency, which is due to the low voltage stress of the switches and diode.


TABLE I COMPARISON OF THE PROPOSED CONVERTER WITH PERVIOUS NON-ISOLATED CONVERTERS

Non-isolated topologies

[2]

[18]

[20]

[21]

[24

[25]

[26

Proposed convertor

Voltage gain

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원본 그림의 크기: 가로 1661pixel, 세로 651pixel

그림입니다.
원본 그림의 이름: image53.png
원본 그림의 크기: 가로 946pixel, 세로 518pixel

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Voltage stress on switch

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Maximum Voltage stress on diodes

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Switches

1

1

1

1

1

1

1

1

Diodes

6

4

5

4

3

6

4

5

Capacitors

5

4

5

4

4

6

5

5

Core

2

1

1

1

2

1

2

1

Efficiency (%) POUT =200W

90.67

93.6

91.84

92.23

94.7

91.98

94.66

95.2


In Fig. 4, the voltage gain and voltage stress variations of the proposed converter versus the duty cycle at a specified turn ratio (n=1) are compared with [2], [18], [20], [21], [24]-[26] under CCM operation. As can be observed, the proposed converter achieves lower voltage stress in comparison with these topologies. Although, for D>0.5, [2] has a larger voltage gain than the proposed converter, its switch voltage stress is higher according to Fig. 4 (b), which decreases its efficiency due to higher conduction losses of the high voltage switches. In addition, the voltage gain and voltage stress of the switch versus the turn ratio at a specified duty cycle (D=0.6) is compared with its counterparts [2], [18], [20], [21], [24]-[26] in Fig. 5. The proposed converter has better performance for n<2.5 in comparison with [20] and for n<1.67 in comparison with [25]. While for a larger turn ratio, the voltage gains of [20] and [25] are better than those of the proposed converter, a larger turn ratio results in more leakage inductance and parasitic resistance, which results in a lower efficiency. In addition, for all values of the turn ratio, the proposed converter has better performance than [18], [21], [24], and [26]. Although, for all turn ratios, [2] has a larger voltage gain than the proposed converter, its voltage stress is very high according to Fig. 5(b), which decrease its efficiency. However, the proposed converter can achieve a high voltage gain without a large duty cycle and a turn ratio that results in a reduction of the magnetic component size, current stress of the switch, input current ripple and conduction losses.


Fig. 4. Comparison of the voltage gain and voltage stress on a switch versus duty cycle variations for n=1. (a) Voltage gain. (b) Voltage stress of a switch normalized by the output voltage (Vs/Vo).

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(a)

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(b)


Fig. 5. Comparison of the voltage gain and voltage stress on a switch versus turn ratio variations for D=0.6. (a) Voltage gain. (b) Voltage stress of a switch normalized by output voltage (Vs/Vo).

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(b)



Ⅴ. EXPERIMENTAL RESULTS

In order to verify the theoretical analysis of the proposed convertor, a 30V to 380V, 200 W laboratory prototype circuit has been implemented and tested. A photograph of the experimental circuit is shown in Fig. 6. This circuit is designed for a proper value of the duty cycle and a low turn ratio. Thus, the duty cycle and turn ratio are adjusted to about D=0.6 and n=1, respectively. The minimum magnetizing inductor can be calculated from (37). According to this, the proper value of the magnetizing inductor is chosen to be 100µH. In order to find proper values for the capacitors, the voltage ripple of the output capacitor and the others are considered to be 0.1% and 1-2% of their average voltages, respectively. According to (39) and (40), the minimum value of the output capacitor and the others are computed to be 8.5µF and 1.4µF, respectively.


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Fig. 6. Photograph of the laboratory prototype converter.


In order to have a low ESR effect, equal diode current stresses and to satisfy equations (41)-(43) the values for all of the capacitors are chosen to be 22µF. The characteristics of the laboratory prototype circuit are given in Table II. Experimental results of the implemented circuit under a full load, input voltage VIN=30V, output power PO=200W and load resistance RL=720Ω, are shown in Fig. 7. The voltage and currents waveforms for all of the diodes and switches are illustrated in Fig. 7(a)-(f). As can be seen, the voltage stress of the diodes D1-3 and Do are equal and matched with equation (27). The leakage inductance of the coupled inductor alleviates the reverse recovery problem of the diodes. The clamp circuit limits the voltage stress of the power switch to about 80V, which is equal to the expected value from equation (26). Thus, a low on-resistance low voltage MOSFET is chosen.


TABLE II CHARACTERISTICS OF THE LABORATORY PROTOTYPE CIRCUIT

Symbol

Parameter

Value

Vin

Input DC voltage

30V

Vout

Output DC voltage

380V

Po

Maximum output power

200W

fsw

Switching frequency

100kHz

Co

Output capacitor

22µF/450V

Cc,C1

Clamp capacitor

22µF/160V

C2-C3

Capacitors

22µF/400V

DC, D1-D3, Do

Diodes

BYV28-200

SW

Power switch

IRFP150

---

Magnetizing core

EI33/29

Ns/Np

Turn ratio

1

Lm

Magnetizing inductance

108µH

K

Coupling coefficient

0.97


Fig. 7. Experimental voltage and current waveforms. (a) Diode D1. (b) Diode D2. (c) Diode D3. (d) Output diode DO. (e) Clamp diode DC. (f) Switch.

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(c)

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(d)

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(e)

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(f)


A power loss breakdown analysis at the rated current considering the nominal specifications and selected components is given in Table III and Fig. 8. In this estimation, both the conduction losses and switching losses are calculated for the active switch while only the conduction losses and copper losses were considered for the diodes and the coupled inductor respectively. According to the estimated values, the switch losses have the most significant impact on the converter efficiency. The measured converter efficiency at the rated power is about 92.77%, while its theoretical value from Table III is 93.16%.


TABLE III ESTIMATED EFFICIENCY AND LOSS DISTRIBUTIONS

Type

rparasitic (mΩ)

Irms/Iave/Imax* (A)

VF/Vmax+ (V)

PLoss

(W)

Ploss ratio (%)

S (conduction loss)

30

8.35

-

2.1

14.31

S (switching loss)

-

11

80

4.4

30

Coupled inductor

80

7.5

-

4.5

30.67

C1-3

200

1.12

-

3*0.25

5.11

Cc

200

0.72

-

0.1

0.68

Co

200

1.62

-

0.52

3.55

Dc, D1-3 and Do

-

0.52

0.89

5*0.46

15.68

total

-

-

-

14.67

100

*Irms for conduction losses, capacitors and coupled inductor losses, Iave for diodes and Imax for switching losses

+VF for diodes and Vmax for switching losses


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Fig. 8. Pie graph of a loss breakdown at the rated power.


Fig. 9 demonstrates the efficiency of the proposed convertor, which is calculated by measuring the input and output average powers at different loads. As can be observed, the maximum efficiency yields around 95.7% at Po=25W. Further, under the full load condition i.e. Po= 200W, VIN=30V and RL=720Ω, the efficiency is about 92.77%. A detailed PSPICE simulation considering the parasitic resistances for all of the elements and ignoring the core loss and PCB track losses is used to compare the efficiency of the proposed converter with that of the converter proposed in [25]. The results of this comparison are shown in Fig. 9. As can be seen, the detailed simulated efficiency of the proposed converter under different loads is near to those achieved by measurements.


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Fig. 9. Efficiency curve of the proposed converter under different loads.



Ⅵ. CONCLUSION

In this paper, a new dc/dc high step up converter was introduced. A high voltage gain has been achieved by combining the coupled inductor technique with the super-lift technique. This converter employs a passive clamp circuit to recycle the energy stored in the leakage inductance. In this topology, a high voltage gain with a proper duty cycle and a low turn ratio is achievable. In addition, the voltage stress on the semiconductor devices has been reduced. A small volume, reduced reverse recovery and conduction losses, high efficiency and low cost are other advantages of the proposed convertor. A laboratory prototype circuit verified the theoretical analysis.



REFERENCES

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[2] P. Saadat and K. Abbaszadeh, “A single-switch high step- up DC-DC converter based on quadratic boost,” IEEE Trans. Ind. Electron., Vol. 63, No. 12, pp. 7733-7742, Dec. 2016.

[3] O. Abutbul, A. Gherlitz, Y. Berkovich, and A. Ioinovici, “Step-up switching-mode converter with high voltage gain using a switched-capacitor circuit,” IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., Vol. 50, No. 8, pp. 1098- 1102, Aug. 2003.

[4] Z. Qun and F.C. Lee, “High-efficiency, high step-up DC-DC converters,” IEEE Trans. Power Electron., Vol. 18, No. 1, pp. 65-73, Jan. 2003.

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[6] H. Liu, H. Hu, H. Wu, Y. Xing, and I. Batarseh, “Overview of high-step-up coupled-inductor boost converters,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 4, No. 2, pp. 689- 704, Jun. 2016.

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[10] H. Seok, B. Han, B. H. Kwon, and M. Kim, “High step-up resonant DC/DC converter with ripple-free input current for renewable energy systems,” IEEE Trans. Ind. Electron., Vol. 65, No. 11, pp. 8543-8552, Nov. 2018.

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[13] M. A. Salvador, T. B. Lazzarin, and R. F. Coelho, “High step-up DC–DC converter with active switched-inductor and passive switched-capacitor networks,” IEEE Trans. Ind. Electron., Vol. 65, No. 7, pp. 5644-5654, Jul. 2018.

[14] K.C. Tseng, C.A. Cheng, and C. T. Chen, “High step-up interleaved boost converter for distributed generation using renewable and alternative power sources,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 5, No. 2, pp. 713-722, Jun. 2017.

[15] S. Changchien, T. Liang, J. Chen, and L. Yang, “Novel high step-up DC-DC converter for fuel cell energy conversion system,” IEEE Trans. Ind. Electron., Vol. 57, No. 6, pp. 2007-2017, Jun. 2010.

[16] W. Li and X. He, “Review of nonisolated high-step-up DC/ DC converters in photovoltaic grid-connected applications,” IEEE Trans. Ind. Electron., Vol. 58, No. 4, pp. 1239-1250, Apr. 2011.

[17] K. Tseng, J. Chen, J. Lin, C. Huang, and T. Yen, “High step-up interleaved forward-flyback boost converter with three-winding coupled inductors,” IEEE Trans. Power Electron., Vol. 30, No. 9, pp. 4696-4703, Sep. 2015.

[18] H. Bahrami, H. Iman-Eini, B. Kazemi, and A. Taheri, “Modified step-up boost converter with coupled-inductor and super-lift techniques,” IET Power Electron., Vol. 8, No. 6, pp. 898-905, Jun. 2015.

[19] S. Sathyan, H. M. Suryawanshi, M. S. Ballal, and A. B. Shitole, “Soft-switching DC-DC converter for distributed energy sources with high step-up voltage capability,” IEEE Trans. Ind. Electron., Vol. 62, No. 11, pp. 7039-7050, Nov. 2015.

[20] Y. Chen, Z. Lu, R. Liang, and C. Hung, “Analysis and implementation of a novel high step-up DC-DC converter with low switch voltage stress and reduced diode voltage stress,” IET Power Electron., Vol. 9, No. 9, pp. 2003-2012, Jul. 2016.

[21] A. Ajami, H. Ardi, and A. Farakhor, “A novel high step-up DC/DC converter based on integrating coupled inductor and switched-capacitor techniques for renewable energy applications,” IEEE Trans. Power Electron., Vol. 30, No. 8, pp. 4255-4263, Aug. 2015.

[22] B. Poorali, A. Torkan, and E. Adib, “High step-up Z-source DC–DC converter with coupled inductors and switched capacitor cell,” IET Power Electron., Vol. 8, No. 8, pp. 1394-1402, Aug. 2015.

[23] B. Poorali, H. M. Jazi, and E. Adib, “Improved high step-up Z-source DC–DC converter with single core and ZVT operation,” IEEE Trans. Power Electron., Vol. 33, No. 11, pp. 9647-9655, Nov. 2018.

[24] H. Ardi, A. Ajami, and M. Sabahi, “A novel high step-up DC/DC converter with continuous input current integrating coupled inductor for renewable energy applications,” IEEE Trans. Ind. Electron., Vol. 65, No. 2, pp. 1306-1315, Feb. 2018.

[25] B. Honarjoo, S. M. Madani, M. Niroomand, and E. Adib, “Analysis and implementation of a new single switch, high voltage gain DC-DC converter with a wide CCM operation range and reduced components voltage stress,” J. Power Electron., Vol.18, No.1, pp.11-22, Jan. 2018.

[26] R. Moradpour, H. Ardi, and A. Tavakoli, “Design and implementation of a new SEPIC-based high step-up DC/ DC converter for renewable energy applications,” IEEE Trans. Ind. Electron., Vol. 65, No. 2, pp. 1290-1297, Feb. 2018.



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Rezvan Fani was born in Ahvaz, Iran. She received her B.Sc. degree in Electronic Engineering from Razi University, Kermanshah, Iran, in 2009; and her M.Sc. degree in Electronic Engineering from Shahid Chamran University of Ahvaz, Ahvaz, Iran, in 2013, where she is presently working towards her Ph.D. degree in Electronic Engineering. Her current research interests include dc-dc converters and soft switching techniques.


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Ebrahim Farshidi was born in Shoushtar, Iran, in 1973. He received the B.Sc. degree from Amirkabir University of Technology, Tehran, Iran, in 1995; the M.Sc. degree from Sharif University of Technology, Tehran, Iran, in 1997; and the Ph.D. degree from Isfahan University of Technology (IUT), Isfahan, Iran, in 2008, all in electronic engineering. From 1997 to 2002, he worked for Karun Pulp and Paper Company. Since 2002, he has been with Shahid Chamran University of Ahvaz, Ahvaz, Iran, where he is currently a Professor of Electrical Engineering. He is author of more than 100 technical papers and three books in electronics. His areas of interests include circuit design for analog integrated circuits and circuit theories.


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Ehsan Adib was born in Isfahan, Iran, in 1982. He received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 2003, 2006 and 2009, respectively. He is currently a faculty member at the Department of Electrical and Computer Engineering, Isfahan University of Technology. He is the author of more than 100 papers in journals and conference proceedings. His research interests include dc–dc converters and their applications and soft-switching techniques. Dr. Adib was a recipient of the Best Ph.D. Dissertation Award from IEEE Iran Section in 2010.


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Abdolnabi Kosarian was born in Behbahan, Khouzestan, Iran. He received his Ph.D. degree in Electronic Engineering from the University of Surrey, Surrey, ENG, UK, in 1998. He is presently an Associate Professor of Electronic Engineering at Shahid Chamran University of Ahvaz, Ahvaz, Iran. His research interests include solid state electronics, semiconductor devices and solar cells.