https://doi.org/10.6113/JPE.2019.19.3.815

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Design and Implementation of Instantaneous Power Estimation Algorithm for Unified Power Conditioner

Sindhu S.^†, Sindhu M. R.^*, and T. N. P. Nambiar^*

^†,*Department of Electrical and Electronics Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India

Abstract

This paper discusses a simple control approach for a Unified Power Conditioner (UPC) system to achieve power quality compensation at the point of common coupling in distribution systems. The proposed Instantaneous Power Estimation Algorithm (IPEA) for shunt and series active power filters uses a simple mathematical concept that reduces the complexity in the design of the controller. The performance of a UPC is verified with a system subjected to voltage distortions, sags/swells and unbalanced loads using MATLAB/SIMULINK. The simulation study shows that a UPC with the proposed control algorithm can effectively compensate for voltage and current harmonics, unbalance and reactive power. The control algorithm is experimentally implemented using dSPACE DS1104 and its effectiveness has been verified.

Key words: Harmonics, Point of common coupling, Power conditioner, Power quality, Series active power filter, Shunt active power filter

Manuscript received Jul. 13, 2018; accepted Feb. 23, 2019

Recommended for publication by Associate Editor Seon-Ju Ahn.

^†Corresponding Author: sindhus2478@gmail.com Tel: 91-4662246100, Amrita Vishwa Vidyapeetham

^*Department of Electrical and Electronics Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India

Ⅰ. INTRODUCTION

Recently, there has been a surge in the current and voltage based power quality problems due to the wide use of power electronic controllers and sensitive equipment in the commercial and industrial areas. The alarming rate of growth in controller using power electronic devices in such industries has resulted in power quality disturbances in distribution networks. High precision process industries and critical loads such as computers, microprocessors and medical equipment require an uninterrupted and regulated power supply of a rated magnitude and frequency. Power quality problems have an adverse effect on industries in terms of equipment failure, data loss, commercial loss and so on [1]. Therefore, standards such as IEEE 519-1992, 2014 have been developed to keep power quality within acceptable limits [2]. A number of mitigation techniques have evolved over time to meet these standards.

These mitigation techniques include passive filters, active filters, hybrid filters and custom power devices [3], [4]. Traditional passive filters using passive components provide only fixed compensation [5]. Active power filters [6]-[8] provide compensation for harmonics and introduce reactive components into systems so that power at a unity power factor can be drawn from the grid. Hybrid power filters [9] are a combination of more than one active filter or passive filter to solve the problems of reactive power and harmonics. Active power filters and hybrid power filters are capable of suppressing either voltage or current related power quality issues. The custom power park [10] concept was developed to provide high quality power to customers with critical loads that cannot tolerate variations in power quality levels. Custom power park with compensating custom power devices such as DVRs, static shunt compensators and unified power quality conditioners overcome power quality disturbances such as voltage sag, voltage swell, transients, voltage and current harmonics. It can also provide a solution to the reactive power burden. DVR injects voltage through a series transformer to regulate the voltage at the load to a reference value, while static shunt compensators mitigate current quality problems [11], [12]. As an optimal solution, a Unified Power Conditioner (UPC) is used to simultaneously mitigate multiple power quality disturbances in voltage and current. These conditioners are classified as either a left or right shunt UPC, based on the positions of series and shunt active power filters. The series active power filter is connected after the shunt active power filter in the left shunt configuration. Meanwhile, the series compensator is connected before the shunt compensator in the right shunt configuration. Based on its control, a Unified Power Quality Conditioner (UPQC) can be classified as a UPQC-P, a UPQC-Q or a UPQC-S [13]. In UPQC-P, the series active power filter injects voltage in-phase with real power injection. In UPQC-Q, the in-phase injection does not involve any real power injection. In the UPQC-S, the series active power filter injects with a minimum kVA rating at an optimum phase angle. A right shunt UPC with real power injection during sag/swell conditions with a series active power filter is implemented in this paper.

Fig. 1. Configuration of a three-phase unified power conditioner.

The performance of the compensator depends upon the control algorithm and how fast and precisely the control algorithm responds. Different control algorithms are available for the control of the shunt and series active filters of a UPC such as power balance theory, instantaneous symmetrical component theory, synchronous reference frame theory, synchronous detection, and unit vector template generation, [14]-[17] etc. A performance analysis was conducted on conventional algorithms such as synchronous reference frame theory, synchronous detection, Icosϕ algorithm, and exponential composition algorithm [18]. Based on this study, the IPEA was proposed. It responds efficiently during dynamic conditions in addition to being simpler than many of the other algorithms. In the literature, the DC link voltage is maintained in accordance with reference values using a sliding mode controller, variable structure PI controller [19], etc.

This paper proposes an IPEA for a shunt active filter that uses only simple mathematic concepts and simplifies the control circuit design to generate a reference current for compensation. Section II of this paper explains the extraction of the active load current component using the IPEA. In this method, the shunt active filter can keep the DC link voltage constant and compensate for any unbalance in the load current. In addition, it can compensate for harmonic currents and reactive power. Here the DC link voltage is kept constant using a PI controller. The control of a series inverter provides a fast response to voltage disturbances and makes the voltage at the Point of Common Coupling (PCC) sinusoidal. Section III discusses a comparison of the IPEA with other control algorithms. It also provides a validation of the IPEA control for a UPC under different operating conditions. Laboratory implementation using dSPACE DS1104 is discussed in section IV. Finally, section V provides some conclusions.

Fig. 2. Schematic of an IPEA for a shunt active power filter.

Ⅱ. UPC STRUCTURE

The UPC arrangement is presented in Fig. 1. It is a combination of series and shunt active power filters with a common DC link capacitor to compensate for multiple power quality concerns. The shunt active power filter provides compensation for the harmonic and reactive components of the load current. The series active power filter mitigates voltage harmonics and unbalance as well as sag/swell conditions in voltage at the PCC. The control of these active power filters is discussed in the following sub sections.

A. Reference Current Generation Strategy

According to the proposed control algorithm, reactive and harmonic components are supplied by the shunt active power filter. The three-phase distorted load currents are sensed. The distorted non-linear load currents consist of fundamental and harmonics components. The IPEA control is based on the extraction of the fundamental component of the current from the distorted load current. The proposed control strategy to extract I_Lcosf is shown in Fig. 2.

The fundamental component of three-phase load current consists of real and reactive parts. The real and reactive parts of the three-phase non-linear load current are separated by passing them through a biquad filter. In addition, with the biquad filter design, it is possible to obtain low pass and band pass outputs simultaneously with a unity gain. The fundamental current obtained from the low pass output of the biquad filter has an inherent phase delay of 90 degrees, and it is inverted to get the real component. The resulting real part of the three-phase load currents are expressed as:

         (1)

The band pass output of the biquad filter provides the reactive part of the fundamental current as:

       (2)

From the sensed voltage at the PCC, a unit template for each of the phases is obtained. The in-phase and quadrature components are obtained from the unit template of each phase.

Multiplying the in-phase components of the load current of each phase and the unit template yields:

    (3)

The output from the product of the quadrature component of each phase and the unit template is:

        (4)

The results obtained in (3) and (4) are added. By applying a trigonometric identity, the magnitude of active part of the three-phase load is obtained as:

         (5)

Under balanced load and source conditions, the magnitudes of the active current components are the same in the three phases. In addition, this algorithm provides reactive power compensation for low power factor balanced load conditions. The fundamental of the three-phase non-linear load current consists of real and reactive components. The biquad filter filters out the reactive component, which is injected by the shunt active power filter. During unbalanced conditions, the magnitude of the reference source current is:

        (6)

The three-phase reference source currents are obtained by multiplying the magnitude in (6) with unit template waveforms of the respective phases obtained from the voltage at the PCC and are given as:

Fig. 3. Block diagram for the control of a series active power filter.

        (7)

The three-phase compensation currents (i*_a, i*_b and i*_c) are obtained by subtracting the load current from the reference source current. These signals are compared with the actual source currents in the hysteresis band control to produce switching pulses for the shunt inverter.

B. Reference Voltage Generation Strategy

This section discusses the compensation of voltage related power quality problems such as distortions, sag and swell. Series active power filters inject appropriate voltage in series with the grid voltage using a series transformer to compensate for voltage power quality issues at the PCC. To compensate for sag, the series inverter injects an in-phase voltage in series with the supply, and an out-of-phase voltage of a required magnitude is injected to compensate for voltage swell. The control algorithm of a series inverter calculates the switching pulses for the series inverter.

The voltage is initially passed through a bandpass filter with cut off frequencies of 49.9Hz and 50.1Hz to remove any distortions. The band pass filter extracts the fundamental component and makes the voltage sinusoidal.

       (8)

The obtained reference voltage is calculated by multiplying the unit template from the fundamental voltages with the desired magnitude. The calculated reference voltages are compared with the actual load terminal voltages to produce switching pulses to the series inverter. The operation is indicated as a block diagram in Fig. 3.

Ⅲ. SIMULATION RESULTS

The performance of a UPC with the IPEA control is validated based on simulation results obtained using MATLAB/ Simulink. For an analysis of the behavior of the developed model, a three-phase thyristor converter load with firing angle control is considered as the harmonic load. For the simulation analysis, a 400V, 50Hz three-phase AC source supplying a thyristor converter feeding an RL load of 12kVA with a 0.7 lagging power factor is selected as the test system. The line impedance is taken as Rs=0.1W and Ls=0.2mH. The coupling inductor value L_sh for the shunt compensator of the UPC is 3.5mH. The PWM inverters of the series and shunt compensators operate at a switching frequency of 20kHz. The DC link capacitor rating is selected as 4.5mF, and the DC link voltage V_DC is 700V. The performance of the IPEA with a shunt active power filter is compared with conventional algorithms. The control algorithms considered for comparison are simulated using MATLAB/ Simulink and the comparison has been done based on the Total Harmonic Distortion (THD) and the time the algorithms take to respond under dynamic conditions. Figure 4 shows a comparison of the IPEA with control algorithms such as synchronous frame theory [20], synchronous detection [21], Icosϕ algorithm [22], [23] and exponential composition algorithm [24].

To compare the dynamic performance of the system with different algorithms, the thyristor converter is initially operated at a firing angle of 30 degrees until 0.2s. After 0.2s the converter is operated at a firing angle of 45 degrees. When simulating the algorithms under similar source and load conditions, all of the algorithms behave satisfactorily by improving the THD, reactive power and power factor correction. With all of the algorithms the THD% is within acceptable limits i.e., less than 5%. However, the response time varies in the algorithms. From Fig. 4(c) to Fig. 4(g), it can be observed that the IPEA performs with a better response time when compared to the other algorithms. The synchronous reference frame theory takes nearly 2.5 cycles to respond, while synchronous detection takes one cycle to respond in the dynamic conditions as can be seen in Fig. 4(c) and Fig. 4(d), respectively. With the Icosf algorithm as shown in Fig. 4(e), a delay of 1.5 cycles is observed as the response time during dynamic conditions. Although the performances of the ECA and IPEA are comparable, as can be seen in Fig. 4(f) and Fig. 4(g), the design complexity of implementing the ECA makes the IPEA performance better. The simulation results show an obvious improvement in the response time using the IPEA over the other control algorithms despite sudden changes in the load current.

Fig. 4. Comparison of the IPEA with different control algorithms under dynamic conditions for balanced source/balanced load conditions.

Table I SIMULATION ANALYSIS OF DIFFERENT OPERATING CONDITIONS FOR A THREE-PHASE THYRISTOR CONVERTER LOAD

SOURCE/LOAD	PHASE	WITHOUT UPC				WITH UPC
		VRMS at PCC(V)	THDV%	IRMS (A)	THDI%	VRMS at PCC(V)	THDV%	IRMS (A)	THDI%
Distorted Source Voltage and Balanced Non-linear Load	a, b, c	230.9	20.62	17.31	27.10	230.9	0.18	15.42	3.67
Voltage Sag and balanced Non-linear Load	a, b, c	173.2	0.5	17.94	28.24	230.9	0.28	15.5	3.66
Voltage Swell and balanced Non-linear Load	a, b, c	300.2	0.4	17.44	27.66	230.9	0.39	15.77	3.64
Distorted Source Voltage and unbalanced Non-linear Load	a	230.9	20.62	3.96	34.08	230.9	0.18	3.26	3.64
	b	230.9	20.62	3.36	35.74	230.9	0.16	3.23	3.63
	c	230.9	20.62	4.05	28.04	230.9	0.20	3.19	3.67

A. Performance Analysis of a UPC

The IPEA was proposed to compensate for current harmonics and reactive power. Voltage distortions such as sag, swell and harmonics are compensated by the series compensator of a UPC at the PCC. The system is simulated under different source/load conditions and dynamic load conditions. Then the harmonic analysis for different operating conditions is tabulated in Table I. The IPEA is implemented using MATLAB/ Simulink under different operating conditions as discussed in the following sub sections.

1) Distorted Grid Voltage and Balanced Non-linear Load: The system is simulated with distortions introduced in the supply voltage from 0.1s to 0.2s. The distorted voltage contains harmonics with fifth and seventh order as 20% and 5% of the fundamental as shown in Fig. 5(a). The three-phase voltages are distorted in equal amounts with a THD of 20.62%. Owing to the non-linearity of the selected load, distortions are introduced in the line current. The three-phase currents are distorted in equal amounts, the THD is 27.10%, and the magnitude of the current is 17.31A as shown in Fig. 5(b). The IPEA computes the reference grid current and voltage at the PCC, which are then used to generate the switching pulses for the shunt and series inverters, respectively.

Fig. 5. Simulation results of the behavior of a UPC under distorted voltage and balanced non-linear load conditions.

Fig. 6. Simulation results of the behavior of a UPC under voltage sag/swell and balanced non-linear load conditions.

Fig. 7. Simulation results of the behavior of the UPC under unbalanced load conditions.

The series active power filter injects compensating voltage for distortion from 0.1s to 0.2s through the series transformer as shown in Fig. 5(c). The injected current by the shunt active power filter is shown in Fig. 5(d). Hence, the voltage at the PCC and the grid current are maintained as pure sinusoidal in phase quantities as shown in Fig. 5(e) and Fig. 5(f). The voltage and current THD are reduced to 0.18% and 3.67% as tabulated in Table I. Fig. 5(g) shows that the DC link voltage is kept constant with the IPEA algorithm. When the test system is simulated for a balanced case, the profiles shown in Fig. 5 and Fig. 6 are for a single phase for better clarity of depiction.

2) Grid Voltage with Sag/Swell and a Balanced Non-Linear Load : A voltage swell of 30% is introduced in the grid voltage between 0.1s and 0.2s. Later, at 0.22s, a sudden 30% sag is introduced into the system as shown in Fig. 6(a). In addition, a non-linear load connected to the PCC draws adistorted current as shown in Fig. 6(b). To keep the voltage at the PCC at its rated value, the series inverter injects an out-of-phase voltage through the series transformer to compensate for the voltage swell from 0.1s to 0.2s, and it injects an in-phase voltage to compensate for sag from 0.22s to 0.32s as observed in Fig. 6(c). The injected current by the shunt inverter is shown in Fig. 6(d). Thus, the IPEA controlled UPC keeps the load voltage, as seen in Fig. 6(e), at the desired level during the sag and swell. In addition, the grid line current is also sinusoidal as can be seen in Fig. 6(f). The real power requirement of the series active power filter is provided by the shunt active power filter through the common DC link of both filters.

The simulation results shown in Fig. 5 and Fig. 6 show that with the IPEA control, voltage sags, swell, harmonics and source current harmonics have been greatly reduced to within acceptable limits with the implementation of the UPC at the PCC. It can also be seen that the proposed control algorithm made the source currents into balanced, sinusoidal currents with a unity power factor. In addition, in all of the operating conditions, the power factor drawn from the supply is nearly unity (around 0.998). The source current THD% has been reduced to within the levels set by IEEE standards.

B. Distorted Grid Voltage and Unbalanced Non-Linear Load

The behavior of the UPC with IPEA control for unbalanced non-linear load conditions is shown in Fig. 7. Distortions in the three phases of the source voltage are introduced into the system at 0.1s to 0.2s as can be seen in Fig. 7(a). The sinusoidal voltage at the PCC after compensation is shown in Fig. 7(b). An unbalance in the load is introduced by connecting an additional star connected load to the three phases on the AC side of the non-linear load. The three-phase non-linear unbalanced current is shown in Fig. 7(c), and the unbalanced currents in the three phases are shown in Fig. 7(e) through Fig. 7(g). The control algorithm responds instantaneously during dynamic conditions and the shunt active power filter injects current, as shown in Fig. 7(h) through Fig. 7(k), to keep the source current in all three phases sinusoidal, as shown in Fig. 7(d), and in-phase with the voltage at the PCC. The UPC compensates for the voltage and source current distortions as well as the load unbalance in the system. The source current THD% has been brought down so that it is within the levels set by IEEE standards.

Observations of the simulation results are tabulated in Table I. Table I compares the %THD values of the main current with and without a UPC when shunt compensation is provided by the IPEA control. The source must only supply the fundamental current while the harmonic current is supplied by the shunt active power filter of the UPC. Therefore, a reduction in the source current can be observed after compensation. In addition, in the case of distortions in the voltage, the THD is reduced from 20.62% to a value less than 1%. During a sag in the supply, the desired value is injected and the voltage at the PCC is increased from 173.2V to 230.9V with the UPC. During a swell in the supply, the series inverter of the UPC injects a voltage out-of-phase and the voltage at the PCC is reduced from 300.2V to 230.9V. From the tabulation in Table I, it can be observed that when the load currents are unbalanced the source current becomes balanced and the THD% for each of the phases is reduced to 3.64%, 3.63% and 3.67%.

Ⅳ. LABORATORY IMPLEMENTATION

The IPEA is implemented in MATLAB/Simulink with a dSPACE DS1104 real time simulator. By using the MATLAB/ Simulink Real-Time-Workshop (RTW) function, a Simulink model with dSPACE interface blocks is linked to the real- time dSPACE DS1104 processor board. Then this code is compiled by a compiler and linked to the real-time dSPACE DS1104 processor board. With the dSPACE Control Desk graphical user interface software, the monitoring of the performance of the control algorithm in real time is made possible. Moreover, it is possible to alter the controller parameters and to see the performance in real time. The experimental results were recorded with the help of a digital storage oscilloscope and a power analyzer (Fluke make model: 435-II). The laboratory set up is shown in Fig. 8, and the system parameters are mentioned in the Appendix.

Fig. 8. Laboratory setup.

Balanced source voltages of 400V are applied across athree-phase thyristor controlled converter with a 3kVA rating. Distortions are introduced for the experimental implementation, the firing angle of the thyristor controlled converter is set to 30 degrees and it feeds a resistive load. The load draws a non-linear current making the power factor less than unity i.e. the power factor in this case is 0.7. The two back to back connected inverters of the UPC are SEMIKRON three-phase IGBT based inverters, 20 kVA, 10A, 20 kHz PWM with a DC link capacitor of 1650µF/ 800V. The system was operated under distorted balanced source/balanced load and balanced source/unbalanced load conditions. The IPEA controller senses the load current, supply voltage and generate PWM pulses to the IGBT inverter. The shunt active power filter is connected to the three-phase supply at the PCC through a 10mH coupling reactance. The DC link voltage is maintained by comparing it with its reference value during voltage or load current changes.

A. Distorted Grid Voltage and Balanced Non-Linear Load

A distorted supply voltage and current are observed in Fig. 9(a). The effectiveness of the IPEA control is observed from the resultant waveforms recorded through dSPACE control desk and are depicted in Fig. 8. The fundamental voltage is attained from the distorted voltage using the bandpass output of the biquad filter to make the voltages balanced and sinusoidal. Then unit templates from the balanced voltages are used to produce compensation signals, as can be seen in Fig. 9(b), using the IPEA. This algorithm diminishes the THD of the source current from 29.8% to 3.6% and the voltage THD from 20.62% to less than 1%. It also makes the power factor nearly unity at the PCC as observed in Fig. 9(c).

Fig. 9. Experimental results using dSPACE DS1104. (a) Phase a: distorted source voltage and non-linear load current. (b) Source current before compensation, filer current and source current after filter operation. (c) Voltage and current at the PCC after compensation.

(a)

(b)

(c)

B. Balanced Grid Voltage and Unbalanced Non-Linear Load

The IPEA control operates effectively during unbalanced load conditions. To cause unbalanced load conditions, a star connected unbalanced resistive load is connected in parallel to the AC load. The unbalanced non-linear currents, as depicted in Fig. 10(a), in the three phases are 3.96A, 3.36A and 4.05A. In addition, the THD% in phases a, b and c are 34.08%, 35.96% and 28.04%, respectively. The unbalance in the load is taken care of in the determination of the reference currents itself. In addition, the three-phase currents injected to compensate for the unbalance are shown in Fig. 10(b). The IPEA control algorithm makes the source current in the three phases is balanced with the values 3.26A, 3.23A and 3.19A as observed in Fig. 10(c). After compensation, the source currents become sinusoidal and balanced at the PCC where the THD% in the three phases are 3.64%, 3.63% and 3.67%. Fig. 12 shows the voltage swell compensation by the UPC. The test results are analyzed using a FLUKE make power quality analyzer.

Fig. 10. Experimental results using dSPACE DS1104. (a) Unbalanced currents in three phases. (b) Compensation currents. (c) Balanced sinusoidal source current of three phases.

(a)

(b)

(c)

The UPC reduces the total harmonic distortion in the source current from 27.8% to 3.6%. The shunt active power filter injects the remaining harmonics in the source current, compensates the reactive power and possess a unity power factor. Relevant results are shown in Fig. 12(a) through Fig. 12(d). The reduction in the source current, which is observed as harmonic current, is being provided by the shunt active power filter. From the harmonics table of Fig. 12(c) and Fig. 12(d), it can be seen that the current THD is reduced from 29.8% to 3.6%.

C. Grid Voltage Sag/Swell and Balanced Non-Linear Load Current

The source voltages at the PCC and the load currents are shown in Fig. 11. In addition, THD of the load currents is approximately 30%. The load current and reference current generated by the control algorithm are shown in Fig. 11(a). The voltage sag injected in-phase voltage and the compensated voltage at the PCC are shown in Fig.11(b). The sensed actual filter current and the source current are observed in Fig. 11(c). The voltage at the PCC and source current are sinusoidal and the THD has been reduced to acceptable limits i.e. less than 5%.

Fig. 11. Experimental results. (a) Load current, real part of the fundamental and reference compensation current in phase a. (b) Voltage sag, injected voltage and voltage at the PCC after compensation. (c) Actual filter current and source current of phase a.

(a)

(b)

(c)

Fig. 12. Experimental results. (a) Phase a voltage with swell and non-linear current before compensation. (b) Phase a voltage at the PCC after compensation and current with the UPC. (c) THD% of the source current spectrum without compensation. (d) THD% of the source current with the UPC for a balanced source and a balanced load (in a Fluke power quality analyzer).

(a)

(b)

(c)

(d)

Ⅴ. CONCLUSIONS

A modified control algorithm for a UPC based on simple mathematical concepts is presented in this paper. The IPEA was verified to generate balanced reference currents in both distorted and unbalanced conditions. This IPEA was studied and a UPC using this algorithm was simulated in MATLAB/ Simulink with a three-phase thyristor converter fed RL load. It has been found to yield a marginally better response time for dynamic load conditions when compared to existing algorithms. In addition, it is simpler than the existing power filtering algorithms. From MATLAB/Simulink based simulation studies, the UPC was verified to operate satisfactorily by simultaneously compensating voltage and current disturbances under different operating conditions. The control algorithm gives satisfactory performance under steady and dynamic conditions. After the implementation of a IPEA controlled UPC, the phase voltage and current are in-phase and sinusoidal. This control algorithm has been found to be very effective. The grid current THD remains within 5% and the THD of the source voltage is found to be less than 3% while the individual harmonics are less than 1%. The effectiveness of the IPEA has been verified and analyzed through simulations and laboratory implementation.

APPENDIX

System Parameters: AC supply: three-phase, 400V, 50Hz; line impedance=0.2mH,0.1W; load: full converter with R-L= 20W, 500mH; DC-link voltage=700V; DC link capacitor= 4.5mF; interfacing inductor of the shunt compensator=3mH; series and shunt inverter rating=5kVA; dSPACE controller DS1104; sampling period of the DS1104=100ms.

ACKNOWLEDGMENT

The authors wish to thank Amrita Vishwa Vidyapeetham, Coimbatore and Jyothi Engineering College, Cheruthuruthy for their support in carrying out research.

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Sindhu S. was born in Kerala, India. She received her B.E. degree in Electronics and Communication Engineering from Bharatiar University, Coimbatore, India; and her M.Tech degree in Power Electronics from Amrita Vishwa Vidyapeetham, Coimbatore, India, where she is presently working towards her Ph.D. degree in the Department of Electrical Engineering. She has been working at Jyothi Engineering College, Cheruthuruthy, India, since August 2010. Her current research interests include power electronics, power quality, and custom power devices.

Sindhu M. R. was born in Kerala, India. She received her B. Tech. and M. Tech. degrees from Calicut University, Kerala, India; and her Ph.D. degree from Amrita Vishwa Vidyapeetham, Coimbatore, India. She is presently working as an Associate Professor at the Amrita School of Engineering, Coimbatore, India. Her current research interests include power quality issues and mitigation techniques, power electronic applications in power systems, flexible AC transmission systems, and electric vehicles.

T. N. P. Nambiar was born in 1942. He graduated from University of Kerala, Thiruvananthapuram, India, in 1966; and his M.E. and Ph.D. degrees in Electrical Engineering from the Indian Institute of Science, Bangalore, India, in 1976 and 1985, respectively. He was a faculty member of Engineering Colleges in Kerala for about 30 years. After his retirement in 1997, he joined the Amrita School of Engineering, Coimbatore, India. He was the Department Chairman from 2003 to 2013, and is presently a Professor Emeritus of Amrita University, Coimbatore, India. His current research interests include power electronics and power system control.