https://doi.org/10.6113/JPE.2019.19.4.944

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

SVPWM Strategies for Three-level T-type Neutral-point-clamped Indirect Matrix Converter

Nguyen Dinh Tuyen^†, Le Minh Phuong^*, and Hong-Hee Lee^**

^†,*Dept. of Electrical and Electronics Engineering, Hochiminh City University of Technology, VNU-HCM, Hochiminh City, Vietnam

^**School of Electrical Engineering, University of Ulsan, Ulsan, Korea

Abstract

In this paper, the three-level T-type neutral-point-clamped indirect matrix converter topology and the relative space vector modulation methods are introduced to improve the voltage transfer ratio and output voltage performance. The presented converter topology is based on combinations of cascaded-rectifier and three-level T-type neutral-point-clamp inverter. It can overcome the limitation of voltage transfer ratio of the conventional matrix converter and the high voltage rating of power switches of conventional matrix converter. Two SVPWM strategies for proposed converter are described in this paper to achieve the advantages features such as: sinusoidal input/output currents and three-level output voltage waveforms. Results from Psim 9.0 software simulation are provided to confirm the theoretical analysis. Hence, a laboratory prototype was implemented, and the experimental results are shown to validate the simulation results and to verify the effectiveness of the proposed topology and modulation strategies.

Key words: Indirect matrix converter, Matrix converter, Multilevel inverter, Space vector modulation

Manuscript received Jan. 4, 2019; accepted Apr. 17, 2019

Recommended for publication by Associate Editor Minh-Khai Nguyen.

^†Corresponding Author: ndtuyen@hcmut.edu.vn, Tel: +84-919142110, Hochiminh City University of Tech., VNU-HCM

^*Dept. of Electrical and Electronics Engineering, Hochiminh City University of Technology, VNU-HCM, Vietnam

^**School of Electrical Engineering, University of Ulsan, Korea

Ⅰ. INTRODUCTION

In the last three decades, the multilevel converter has been received more attention and they become widely used in high power medium voltage such as motor drives, renewable energy system. The multilevel inverter provides numerous advantages as compared to the two-level inverter: better performance of the output voltage, an increase in the DC-link voltage for a given blocking voltage capacity of the semi- conductors [1]-[4]. The multilevel inverters can be divided into three main kinds based on their topologies: diode clamped multilevel inverter (NPC), Flying capacitors multilevel inverter and Cascaded H- bridge multilevel inverter. Among all the multilevel inverters, the three-level NPC inverter is the most widely used one because it uses a low number of capacitor and can be connected to the single DC-link [5], [6]. Recently, there is growing interest in development of NPC multilevel topologies and modulation methods in order to improving output performance, reducing the common-mode voltage, reducing power switching losses, balancing the capacitor voltage [7]-[9]. In these researches, the T-Type NPC has been proposed as an alternative to the conventional NPC due to it has some advantages: higher efficiency and lower number of power switches [10]-[12]. However, despite their favorable output performance, the T-Type NPC inverter include the intermediate energy storage element, which affect the size, life-time and reliability of the inverter. With the uncontrolled rectifier stage, the distorted input current and low input power factor are the disadvantages of the conventional T-Type NPC.

Since the early 2000s, the indirect matrix converters (IMC) have been widely studied to connect a fixed frequency/voltage AC power supply with any load requiring variable frequency/ voltage without using a large component in the DC-link. It is well-known that the IMC provides some advantages such as simple commutation, nearly unity input power factor, bidirectional power flow, sinusoidal input current and sinusoidal output voltage [13]-[15]. Because of these attractive features, some researchers have focused on development the IMC topology for particular applications such as: 1) Sparse matrix converter for reduce power switches devices [16] 2) Three-to-five phase IMC converter to feed five-phase load [17]-[19] 3) Dual IMC converter to feed two three-phase loads [20], [21] or open-end winding load [22], [23] 4) Four-leg IMC for unbalanced or nonlinear load conditions [24], [25]. In these traditional IMC with single rectifier stage introduced in [13]-[25], the obtainable AC output voltage is limited to less than 0.866 times of AC input voltage. To solve this problem, an additional stage such as Z-source network added between rectifier stage and inverter stage has been used to provide the commercial AC output voltage [26]-[29].

As we mentioned before, the multi-level converters can reach higher voltage levels with low cost, easily available low voltage device. Recently, the multilevel MC was developed as a new topology from this family that combines the multilevel converter concept with a MC. There are two kinds of multilevel MC: multilevel direct MC [30]-[32] and multilevel indirect MC [33]-[36].

The multilevel IMC topology in [33]-[34] is developed from the traditional IMC by replacing the conventional six- switch inverter stage by the three-level NPC inverter. In [33], the neutral-point balancing has not been explicitly considered. In order to solve the neutral-point balancing problem, the appropriate selection and arrangement of active vectors are made to ensure that average neutral point current is obtained within a sampling period. As compare to the conventional multilevel IMC presented in [33]-[34], a new multilevel diode – clamped IMC proposed in [37] provides an outstanding advantage that is avoid neutral-point voltage balancing control. The neutral-point voltage is self-balanced due to the upper and lower DC-link voltage are supplied by two isolated rectifiers [37]. 

In order to avoid the disadvantages of the conventional NPC inverter and to extend the application of the conventional IMC in high capacity power, a three-level T-type NPC IMC is proposed in this paper. The space vector pulse width modulation (SVPWM) schemes have been preferred to the carrier-based PWM to effectively drive IMC due to its superiority such as easy change in switching sequence without re-calculation and more control freedom caused by flexible vector selection and pulse generation. We introduce two SVPWM methods to generate the output voltage of the inverter stage: one is implemented by two active vectors and one zero vector, and another is by three nearest vectors.

The presented topology with the SVPWM methods in this paper has the following features:

- The sinusoidal input/output currents are obtained.

- The topology is able to generate three-level output voltage with high voltage transfer ratio.

- The three-level T-type NPC inverter stage is fed from two isolated rectifier stages with simple algorithm to balance the neural-point voltage.

This paper is organized as follows: the operational principle of the proposed converter is introduced in Section II. Section III describes the SVPWM methods to synthesis the input current and output voltage. Section IV presents the simulation results to verify the theoretical findings. Later in Section V, the hardware systems design is described, and experimental results are discussed. Finally, Section VI presents some conclusions.

Ⅱ. THREE-LEVEL T-TYPE NEUTRAL-POINT-CLAMPED INDIRECT MATRIX CONVERTER TOPOLOGY

The topology of three-level T-type NPC IMC is shown in Fig. 1. The topology has one T- type NPC inverter connected to two six-bidirectional-switches rectifiers. The main components of this converter from the left to the right are: LC second-order low pass input filter which is placed between the mains and the current source rectifier stage to reduce the current harmonics injected into the AC source, two cascaded four-quadrant current source rectifier stage and a three-level T-type inverter stage. The maximum DC output voltage at the DC-link bus is generated by control the rectifier stage, where the maximum and medium line–to–line input voltages are chosen to form the DC–link voltage. The space vector modulation is applied to the inverter stage to generate the sinusoidal output currents with variable magnitude and frequency. The rectifier and inverter stages are controlled based on the reference input current vector and output voltage vector, respectively. Hence, the switching patterns of the two stages are mixed together to keep balanced input and output currents.

Fig. 1. Three-level T-Type neural-point-clamped Indirect Matrix Converter.

There are six bidirectional switches for each rectifier stage: S_ap1, S_bp1, S_cp1, S_an1, S_bn1, S_cn1 for rectifier-1 and S_ap1, S_bp2, S_cp2, S_an2, S_bn2, S_cn2 for rectifier-2. The upper and lower DC-link voltage (v_PO, v_ON) are generated by rectifier-1 and rectifier-2, respectively, and they are used to feed the T-type three-level NPC inverter. From the T-type NPC topology shown in Fig. 1, each leg of a T-type NPC inverter has four IGBTs and four anti-parallel diodes. The bidirectional switch (S_x2 and S_x3, x=A,B,C) is connected between the midpoint of DC-link voltage and the output terminal, and the other two switches (S_x1 and S_x4) are arranged like the conventional two-level inverter. The number of power switches of presented topology in this paper has less than those of conventional multilevel IMC six diodes.

Ⅲ. SPACE VECTOR PULSE WIDTH MODULATION STRATEGIES

A. Rectifier Stage Control

From Fig. 1, it may be noted that rectifier-1 and rectifier -2 are fed by two AC power supplies which have the same magnitude and frequency. The rectifier-1 and rectifier-2 generate the same output voltage in the DC-link. Therefore, without missing the generality of the analysis and avoid the duplication, only space vector modulation for rectifier–1 is presented.

It is assumed that the three phase input voltages are balanced and given as follows:

       (1)

where V_in and ω_in are the amplitude and angular frequency of the input phase voltage, respectively.

As described in [14]-[16], there are 8 possible combinations for the rectifier switches, which consist of six active current vectors (I_ab, I_ac, I_bc, I_ba, I_ca, I_cb) and three zero current vectors (I_aa, I_bb, I_cc) in the space vector diagram. The active vectors divide the space vector into six sectors as shown in Fig. 2. Assume that the reference input current vector I_ref is located in sector 1 (). Then, the two nearest active vectors I_ab and I_ac are chosen to synthesize the reference current vector without the zero current vectors.

Fig. 2. Space vector diagram of the rectifier stage.

From Fig. 2, the duty ratio of the two active vectors, which are used to synthesis the reference input current vector, are given as:

      (2)

       (3)

where m_rec is the modulation index of rectifier stage.

In order to complete the sampling period, the zero vector is used. However, to maintain the maximum DC-link output voltage, the zero vector is neglected. Therefore, the duty cycle and for two active vectors I_ab and I_ac are recalculated as follows [16]-[23]:

           (4)

          (5)

In sector 1, switch S_ap1 is in the ON state during the sampling time T_s, and the switches S_bn1 and S_cn1 are modulated to obtain two higher line-to-line input voltages at DC-link bus. During one sampling period, switches S_bn1 and S_cn1 are applied for times d_xT_s and d_yT_s , respectively.

From (4) and (5), the DC-link voltage has two values, v_ab and v_ac , for the duty ratios d_x and d_y , respectively. And, in order to ensure a balance between the upper DC-link voltage (v_PO) and lower DC-link voltage (v_ON). , output voltage of each rectifier should be same. Considering in one sampling period. the average value of the DC-link voltages which are generated by the rectifier-1 and rectifier-2 is:

      (6)

Then, DC-link voltage, which is used to feed the three-level T-type NPC stage, is:

         (7)

From (7), the minimum value of the V_DC is

      (8)

Table I summarizes the switching states of the rectifier-1 and rectifier-2 and DC-link voltages according to the input angular frequency.

TABLE I  DUTY CYCLES OF ACTIVE VECTORS AND DC-LINK VOLTAGES

Input voltage phase wint	Sector	ON switch	Modulated switches	Duty ratios	Instantaneous DC link voltages (VDC )	Average DC link voltage vPN VDC
		Rectifier -1		(dx , dy )	VPO
		Rectifier -2		(dx , dy )	VON
-π/6 .. π/6	1	Sap1	(Sbn1 , Scn1 )	(-vb /va, -vc /va)	(vab , vac )
		Sap2	(Sbn2 , Scn2 )
π/6 .. π/2	2	Scn1	(Sbp1 , Sap1 )	(-vb /vc , -va /vc )	(vbc , vac )
		Scn2	(Sbp2 , Sap2 )
π/2 .. 5π/6	3	Sbp1	(Scn1 , San1 )	(-vc /vb , -va /vb )	(vbc , vba )
		Sbp2	(Scn2 , San2 )
5π/6 .. 7π/6	4	San1	(Scp1 , Sbp1 )	(-vc /va , -vb /va )	(vca , vba )
		San2	(Scp2 , Sbp2 )
7π/6 .. 9π/6	5	Scp1	(San1 , Sbn1 )	(-vb /vc , -vb /va )	(vcb , vca )
		Scp2	(San2 , Sbn2 )
9π/6 .. 11π/6	6	Sbn1	(Scp1 , Sap1 )	(-vc /vb ,-va /vb )	(vab , vcb )
		Sbn2	(Scp2 , Sap2 )

B. Inverter Stage Control

It is useful to consider the converter shown in Fig. 1 as a three-level T-type NPC with three-phase output voltage V_A, V_B, V_C supplied by a variant DC-source shown in (7). Because the average value of DC-link voltage is not constant, the modulation methods for inverter stage are modified and coordinated with the rectifier stages control to obtain the balanced sinusoidal output currents.

In order to generate the desired output phase voltages for the inverters, SVPWM techniques have been widely used for industrial applications. In the SVPWM methods, the reference voltage space vector is represented in complex form:

     (9)

where m_inv is the modulation index of inverter stage which is defined as in (10), q is the output angular frequency.

             (10)

The maximum magnitude of V_ref is the radius of the largest circle that can be inscribed in the space vector diagram. The medium vectors have the same length as the maximum V_ref.

        (11)

Fig. 3 shows the space vector diagram for the three-level T-type NPC inverter. The inverter has 27 switching states corresponding to all the combinations of connections of each phase to the DC-link points. For example, (1,0,-1) corresponds to the connection of phase A to point P, phase B to O, and phase C to point N. There are a total number of 24 active vectors which can be split into three categories: large, medium and small vectors. There are 6 large vectors, 6 medium vectors, 12 small vectors and 3 additional zero vectors.

Fig. 3. Space vector diagram of the inverter stage.

The SVPWM methods generates the reference voltage through three steps: the first step is to determine the location of the V_ref vector and find three vectors to synthesis it. In the next step, the duty ratio of these effective vectors is also calculated within a sampling period. In the last step, the switching pattern is arranged to reduce the switching commutation number. In this paper, two SVPWM methods are developed.

1) Method I: SVPWM with Zero-Current Commutation

In this method, the space vector diagram is divided into twelve sectors with 30° angle difference between medium and large vectors as shown in Fig. 4(a). It is assumed that the reference output voltage vector is located in sector 1. This method uses the two active vectors (medium and large vectors) and one zero vector to synthesis reference output voltage vector. They are applied with the duty cycles d₇, d₁₃ and d₀, respectively. The reference output voltage is described as

        (12)

Fig. 4. Space vector diagram. (a) Sector divided of the space vector diagram for the inverter stage of SVPWM Method I. (b) Sector and region divided of the space vector diagram for the inverter stage of SVPWM Method II.

(a)

(b)

In (12), the sum of d₀, d₇ and d₁₃ should be unity, and they are given as follows:

       (13)

        (14)

       (15)

Once all affected vectors and corresponding duty cycles for both stages are determined, they are combined properly to generate the final PWM for all power switches. The complete modulation is obtained by multiplying corresponding duty cycles determined by the rectifier and the inverter stages like the conventional IMC. When the line-to-line input voltage v_ab applied to DC-link voltage, the duty cycles (d_7(ab), d_13(ab), d_0(ab)) of active and zero vectors (V₇, V₁₃, V₀) are calculated as following:

     (16)

Similarly, when the line-to-line input voltage v_ac applied to DC-link voltage, the duty cycles (d_7(ac), d_13(ac), d_0(ac)) are given in (17):

      (17)

Fig. 5 shows the switching states of the rectifier and the inverter stages in case that the rectifier stage operates in sector 1 and the reference output vector is also located in sector 1. In this example, the upper switches of phase a (S_ap1, S_ap2 ) are on state, while the lower switches of phase b and phase c (S_bn1, S_cn1, S_bn2, S_cn2 ) are modulated. The DC-link voltage has two levels: 2v_ab and 2v_ac. The voltage space vectors at the inverter stage are arranged in a double-sided switching sequence, V₀₀₀ → V_10-1 → V_1-1-1 → V_10-1- → V₀₀₀ → V_10-1 → V_1-1-1 → V_10-1 → V₀₀₀, but with unsymmetrical halves because each half of switching sequence is applied to different level of DC-link voltage.

Fig. 5 Switching pattern of SVPWM Method I.

The SVPWM Method I provides a simple commutation. In the commutation strategy, the inverter stage could be switched in to free-wheeling state (vector V₀) and then the rectifier stage could commutate as shown in Fig. 5. Therefore, the commutation between the bidirectional switches in the rectifier stage occurs at zero current. The commutation between two switches S_bn1 and S_cn1 is implemented by using dead time in order to avoid the short circuit between two input lines.

2) Method II: The Nearest Three Space Vector PWM

In Method II, the space vector diagram is divided into six sectors with 60° angle difference between two adjacent large vectors as shown in Fig. 4(b), where four minor regions are included for each major sector.

The reference vector is synthesized by using the space vector modulation of the three switching state vectors that are nearest to the reference vector at every sampling instant. The nearest three vectors are selected from the reference vector in one of the four small triangles illustrated in Fig. 4(b). The dwell time is defined as the duty cycle time of the switches during the modulation sampling period. The relationship of the dwell time with the active vectors is given in (18):

      (18)

where d_i, d_j, d_k are duty cycles of three vectors, V_i, V_j, V_k, respectively.

TABLE II  DUTY CYCLES OF ACTIVE VECTORS IN SECTOR 1

Region	di		dj		dk
1
2
3
4

The duty cycle of each selected vector is determined from the equations in Table II. The sequence of the selected vectors within one sampling period in sector 1 is determined according to the region of the reference voltage vector :

Region 1: The reference voltage V_ref is synthesized by the combination of two small vectors out of (V₁₀₀, V_00-1 V_0-1-1, V₁₁₀) and two zero vectors (V₀₀₀, V_-1-1-1). From these switching states, the switching sequence becomes V_-1-1-1 → V_0-1-1 → V_00-1 → V₀₀₀  ®V₁₀₀ → V₁₁₀ → V₁₁₁ → V₁₁₀  → V₁₀₀ → V₀₀₀  → V_00-1 →  V_0-1-1 → V_-1-1-1.

Region 2: The reference voltage V_ref is synthesized by the combination of three active vectors: two small vectors out of (V₁₀₀, V_00-1 V_0-1-1, V₁₁₀) and one medium vector (V_10-1). From these switching states, the switching sequence becomes V_0-1-1 → V_00-1 → V_10-1 → V₁₀₀ → V₁₁₀ → V₁₀₀ → V_10-1 → V_00-1 → V_0-1-1.

Region 3: The reference voltage V_ref is synthesized by the combination of three active vectors: one small vector between (V₁₀₀, V_0-1-1), one medium vector (V_10-1) and one large vector (V_1-1-1). From these switching states, the switching sequence becomes V_0-1-1 → V_1-1-1 → V_10-1 → V₁₀₀ → V₁₀₁ → V_1-1-1 →  V_0-1-1.

Region 4: The reference voltage V_ref is synthesized by three active vectors: one small vector between (V₁₁₀, V_00-1), one medium vector (V_10-1) and one large vector (V_11-1). The switching sequence becomes V_00-1 → V_10-1 →  V_11-1  →  V₁₁₀ → V_11-1 → V_10-1 → V_00-1.

Similar to the SVPWM Method I, the switching patterns of the inverter stage is separated into two groups. As described in Section III. A, since there are two portions in each switching period, the dwell time of active and zero vectors in the inverter stages are also distributed to each portion.

During the first switching state, I_ab is applied to the rectifier stage, and the duty cycles (d_i(ab),d_j(ab),d_k(ab)) of three vectors V_i, V_j, and V_k are determined as following:

      (19)

During the second switching state, I_ac is applied to the rectifier stage, and the duty cycles (d_i(ac),d_j(ac),d_k(ac)) of three vectors V_i, V_j, and V_k are given in (20):

      (20)

Fig. 6. shows the switching pattern of the rectifier and inverter stages of Method II in case that the reference input current is located in sector 1 and reference output voltage are located in region 1 of sector 1.

Fig. 6. The switching pattern of Method II.

C. Voltage Transfer Ratio

If we define m as the voltage transfer ratio between the output and input voltages, then

       (21)

From (8), (11), and (21), the maximum voltage transfer ratio of the three-level T-type NPC IMC is:

     (22)

Ⅳ. SIMULATION RESULTS

Numerical simulations are carried out using Psim 9.0 software to evaluate the performance. The simulation parameters are given in Table III.

TABLE III  SIMULATION PARAMETERS

Input voltage (Vin )	100 V
Input frequency (fin )	50 Hz
R load	25 Ω
L load	12 mH
Output frequency (fout )	40 Hz
Sampling period (Ts ) Filter: Lf, Cf	100 kHz 1.4 mH, 22µF
Voltage transfer ratio (m) Transformer ratio Lp Ls Lt	1.4 1:1:1 0.05 mH 0.05 mH 0.05 mH

Fig. 7 shows the upper and lower DC-link voltages, v_PN and v_ON, which are generated by the rectifier-1 and rectifier-2, respectively. In the rectifier stage control, the DC-link voltage does not reach to zero because the zero vectors are eliminated. The DC-link voltage is formed by the two line-to-line input voltages, and the average value of DC-link voltage vacillates with the frequency of six times of input voltage frequency.

Fig. 7. The simulated DC-link voltage: v_PO and v_ON.

Figs. 8-11 show the simulation results of currents and voltage waveforms at input and output sides with the SVPWM Method I and SVPWM Method II, respectively, at voltage transfer ratio m = 1.4. It can be seen that both of two SVPWM methods achieve the sinusoidal input currents and balanced output currents. The input power factor is near unity and the main input current (i_as) is kept sinusoidal waveform due to input filter even though the input current of the converter (i_a) contains a lot of switching noises due to the high-frequency switching operation.

Fig. 8. The simulation results of input current of converter (i_a), input current of power source (i_as) voltage with SVPWM Method I.

Fig. 9. The simulation results phase voltage (v_A), line-to-line output voltage (v_AB) and three-phase output current with SVPWM method I.

Fig. 10. The simulation results of input current of converter (i_a), input current of power source (i_as) voltage with SVPWM Method II.

Fig. 11. The simulation results phase voltage (v_A), line-to-line output voltage (v_AB) and three-phase output current with SVPWM Method II.

Figs. 12 (a)-(c) show the output phase voltage and their fast Fourier transform (FFT) analysis with the conventional POD PWM method presented in [37], the PWM Method I and the PWM method II, respectively at an output frequency of 40 Hz. It is clear seen that the PWM Method II contains fewer harmonic components compared to those in the PWM Method I and the conventional POD PWM method.

Fig. 12. The waveforms of output phase voltages and their FFT analysis. (a) Conventional POD PWM method [37]. (b) Method I (c) Method II.

(a)

(b)

(c)

According to the simulated results, the proposed IMC topology provides the sinusoidal input current on both of input and output sides with three-level output voltage. The different output voltage waveforms result from different modulation methods which depend on the reference output voltage vector in the inverter stage.

Ⅴ. EXPERIMENTAL RESULTS

To validate the proposed SVPWM methods, experiments for the SVPWM methods are carried out based on the simulation by using the three-phase power supply, isolated transformer, LC filter and a three-phase RL load which are identical to the simulation parameters. The primary, secondary and tertiary leakages of the transformer are: 1.75 mH, 1.82 mH and 1.68 mH, respectively.

Fig. 13 shows the experimental setup in laboratory. The control board consists of DSP TMS320F28377S operating at a clock of 200MHz and a CPLD Altera EPM7218. The DSP determines the input/output sector and calculates the duty cycles of the effective vectors in both of two stages. The CPLD generates the gating signals and conducts the four-step commutation. A sensor board uses voltage sensor LEM LV25-P and current sensor LEM LA2-P5 to measure voltages/ currents and to detect the voltage/current sign for safe commutation. The IGBTs, SK60GM123, have been used to implement the bidirectional switch in the power circuit at the rectifier and inverter stages. 

Fig. 13 Experimental setup of multilevel IMC.

The experimental results shown in Fig. 14 are input sector, the upper and lower DC-link voltages which are generated by the Rectifier-1 and Rectifier-2, respectively. Fig. 15 shows the DC-link voltage and two line-to-line input voltages. It can be seen that the DC-link voltage is shaped by line-to-line input voltage. In can be seen that the DC-link voltage is formed by v_ac and v_ab in sector 1. The DC-link voltage waveforms are not affected by the inverter stage control and do not decrease to zero because no zero switching states in the rectifier stage are used.

Fig. 14. The experimental results of upper and lower DC-link voltage according to the input sector.

Fig. 15. The experimental results of upper DC-link (V_PO) and two line-to-line input voltages (v_ab and v_ac).

Figs. 16-17 show the input current/voltage and output current/voltage, respectively, with the SVPWM Method I. The experimental results with the SVPWM method II are shown in Figs. 18-19, which correspond to the experimental results shown in Figs. 16-17. It is evident that output current shows the sinusoidal waveform. In Figs. 16 and 18, the input current of the power converter (i_a) contains a lot of switching harmonics and its fundamental component is in phase with input voltage (v_a). By using low pass filter (LC), the input current of power source (i_as) is almost sinusoidal waveform.

Fig. 16. The experimental results of input current/voltage with the SVPWM Method I

Fig. 17. The experimental results of phase output voltage, line- to-line output voltage and output current with the SVPWM Method I.

Fig. 18. The experimental input current/voltage with the SVPWM Method II.

Fig. 19. The experimental phase output voltage, line-to-line output voltage and output current with the SVPWM Method II.

Figs. 20 a,b,c show the harmonic spectrum of the phase output voltage of three methods: conventional carrier based- PWM method [37], Method I and Method II, respectively. As the spectrum indicates, the proposed method II shows a good phase output voltage as compared to that of the conventional POD PWM method and Method I.

Fig. 20. The experimental results of output phase voltages and their FFT analysis. (a) Conventional POD PWM method [37]. (b) Method I. (c) Method II.

(a)

(b)

(c)

Figs. 21-22 show a comparison between two SVPWM methods and the conventional POD PWM method in terms of input current total harmonic distortion (THD) and output voltage THD versus voltage transfer ratio. As can be seen, the THD of output voltage with the SVPWM method II is lower than that with the SVPWM Method I and conventional POD PWM method, because, in Method I and conventional POD PWM method, the reference output voltage vector is synthesized by one medium vector and one large vector, while the reference output voltage vector is generated by three nearest vectors in Method II. At high modulation index, the harmonics of output voltage with the conventional POD PWM method is higher than that with the Method I. By having better quality output voltage waveform in terms of harmonic content, the distortion in the input current is also reduced with the Method II.

Fig. 21. The THD for output phase voltage.

Fig. 22. The THD for input current.

From the experimental results from Figs. 16-20, we can see that the currents of the input side with both two SVPWM methods are nearly sinusoidal. On the other side, the load current satisfies the sinusoidal waveform condition. The SVPWM method in the inverter stage determines the line- to-line output voltage waveforms. The waveforms of line-to- line output voltage of two methods are different. These results agree well with theories analysis and simulation results

Ⅵ. CONCLUSION

In this paper, the T-type NPC inverter and cascaded rectifier are integrated to implement high performance three-level IMC converter. The input to this matrix converter is three-phase AC power supply and the output is three-level three-phase load. Two SVPWM methods are presented the with the voltage transfer ratio can reach 1.772. In order to obtain high gain of voltage transfer ratio, the two higher line-to-line input voltage is applied to the rectifier stage. In the inverter stage control, two active vectors, medium and large vectors are used to synthesize the reference output voltage vector with zero-current commutation in Method I while three nearest vectors are used to generate the reference output voltage vector in Method II. Simulation and experimental results are provided to verify the theoretical analysis for the presented topology and modulation methods.

ACKNOWLEDGMENT

This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 103.99-2015.102.

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Nguyen Dinh Tuyen was born in Binh Dinh province, Vietnam, in 1982. He received the B.S. degree in electrical engineering from University of Technology, Ho Chi Minh City, Vietnam, in 2004 and Ph.D degree from University of Ulsan, Ulsan, Korea in 2012. He is currently lecturer for the Faculty of Electrical and Electronics Engineering, University of Technology, Ho Chi Minh City, Vietnam. His research interests include power electronics, electrical machine drives, low cost inverter and renewable energy, especially matrix converter.

Le Minh Phuong was born in Vietnam, in 1973. He received M.S. degree in Electrical Engineering from Kharkov State Academy, Kharkov, Ukraine, in 1997; and the Ph.D. degree from the Department of Automated Electromechanical Systems, Kharkov National Technical University, Kharkov, Ukraine, in 2001. He is currently working as a Lecturer in the Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam. His current research interests include power converters in microgrids, renewable energy, power electronics, power converters, and motor drives.

Hong-Hee Lee received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, in 1980, 1982 and 1990, respectively. From 1994 to 1995, he was a Visiting Professor at Texas A&M University, College Station, TX, USA. Since 1985, he has been a Professor in the Department of Electrical Engineering in the School of Electrical Engineering, University of Ulsan. He was also the Director of the Network-based Automation Research Center (NARC) from 2002 to 2018, which is sponsored by the Ministry of Trade, Industry and Energy. His current research interests include power electronics, network-based motor control, and renewable energy. Dr. Lee is a Member of the Institute of Electrical and Electronics Engineers (IEEE), the Korean Institute of Power Electronics (KIPE), the Korean Institute of Electrical Engineers (KIEE), and the Institute of Control, Robotics and Systems (ICROS). He served as the President of KIPE in 2014.