사각형입니다.

https://doi.org/10.6113/JPE.2019.19.4.989

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Fault-Tolerant Control for 5L-HNPC Inverter-Fed Induction Motor Drives with Finite Control Set Model Predictive Control Based on Hierarchical Optimization


Chunjie Li*, Guifeng Wang, Fei Li*, Hongmei Li*, Zhenglong Xia*, and Zhan Liu*


†,*Department of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou, China



Abstract

This paper proposes a fault-tolerant control strategy with finite control set model predictive control (FCS-MPC) based on hierarchical optimization for five-level H-bridge neutral-point-clamped (5L-HNPC) inverter-fed induction motor drives. Fault- tolerant operation is analyzed, and the fault-tolerant control algorithm is improved. Adopting FCS-MPC based on hierarchical optimization, where the voltage is used as the controlled objective, called model predictive voltage control (MPVC), the postfault controller is simplified as a two layer control. The first layer is the voltage jump limit, and the second layer is the voltage following control, which adopts the optimal control strategy to ensure the current following performance and uniqueness of the optimal solution. Finally, simulation and experimental results verify that 5L-HNPC inverter-fed induction motor drives have strong fault tolerant capability and that the FCS-MPVC based on hierarchical optimization is feasible.


Key words: Fault-tolerant capability, Finite control set model predictive control (FCS-MPC), Five-level H-bridge neutral-point- clamped (5L-HNPC) inverter, Hierarchical optimization


Manuscript received Oct. 10, 2018; accepted Mar. 21, 2019

Recommended for publication by Associate Editor Zheng Wang.

Corresponding Author: wgfmy@163.com, Tel: +86-516-8353-6607, Fax: +86-516-8388-2453, Jiangsu Normal University

*Department of Electrical Engineering and Automation, Jiangsu Normal University, China



Ⅰ. INTRODUCTION

Electric drive systems are exposed to rigorous operating conditions, which may lead to faults related to the induction motor and the inverter. A recent survey shows that about 38% of the faults in variable-speed drives are due to semiconductor power device failures [1]. Semiconductor power devices are considered to be the most fragile components of electric drives [2]. Fault-tolerant capability to improve reliability is effective for electric drives [3]-[5]. At present, inherent redundancy allowing for the fault-tolerant operation of drives with no additional hardware can be divided into two types of schemes. These schemes are multiphase machines [5]-[7] and multilevel inverters [8].

The multiphase machines with multiple sets of windings in [5]-[7] have numerous advantageous features when compared to their three-phase counterparts. The number of phases decreases the stator current stress. These multiphase machines are used in applications that require lower noise and vibration. In addition, increasing the number of phases can offer stronger fault tolerance. However, these machines have higher manufacture costs and increased weight [3]. At present, multiphase drives are used for high-power low-voltage applications. Due to their mature motor body, three-phase motor drives are extensively utilized in modern industry. To improve output voltage levels and fault tolerance, multilevel converters (MCs) are an interesting technology for medium/ high-voltage (MV/HV) and high-power applications [8]-[12]. The three-level neutral point clamped (3L-NPC) converter [13]-[15] with its good fault-tolerance, is still one of the most popular converter topologies for MV drive applications from 3kV to 4kV [14]. The five-level neutral point clamped (5L- NPC) converter in [10], [13]-[16] can realize an output voltage level of up to 6.6kV with standard semiconductors and no transformer. However, the 5L-NPC converter has difficulty in balancing the voltage of capacitors. A five-level H-bridge NPC (5L-HNPC) converter was presented in [17], [18]. When compared with the traditional 5L-NPC inverter, the output voltage amplitude of the 5L-HNPC inverter is double that of the traditional five-level inverter. In addition, when the power devices of the drive system break down, the reconfiguration inverter, due to its self-fault-tolerant function, becomes a 3L-NPC inverter.

Traditional modulation methods, such as sinusoidal modulation and space vector modulation, can be complex. During the last decade, model predictive control (MPC) has received a lot of attention [16]. MPC does not employ modulation. Instead, it relies on the switching state of power converters, where only a finite number of output states are available. These states are evaluated in order to select the optimal control objectives. This approach is known as finite- control-set MPC (FCS-MPC) [16]. The FCS-MPC strategy has been applied to a wide range of power converters [19]-[24], where it has several advantages such as a fast-transient response, simple implementation, and straightforward handling of nonlinearities and constraints [16]. Thus, fault-tolerant control with FCS-MPC is presented in [6], [20].

Since the conventional FCS model predictive current control (FCS-MPCC) [11] method selects optimal vectors as the next switching cycle through multiple current predictions, a novel FCS model-predictive voltage control (FCS-MPVC) method is realized by a single voltage prediction for the reference voltage, which can reduce the prediction algorithm.

There are many control objectives for multilevel inverters. These objectives include voltage jump limits, current following control, and switching frequency limits. When the traditional weighting factor method is used to optimize the performance function, multiple weighting factors need to be tuned [20]. Therefore, configuring a single weighting factor to meet the desired control objectives of a designer is difficult. Considering the conflict of each optimization performance index, when one performance indicator is over-optimized for a 5L-HNPC inverter, it is inevitable that the other performance indicators become worse. In addition, weighting factor tuning is difficult. At present, there is no uniform and effective solution. However, hierarchical control [25] can suppress the weighting factor and simplify the controller.

In this paper, the fault-tolerant operation of a 5L-HNPC inverter is analyzed, which has not yet been reported. A fault-tolerant control with FCS-MPVC based on hierarchical optimization for induction motor (IM) drives is proposed, which can reduce both the modulation algorithm and the MPC algorithm.



Ⅱ. PROCEDURE ANALYSIS OF A 5L-HNPC CONVERTER


A. Structure Description

The 5L-HNPC converter topology is shown in Fig. 1 [19]. The rectifying part adopts three 12-pulse independent rectifiers, which are formed by cascaded 6-pulse rectifiers whose AC input voltages have phase-difference of 30°. The inverter part is composed of three H-bridge NPC inverters. The mid-point of the 12-pulse rectifier can be connected with the neutral point of the DC-link capacitors. This can ensure the neutral point voltage balance and simplified control algorithm for the NPC inverter.


그림입니다.
원본 그림의 이름: CLP00001f5c0003.bmp
원본 그림의 크기: 가로 4956pixel, 세로 1795pixel

Fig. 1. 5L-HNPC inverter topology structure.


To avoid short circuits in one bridge arm, the drive signals of the upper and lower power devices are complementary. For example, the switches Sa11 and Sa13, along with the switches Sa12 and Sa14 are controlled by complementary signals. Each H-bridge inverter consists of two three-level NPC half bridges to form a five-level H-bridge structure. Each of the three-level half bridges can output three levels (그림입니다.
원본 그림의 이름: CLP00001f5c0004.bmp
원본 그림의 크기: 가로 244pixel, 세로 76pixel, 0 and 그림입니다.
원본 그림의 이름: CLP00001f5c0005.bmp
원본 그림의 크기: 가로 172pixel, 세로 73pixel). Defining 그림입니다.
원본 그림의 이름: CLP00001f5c0006.bmp
원본 그림의 크기: 가로 273pixel, 세로 77pixel, one H-bridge inverter can output five levels (+ 2E, +E, 0, -E and -2E).


B. Operation Mode

Taking phase A as an example, in order to facilitate the presentation, the output voltage levels +2E, +E, 0, -E, -2E are numbered as the switching states ST = 2, 1, 0, -1, -2, respectively. The operation modes corresponding to the switching states are given in Fig. 2. The analysis of the nine working modes is as follows.


그림입니다.
원본 그림의 이름: CLP00001f5c0007.bmp
원본 그림의 크기: 가로 5263pixel, 세로 4502pixel

Fig. 2. Working modes of a 5L-HNPC inverter.


Mode a (ST = 2, uao = +2E): The power devices of S11, S12, S23, S24 are turned ON at the same time. Regardless of whether the output current ia is positive or negative, both of the capacitors C1 and C2 can work. Thus, the capacitor voltages of C1 and C2 are equal.

Mode b (ST = 1, uao = +E): The power devices of S12, S13, S23, S24 are turned ON at the same time. When the output current ia is positive, the capacitor C2 is discharged and the capacitor voltage uC2 decreases, and vice versa. Regardless of whether the output current ia is positive or negative, the capacitor C1 cannot work. Thus, the capacitor voltages of C1 and C2 are not equal.

Mode c (ST = 1, uao = +E): The power devices of S11, S12, S22, S23 are turned ON at the same time. When the output current ia is positive, the capacitor C1 is discharged and the capacitor voltage uC1 drops, and vice versa. Regardless of whether the output current ia is positive or negative, the capacitor C2 cannot work. Thus, the capacitor voltages of C1 and C2 are not equal.

Modes d, e, f (ST = 0, uao = 0): Both of the capacitors C1 and C2 cannot work. The capacitor voltages of C1 and C2 are not influenced by the output current.

Mode g (ST = -1, uao = -E): The power devices of S12, S13, S21, S22 are turned ON at the same time. When the output current ia is positive, the capacitor C1 is discharged and the capacitor voltage uC1 decreases, and vice versa. Regardless of whether the output current ia is positive or negative, the capacitor C2 cannot work. Thus, the capacitor voltages of C1 and C2 are not equal.

Mode h (ST = -1, uao = -E): The power devices of S13, S14, S22, S23 are turned ON at the same time. When the output current ia is positive, the capacitor C2 is discharged and the capacitor voltage uC2 drops, and vice versa. Regardless of whether the output current ia is positive or negative, the capacitor C1 cannot work. Thus, the capacitor voltages of C1 and C2 are not equal.

Mode i (ST = -2, uao = -2E): The power devices of S13, S14, S21, S22 are turned ON at the same time. Regardless of whether the output current ia is positive or negative, both of the capacitors C1 and C2 can work. Thus, the capacitor voltages of C1 and C2 are equal.

To conclude, when ST=그림입니다.
원본 그림의 이름: CLP00001f5c002b.bmp
원본 그림의 크기: 가로 53pixel, 세로 54pixel2, there is only one operation mode. When ST=그림입니다.
원본 그림의 이름: CLP00001f5c002b.bmp
원본 그림의 크기: 가로 53pixel, 세로 54pixel1, there are two different working modes, whose working capacitors are different. To maintain the neutral-point voltage balance, the two different working modes must be reasonably chosen. When ST=0, there are three different working modes, where both C1 and C2 cannot work. Thus, there is no problem in terms of the neutral-point voltage balance. However, for reducing switching loss, the best choice is mode e.

The optimizing transition of the output states for a 5L-HNPC converter is shown in Fig. 3, which describes the transitions of the different modes and different voltage levels. Since each phase can output five levels for a three-phase 5L-HNPC converter, there are 125 kinds of space voltage vectors. A vector diagram of these space voltage vectors is presented in Fig. 4. One basic vector can correspond to a variety of switching combinations, which means that it possess state redundancy. After removing the redundant vectors, there are 61 kinds of basic space vectors.


그림입니다.
원본 그림의 이름: CLP00001f5c0008.bmp
원본 그림의 크기: 가로 3763pixel, 세로 911pixel

Fig. 3. Phase voltage and optimized transition for a 5L-HNPC converter.


그림입니다.
원본 그림의 이름: image9.emf
원본 그림의 크기: 가로 362pixel, 세로 296pixel

Fig. 4. Space vector distribution of a 5L-HNPC converter.



Ⅲ. FAULT-TOLERANT MODE ANALYSIS


A. Fault Tolerant Operation Analysis

There are two methods to realize the fault-tolerant operation of a 5L-HNPC inverter. These methods are adding switching devices and using power devices. The first method is shown in Fig. 5, where the switching devices QS1, QS2 and QS3 can disconnect a faulty phase to realize a fault- tolerant reconfiguration. The relationships among the operation mode, working bridge arm and switching devices are shown in Table I. For example, when a phase-C bridge fault occurs, the postfault inverter structure is presented in Fig. 6.


TABLE I  RELATIONSHIPS AMONG OPERATION MODE, WORKING BRIDGE ARM AND SWITCHING DEVICES

Operation mode

Working bridge arm

 

Switching device states

A

B

C

 

QS1

QS2

QS3

Normal mode

 

I

I

I

Fault-tolerant mode

Phase-A fault

×

 

II

I

I

Phase-B fault

×

 

I

II

I

Phase-C fault

×

 

I

I

II


그림입니다.
원본 그림의 이름: CLP00001f5c0009.bmp
원본 그림의 크기: 가로 5709pixel, 세로 2017pixel

Fig. 5. Fault-tolerant reconfiguration by using an additional device.


그림입니다.
원본 그림의 이름: CLP00001f5c000a.bmp
원본 그림의 크기: 가로 5937pixel, 세로 2297pixel

Fig. 6. Fault-tolerant reconfiguration of phase-A and phase -B through an additional device.


The second method is to realize fault-tolerance by controlling the power devices and ensuring that the fault phase outputs zero level, i.e. ST=0 in Fig. 2, which means the 2-H bridge inverter is working. A detailed analysis is shown in Part B.


B. Fault-Tolerant Analysis

Taking phase-C as an example, the fault-tolerant working mode is analyzed. When the power device of S11 produces an open-fault, the inverter can choose from the working modes e or f in Fig. 7. When the power device of S11 produces a short-circuit fault, the inverter can choose from the working modes d or f in Fig. 7. When the power device of S12 produces an open fault, the inverter can choose the working mode f in Fig. 7. When a short-circuit fault of the power device of S12 occurs, the inverter can choose from the working modes d or e in Fig. 7.


TABLE II  RELATIONSHIP BETWEEN OPERATION MODE AND FAULT STATE

Fault devices

Fault states

Working modes

Power devices with tail 1 (S21,S11)

Open fault

e,f

Short circuit

d,f

Power devices with tail 2 (S22,S12)

Open fault

f

Short circuit

d,e

Power devices with tail 3 (S23,S13)

Open fault

d

Short circuit

e,f

Power devices with tail 2 (S24,S14)

Open fault

d,e

Short circuit

d,f


그림입니다.
원본 그림의 이름: CLP00001f5c000b.bmp
원본 그림의 크기: 가로 5586pixel, 세로 1569pixel

Fig. 7. Fault-tolerant reconfiguration mode.


The operational working modes corresponding to different switch faults are shown in Table II. From Table II, it can be inferred that the fault tolerant operation must satisfy a number of requirements. Both of the power devices with tail 1 and 3 cannot produce an open fault; both of the power devices with tail 2 and 3 cannot generate an open fault; both of the power devices with tail 2 and 4 cannot create an open fault. Otherwise, it cannot realize ST=0. The self-fault-tolerance cannot add hardware, which increases the cost and weight. Therefore, the self-fault-tolerance of a 5L-HNPC inverter is researched in the paper.

For example, an open fault of power device Sc21 emerges, from Table II, the open fault mode can choose from modes e and f. For mode e, its reconfiguration is shown in Fig. 8. It can be seen that the neutral point O is connected to the winding terminal C by controlling the rest of the power devices. The rest of the 2-H bridge NPC structure can output AC voltage with a mutual difference of 60°, which can produce a rotating magnetic field. Therefore, three-phase motor can realize fault-tolerant mode.


그림입니다.
원본 그림의 이름: CLP00001f5c000c.bmp
원본 그림의 크기: 가로 3773pixel, 세로 1903pixel

Fig. 8. Inverter reconfiguration under an open fault of phase-C.


C. Vector Diagram Analysis

When a phase-C H-bridge arm breaks down, the fault tolerant topology is shown in Fig. 8, which can be redrawn as Fig. 9. From Fig. 9, it can be seen that the H-bridge inverter structure of phase-A and phase-B is not altered. However, the phase-C winding is connected with the neutral point O. Thus, the output voltage is changed from the motor phase-voltage under the normal operating mode and to the motor line- voltage under the fault-tolerant operation mode, which satisfies:

그림입니다.
원본 그림의 이름: CLP00001f5c000e.bmp
원본 그림의 크기: 가로 1278pixel, 세로 89pixel   (1)

The motor winding voltages (uac and ubc) have five-level changes. However, the line voltage uab is denoted as:

그림입니다.
원본 그림의 이름: CLP00001f5c000f.bmp
원본 그림의 크기: 가로 1130pixel, 세로 92pixel      (2)

From (2), it can be seen to realize nine levels.


그림입니다.
원본 그림의 이름: CLP00001f5c000d.bmp
원본 그림의 크기: 가로 3336pixel, 세로 2209pixel

Fig. 9. Postfault reconfiguration of phase-A and phase-B.


A vector diagram of three-phase fault-tolerant operation in the g-h coordinate system is shown in Fig. 10, where there are three fault-tolerant methods. These methods are AB fault tolerance, BC fault tolerance and AC fault tolerance. AB fault  tolerance denotes when a fault of the phase-C H-bridge inverter occurs, and the phase-A and phase-B H-bridge inverters drive the motor. BC fault tolerance describes when the phase-A H-bridge inverter breaks down, and the phase-B and phase-C H-bridge inverters drive the motor. AC fault tolerance is when the phase B H-bridge inverter generates fault, and the phase-A and phase-C H-bridge inverters drive the motor. From Fig. 10, it can be seen that valid vector distribution areas with 19 basic space vectors of the three fault-tolerant operation modes are consistent, and located in the three-level working areas. The invalid vectors are located in different five-level working areas with 25 space vectors.


그림입니다.
원본 그림의 이름: image17.emf
원본 그림의 크기: 가로 474pixel, 세로 451pixel

Fig. 10. Space vector distribution of a two-phase fault-tolerance inverter.


The HNPC inverter only works in three-level areas under the fault-tolerant operation mode. The output-voltage amplitude of the postfault inverter is reduced to sixty percent of the normal mode. Thus, the running motor services in a de-rated capacity.



Ⅳ. ANALYSIS OF FAULT-TOLERANT CONTROL WITH FCS-MPVC BASED ON OPTIMIZATION FOR IM DRIVES


A. Prediction Model of the IM

Based on predictive current control and the voltage control principle, discrete-time models of the currents and voltages for induction motors are as follows.

The predictive current model is:

그림입니다.
원본 그림의 이름: CLP00001f5c0010.bmp
원본 그림의 크기: 가로 1155pixel, 세로 359pixel     (3)

where     

그림입니다.
원본 그림의 이름: CLP00001f5c0011.bmp
원본 그림의 크기: 가로 856pixel, 세로 684pixel, 그림입니다.
원본 그림의 이름: CLP00001f5c0012.bmp
원본 그림의 크기: 가로 1079pixel, 세로 343pixel, 그림입니다.
원본 그림의 이름: CLP00001f5c0013.bmp
원본 그림의 크기: 가로 1230pixel, 세로 86pixel, 그림입니다.
원본 그림의 이름: CLP00001f5c0014.bmp
원본 그림의 크기: 가로 294pixel, 세로 76pixel.


The meanings of the variables in matrix A and matrix B can be seen in [27].

The predictive voltage model can be written as:

그림입니다.
원본 그림의 이름: CLP00001f5c0015.bmp
원본 그림의 크기: 가로 997pixel, 세로 545pixel       (4)

To compensate for the control system delay [26], the predictive voltage needs to push forward as follows:

그림입니다.
원본 그림의 이름: CLP00001f5c0016.bmp
원본 그림의 크기: 가로 1329pixel, 세로 573pixel     (5)


B. FCS-MPVC Based on Hierarchical Optimization

In order to avoid the problem of weighting factor tuning and reduce the computational burden of the system in the cost function, a FCS-MPVC based on hierarchical optimization is used in the paper.

To meet the requirement of low switching-frequency loss, there can be at most two vectors switching simultaneously between two-phase adjacent vectors. Based on the control method, the controller can be simplified to two layers of control. The first layer is the voltage jump limit that is realized by directly selecting the neighboring vectors. The second layer is the voltage following control to ensure the current following performance and the uniqueness of the optimal solution through an optimal control strategy.

The vector selection principle to meet the first layer voltage transition limit is analyzed as follows.

Assuming that the optimal switching vector is selected in the last period is denoted as 그림입니다.
원본 그림의 이름: CLP00001f5c0017.bmp
원본 그림의 크기: 가로 299pixel, 세로 71pixel. Then, the possible switching vector in the next period is indicated as 그림입니다.
원본 그림의 이름: CLP00001f5c0018.bmp
원본 그림의 크기: 가로 779pixel, 세로 70pixel.

All of the possible switching vectors are presented as follows.

그림입니다.
원본 그림의 이름: CLP00001f5c0019.bmp
원본 그림의 크기: 가로 868pixel, 세로 634pixel         (6)

And satisfying:

그림입니다.
원본 그림의 이름: CLP00001f5c001a.bmp
원본 그림의 크기: 가로 559pixel, 세로 273pixel           (7)

For the three different fault-tolerant operations, AB fault- tolerant operation, BC fault-tolerant operation and AC fault- tolerant operation, the corresponding switch mapping formulas are as follows:

그림입니다.
원본 그림의 이름: CLP00001f5c001b.bmp
원본 그림의 크기: 가로 979pixel, 세로 164pixel         (8)

그림입니다.
원본 그림의 이름: CLP00001f5c001c.bmp
원본 그림의 크기: 가로 1076pixel, 세로 169pixel      (9)

그림입니다.
원본 그림의 이름: CLP00001f5c001d.bmp
원본 그림의 크기: 가로 1345pixel, 세로 78pixel    (10)

Define the cost function of the current as follows [19]:

그림입니다.
원본 그림의 이름: CLP00001f5c001e.bmp
원본 그림의 크기: 가로 911pixel, 세로 104pixel          (11)

Assuming that the current reference 그림입니다.
원본 그림의 이름: CLP00001f5c0022.bmp
원본 그림의 크기: 가로 80pixel, 세로 90pixel corresponds to the reference voltage prediction 그림입니다.
원본 그림의 이름: CLP00001f5c0023.bmp
원본 그림의 크기: 가로 101pixel, 세로 89pixel in the gh coordinate system, from (3) and (11), the following can be obtained [19]:

그림입니다.
원본 그림의 이름: CLP00001f5c001f.bmp
원본 그림의 크기: 가로 1455pixel, 세로 278pixel     (12)

where 그림입니다.
원본 그림의 이름: CLP00001f5c0021.bmp
원본 그림의 크기: 가로 264pixel, 세로 84pixel denotes the current prediction corresponding to the optimized switching vector 그림입니다.
원본 그림의 이름: CLP00001f5c0020.bmp
원본 그림의 크기: 가로 289pixel, 세로 86pixel.

From (12), the cost function of the voltage following can be described as:

그림입니다.
원본 그림의 이름: CLP00001f5c0024.bmp
원본 그림의 크기: 가로 1453pixel, 세로 163pixel     (13)

From (13), it can be seen that the voltage following is equivalent to the current following.

The reference voltage predictions in the 그림입니다.
원본 그림의 이름: CLP00001f5c0025.bmp
원본 그림의 크기: 가로 81pixel, 세로 69pixel coordinate system can be used to directly obtain the voltage predictions of 그림입니다.
원본 그림의 이름: CLP00001f5c0026.bmp
원본 그림의 크기: 가로 250pixel, 세로 83pixel, 그림입니다.
원본 그림의 이름: CLP00001f5c0027.bmp
원본 그림의 크기: 가로 250pixel, 세로 84pixel through the coordinate transformation. The predictive value of the reference voltage can be directly used in the 그림입니다.
원본 그림의 이름: CLP00001f5c0025.bmp
원본 그림의 크기: 가로 81pixel, 세로 69pixel coordinate system. From (7), (12) and (13), the voltage following optimization performance function can be redefined as:

그림입니다.
원본 그림의 이름: CLP00001f5c0028.bmp
원본 그림의 크기: 가로 1081pixel, 세로 362pixel      (14)

From the above analysis, a flow diagram of the fault tolerant control algorithm with FCS-MPVC is shown in Fig. 11. In the gh coordinate system, the FCS-MPVC strategy avoids a lot of repetitive prediction algorithms, which is reduced to 7 times.


그림입니다.
원본 그림의 이름: CLP00001f5c0029.bmp
원본 그림의 크기: 가로 3551pixel, 세로 4596pixel

Fig. 11. Flow diagram of a fault-tolerant control algorithm with FCS-MPVC.


C. Control Strategy of the Drive System

In order to realize decoupling control of the excitation component and the torque component, and to give full play to the advantages of FCS-MPC, an induction motor control system based on FCS-MPVC is built, as shown in Fig. 12. In the control strategy, the FCS-MPVC single-loop is used to replace the two inner current loops and PWM modulation in the traditional control system to greatly simplify the controller. The design of the outer loop and magnetic chain observer in the system is consistent with the traditional FOC control system. In the control strategy, the key is the design of the FCS-MPVC controller.


그림입니다.
원본 그림의 이름: CLP00001f5c002a.bmp
원본 그림의 크기: 가로 3878pixel, 세로 2009pixel

Fig. 12. Drive system structure diagram.



Ⅴ. SIMULATION AND EXPERIMENTAL RESULTS

When an open fault of the phase-C bridge occurs, the reconfiguration structure is shown in Fig. 8. Table III presents the parameters of the induction motor.


TABLE III  PARAMETERS OF THE INDUCTION MOTOR

Parameters

Value

Parameters

Value

Rated power (kW)

5.5

Stator resistance (Ω)

1.55

Rated voltage (V)

380

Rotor resistance (H)

0.692

Rated current (A)

11.5

Magnetic inductance (H)

0.133

Pole pairs

2

Stator leakage inductance (H)

0.0054

Rated torque (Nm)

35

Rotor leakage inductance (H)

0.0054


Simulation results of the drive system under the fault tolerant mode are presented and analyzed, as shown in Fig. 13 and Fig. 14.


Fig. 13. Simulation results of the motor loading and unloading process under the fault-tolerant mode. (a) Reference speed n*and actual speed nact. (b) Three-phase stator current waveform. (c) Reference excitation current 그림입니다.
원본 그림의 이름: CLP00001f5c0001.bmp
원본 그림의 크기: 가로 45pixel, 세로 68pixel, actual excitation current id, reference torque current 그림입니다.
원본 그림의 이름: CLP00001f5c0002.bmp
원본 그림의 크기: 가로 39pixel, 세로 76pixel and actual torque current iq. (d) Two-phase winding voltage.

그림입니다.
원본 그림의 이름: CLP00001f5c02dd.bmp
원본 그림의 크기: 가로 3690pixel, 세로 1181pixel

(a)

 

그림입니다.
원본 그림의 이름: image50.emf
원본 그림의 크기: 가로 622pixel, 세로 279pixel

(b)

 

그림입니다.
원본 그림의 이름: image51.emf
원본 그림의 크기: 가로 561pixel, 세로 258pixel

(c)

 

그림입니다.
원본 그림의 이름: image52.emf
원본 그림의 크기: 가로 575pixel, 세로 283pixel

(d)


Fig. 14. Simulation results of motor acceleration under the fault- tolerant mode. (a) Waveform of the speed n from 100rpm to 600rpm. (b) Waveform of the torque current iq. (c) Three-phase stator current waveform.

그림입니다.
원본 그림의 이름: image55.emf
원본 그림의 크기: 가로 630pixel, 세로 310pixel

(a)

 

그림입니다.
원본 그림의 이름: image56.emf
원본 그림의 크기: 가로 638pixel, 세로 285pixel

(b)

 

그림입니다.
원본 그림의 이름: image57.emf
원본 그림의 크기: 가로 643pixel, 세로 295pixel

(c)


When the reference speed is 600rpm, the sudden load torque is 30Nm when t=0.3s. The load torque is suddenly reduced to zero when t=0.5s. Simulation results are shown in Fig. 13. Fig. 13(a) presents the speed and its local amplification. From Fig. 13(a), it can be seen that the staring process has almost no overshoot and that the speed fluctuation is small. The three-phase stator current waveform is shown in Fig. 13(b), and it can be seen that the current is sinusoidal. Fig. 13(c) shows the good following performance of the excited current and torque current. The two-phase winding voltage of the fault-tolerant structure is presented in Fig. 13(d). From Fig. 13(d), it can be seen that it operates in the 3-level region and that the two-phase voltages have a mutual difference of 60° in their phase. The simulation results reveal that the fault tolerance of the 5L-HNPC inverter is feasible and that the drive system has good performance.

Fig. 14 shows simulation results of motor acceleration when the load torque is 12Nm. Fig. 14(a) presents the speed from 100rpm to 600rpm. Fig. 14(b) shows a torque current waveform. It can be seen that the torque ripple is small. Fig. 14(c) presents stator currents. It can be seen that the three phase stator currents are spaced 120°apart and are sinusoidal.

A floating-point digital signal processor (DSP, TMS320 F28335) is used to select the optimal switching state and a field programmable gate array (FPGA) is used to generate an impulse to control the switches in the experimental platform built based on Fig. 12. Fig. 15 shows experimental waveforms of the drive system under normal operation from no load to load-on. Fig. 15(a) shows an acceleration waveform of the drive system under normal conditions. In the dynamic process, the load current ia is seen to be sinusoidal, the excitation component id is kept constant, and the rotor speed n is non-overshoot. Steady state waveforms of the winding line-voltage and the winding current are presented in Fig. 15(b). It can be seen that the line-voltage has 9 levels and that the winding current is sinusoidal with low distortions. From Fig. 15, it can be seen that the drive system is feasible under normal operation.


그림입니다.
원본 그림의 이름: image58.emf
원본 그림의 크기: 가로 767pixel, 세로 370pixel

Fig. 15. Experimental waveforms of the drive system under normal operation. (a) Acceleration waveforms of the phase current ia, d-q current and rotor speed. (b) Steady waveforms of the winding line-voltage and current.


When one power device of a phase-C H-inverter breaks down, fault-tolerant operation waveforms of phase A and phase B are shown in Fig. 16. Fig. 16(a) shows a dynamic process waveform of the motor speed from 100rpm to 600rpm. It can be seen that the sinusoidal degree of the winding current and the dynamic response of the rotor speed are better, and that the excitation component id is basically stable. Output voltage waveforms of phase-A and phase-B are shown in Fig. 16(b). The winding voltages have five levels. However, they correspond to the line voltages of phase-AC and phase-BC. The postfault reconfiguration can be equivalent to a three-level inverter. Experimental results indicate that the two-phase fault tolerant drive can work steadily in the three-level region.


그림입니다.
원본 그림의 이름: image59.emf
원본 그림의 크기: 가로 763pixel, 세로 383pixel

Fig. 16. Experimental waveforms of a drive under the fault tolerant mode. (a) Phase current ia, d-q current and rotor speed n under the dynamic process. (b) Winding voltages uac and ubc under the steady state.


From the above statement, it can be seen that the proposed fault-tolerant control with FCS-MPVC based on hierarchical optimization is feasible.



Ⅵ. CONCLUSION

The fault-tolerant operation of a 5L-HNPC inverter is analyzed in detail, and a fault-tolerant control with FCS- MPVC based on hierarchical optimization is proposed. The fault-tolerant reconfiguration structure is realized by controlling the fault-bridge switch itself. The proposed fault-tolerant control strategy can simplify the mathematic calculations and resolve the problem of weighting-factor tuning. The fault tolerant mode cannot change the structure of a 5L-HNPC inverter or effect the dynamic performance of the drive system. The 5L-HNPC inverter can operate in the three-level area under the double bridge fault tolerant mode. Simulation and experimental results verify that the fault- tolerant operation of a 5L-HNPC inverter based on the proposed control strategy is feasible.



ACKNOWLEDGMENT

This work was supported in part by the National Natural Science Foundation of China under Grant 51707085 and Grant 51707086, by the Natural Science Foundation of Jiangsu Province under Grant BK20160219,by the Natural Science Foundation of the Jiangsu Higher Education Instiitutions of China under Grant 17KJB470004, and by the Xuzhou key Research and Development Projects of China under Grant KC18080.



REFERENCES

[1] S. Yang, A. Bryant, P. Mawby, D. Xiang, L. Ran, and P. Tavner, “An industry-based survey of reliability in power electronic converters,” IEEE Trans. Ind. Appl., Vol. 47, No. 3, pp. 1441-1451, May/Jun. 2011.

[2] Dehong Zhou, Yunhua Li, Jin Zhao, Feng Wu, and Hui Luo, “An embedded closed-loop fault-tolerant control scheme for nonredundant VSI-fed induction motor drives,” IEEE Trans. Power Electron., Vol. 32, No. 5, pp. 3731-3740, May 2017.

[3] E. Levi, “Multiphase electric machines for variable-speed applications,” IEEE Trans. Ind. Electron., Vol. 55, No. 5, pp. 1893-1909, May 2008.

[4] X. Huang, A. Googman, C. Gerada, Y. Fang, and Q. Lu, “Design of a five-phase brushless dc motor for a safety critical aerospace application,” IEEE Trans. Ind. Electron., Vol. 59, No. 9, pp. 3532-3541, Sep. 2012.

[5] M. J. Duran, I. G. Prieto, M. Bermudez, F. Barrero, H. Guzman, and M. R. Arahal, “Optimal fault-tolerant control of six- hase induction motor drives with parallel converters,” IEEE Trans. Ind. Electron., Vol. 63, No. 1, pp. 629-640, Jan. 2016.

[6] A. Hosseynia, R. Trabelsib, and M. F. Mimounia, “Fault tolerant control strategy of a five-phase permanent magnet synchronous motor drive,” The 16th International Conference on Sciences and Techniques of Automatic Control & Computer Engineering, pp. 218-222, Dec. 2015.

[7] A. Mohammadpour, S. Sadeghi, and L. Parsa, “A generalized fault-tolerant control strategy for five-phase PM motor drives considering star, pentagon, and pentacle connections of stator windings,” IEEE Trans. Ind. Electron., Vol. 61, No. 1, pp. 63-75, Jan. 2014.

[8] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodŕıguez, M. A. Ƥerez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., Vol. 57, No. 8, pp. 2553-2580, Aug. 2010.

[9] R. P. Aguilera, P. Acũna, P. Lezana, G. Konstantinou, B. Wu, S. Bernet, and V. G. Agelidis, “Selective harmonic elimination model predictive control for multilevel power converters,” IEEE Trans. Power Electron., Vol. 32, No. 3, pp. 2416-2426, Mar. 2017.

[10] G. Tan, Q. Deng, and Z. Liu, “An optimized SVPWM strategy for five-level active NPC (5L-ANPC) converter,” IEEE Trans. Power Electron., Vol. 29, No. 1, pp. 386-395, Jan. 2014.

[11] C. Xue, W. Song, X. Wu, and X. Feng, “A constant switching frequency finite-control-set predictive current control scheme of five-phase inverter with duty ratio optimization,” IEEE Trans. Power Electron., Vol. 33, No. 4, pp. 3583-3594, Apr. 2018.

[12] R. Baidya, R. P. Aguilera, P. Acuna, S. Vazquez, H. du Toit Mouton, “Multistep model predictive control for cascaded H-bridge inverters: formulation and analysis,” IEEE Trans. Power Electron., Vol. 33, No. 1, pp. 876-886, Jan. 2018.

[13] T. D. Nguyen and N. D. Tuong, “Carrier-based PWM strategy for post-fault reconfigured 3-Level NPC inverter under imbalanced DC-link voltages,” IEEE 8th International Power Electronics and Motion Control Conference, pp. 1-6, May 2016.

[14] B. R. O. Baptista, M. B. Abadi, A. M. S. Mendes, and S. M. A. Cruz, “The performance of a three-phase induction motor fed by a three-level NPC converter with fault tolerant control strategies,” IEEE International Symposium on Diagnostics for Electric Machines, Power Electronics and Drives, Valencia, pp. 497-504, Aug. 2013.

[15] F. Sebaaly, H. Vahedi, H. Y. Kanaan, N. Moubayed, and K. Al-Haddad, “Model predictive controller with fixed switching frequency for a 3L-NPC inverter,” IECON - 42nd Annual Conference of the IEEE Industrial Electronics Society, Oct. 2016.

[16] H. Young and J. Rodríguez, “Comparison of finite-control- set model predictive control versus a SVM-based linear controller,” 15th European Conference on Power Electronics and Applications, Sept. 2013.

[17] A. Sanchez-Ruiz, G. Abad, I. Echeverria, I. Torre, and I. Atutxa, “Continuous phase-shifted selective harmonic elimination and dc-link voltage balance solution for H-bridge multilevel configurations, applied to 5L HNPC,” IEEE Trans. Power Electron., Vol. 32, No. 4, pp. 3533- 3545, Apr. 2017.

[18] S. Bayhan, P. Kakosimos, H. Abu-Rub, and J. Rodriguez, “Model predictive control of five-level H-bridge neutral- point-clamped qZS Inverter,” IECON - 42nd Annual Conference of the IEEE Industrial Electronics Society, Oct. 2016.

[19] G. Wang, “Nonlinear FCS-MPC strategy of NPC/H-5L inverter based on satisfactory optimization algorithm,” Chaos, Solitons and Fractals, Vol. 89, pp. 353-362, Jan. 2016.

[20] T. Peng, H. Dan, J. Yang, H. Deng, Q. Zhu, C. Wang, and W. Gui, and J. M. Guerrero, “Open-switch fault diagnosis and fault tolerant for matrix converter with finite control set-model predictive control,” IEEE Trans. Ind. Electron., Vol. 63, No. 9, pp. 5953-5963, Sep. 2016.

[21] K. V. Praveen and K. T. Vinay, “Predictive torque control of open-end winding induction motor drive fed with multilevel inversion using two two-level inverters,” IET Electr. Power Appl., Vol. 12, No. 1, pp. 54-62, Jan. 2018.

[22] R. P. Aguilera, R. Baidya, P. Acuna, S. Vazquez, T. Mouton, and V. G. Agelidis, “Model predictive control of cascaded H-bridge inverters based on a fast-optimization algorithm,” in Proc. IEEE IECON, Yokohama, pp. 4003- 4008, Nov. 2015.

[23] H. A. Young, M. A. Perez, and J. Rodriguez, “Analysis of finite-control-set model predictive current control with model parameter mismatch in a three-phase inverter,” IEEE Trans. Ind. Electron., Vol. 63, No. 5, pp. 3100-3107, May 2016.

[24] A. A. Abdelsalam, B. K. Koh, H. S. Park, K. B. Lee, and Y. I. Lee, “Finite-control set model predictive control method for torque control of induction motors using a state tracking cost index,” IEEE Trans. Ind. Electron., Vol. 64, No. 3, pp. 1916-1928, Mar. 2017.

[25] X. Wang, L. Li, and C. Yang, “Hierarchical control of dry clutch for engine-start process in a parallel hybrid electric vehicle,” IEEE Trans. Transport. Electrific., Vol. 2, No. 2, pp. 231-242, Jun. 2016.

[26] P. Cortes, J. Rodriguez, and C. Silva, “Delay compensation in model predictive current control of a three-phase inverter,” IEEE Trans. Ind. Electron., Vol. 59, No. 2, pp. 1323-1325, Feb. 2012.

[27] T. Weisheng, “The research on high voltage variable frequency variable speed system based on five-level neutral-point-clamped (NPC) H-bridge inverter,” M.S. Thesis, Hunan University, Chinese, 2013.



그림입니다.
원본 그림의 이름: image60.jpeg
원본 그림의 크기: 가로 210pixel, 세로 223pixel

Chunjie Li was born in Liaocheng, Shandong Province, China, in 1985. She received her B.S. and M.S. degrees in Electrical Engineering from the Shandong University of Science and Technology, Qingdao, China, in 2008 and 2011, respectively. She received her Ph.D. degree in Power Electronics and Electrical Drives from the Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2016. In 2016, she joined the faculty of the College of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou, China, where she is presently working as a Lecturer. Her current research interests include power electronics and the control of electrical machine systems.


그림입니다.
원본 그림의 이름: image61.jpeg
원본 그림의 크기: 가로 177pixel, 세로 207pixel

Guifeng Wang was born in Linyi, Shandong Province, China, in 1982. He received his B.S. and M.S. degrees from School of Information and Electrical Engineering at the China University of Mining and Technology, Xuzhou, China, in 2004 and 2007, respectively. He received his Ph.D. degree in Power Electronics and Electrical Drive from Shanghai Jiao Tong University, Shanghai, China. He is presently working as a Senior Engineer in the College of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou, China. His current research interests include power electronic converters for electrical drives and power quality.


그림입니다.
원본 그림의 이름: image62.jpeg
원본 그림의 크기: 가로 90pixel, 세로 106pixel

Fei Li was born in Xuzhou, Jiangsu Province, China, in 1982. He received his B.S. degree from the China University of Mining and Technology, Xuzhou, China, in 2005; his M.S. degree from the University of Duisburg-ssen, Duisburg and Essen, Germany, in 2009; and his Ph.D. degree from the China University of Mining and Technology, in 2017. His current research interests include power electronics converters and power quality.


그림입니다.
원본 그림의 이름: image63.jpeg
원본 그림의 크기: 가로 114pixel, 세로 132pixel

Hongmei Li was born in Yantai, Shandong Province, China, in 1969. She received her B.S. degrees in Electrical Engineering from the Shandong University of Science and Technology, Qingdao, China, in 1995; and her Ph.D. degree in Electrical Engineering from Southeast University, Nanjing, China, in 2015. She is a member of China Electrical Engineering Society. Her current research interests include the stability and control of power systems and new energy.


그림입니다.
원본 그림의 이름: image64.jpeg
원본 그림의 크기: 가로 143pixel, 세로 169pixel

Zhenglong Xia received his B.S. and Ph.D. degrees from the School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China, in 2005 and 2014, respectively. In 2014, he became a Lecturer in the school of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou, China. He has published more than 20 research papers in journals. His current research interests include the reactive compensation of power systems, fault diagnosis, distributed parallel processing and neural networks.


그림입니다.
원본 그림의 이름: image65.jpeg
원본 그림의 크기: 가로 170pixel, 세로 201pixel

Zhan Liu was born in Xiaoxian, Anhui Province, China, in 1989. He received his Ph.D. degree in Electrical Engineering and Automation from the China University of Mining and Technology, Xuzhou, China, in 2016. He is presently working as a Faculty Member in the School of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou, China. His current research interests include power electronics, modern control theory and multilevel converters.