https://doi.org/10.6113/JPE.2018.18.4.965
ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718
Voltage-Fed Push-Pull PWM Converter Featuring Wide ZVS Range and Low Circulating Loss with Simple Auxiliary Circuit
Manyuan Ye†, Pinggang Song*, Song Li*, and Yunhuang Xiao*
†,*School of Electrical and Automation Engineering, East China Jiaotong University, Nanchang, China
Abstract
A new zero-voltage-switching (ZVS) push-pull pulse-width modulation (PWM) converter is proposed in this paper. The wide ZVS condition for all of the switches is obtained by utilizing the energy stored in the output inductor and magnetizing inductance. As a result, the switching losses can be dramatically reduced. A simple auxiliary circuit including two small diodes and one capacitor is added at the secondary side of a high frequency (HF) transformer to reset the primary current during the circulating stage and to clamp the voltage spike across the rectifier diodes, which enables the use of low-voltage and low-cost diodes to reduce the conducting and reverse recovery losses. In addition, there are no active devices or resistors in the auxiliary circuit, which can be realized easily. A detailed steady operation analysis, characteristics, design considerations, experimental results and a loss breakdown are presented for the proposed converter. A 500 W prototype has been constructed to verify the effectiveness of the proposed concept.
Key words: Push-pull, Simple auxiliary circuit, Voltage-fed, Zero-voltage-switching
Manuscript received Oct. 18, 2017; accepted Feb. 6, 2018
Recommended for publication by Associate Editor Chun-An Cheng.
†Corresponding Author: ye_ecjtu@126.com Tel: +86-18170828710, East China Jiaotong University
*School of Electr. and Autom. Eng., East China Jiaotong Univ., China
Ⅰ. INTRODUCTION
In medium-small power and low-input-voltage applications such as battery chargers, uninterruptible power supply (UPS), electric vehicles and distributed renewable energy systems i.e., fuel cells, solar cells and wind turbines, a high voltage step-up dc/dc converter is generally required to serves as an interface between a low-voltage source and a high-voltage bus (200-400V) [1]-[4]. Usually, a push-pull converter is the preferred choice due to its simple circuitry, high-voltage conversion ratio, electric isolation and good transformer utilization. However, conventional push-pull converters, including voltage-fed and current-fed converters, suffer from the drawbacks of hard-switching and high-voltage overshoots across the primary switches and secondary diodes due to the resonance between the leakage inductance of the HF transformer and the junction capacitors during the turn-off transient, which results in high switching losses and large voltage rating components [5]. In particular, when the switching frequency becomes higher, these limitations become more serious. To solve these problems, a number of zero-voltage and zero-current switching (ZVZCS) push-pull converters have been proposed during the past several years [5]-[18], [21], [22]. These topologies can be categorized according to their modulation strategy as either variable frequency modulation (VFM) [6]-[12] or pulse-width modulation (PWM) strategies [5], [13]-[20].
The VFM is mainly adopted in resonant converters to realize the ZVZCS operation of switches and to maintain the regulation of the output voltage. In [6]-[9], LCL, LLC and LC resonant-tanks are added in the secondary of voltage-fed push-pull converters to assist in ZVS or ZCS for the primary switches. In addition, the leakage inductance of the HF transformer and parasitic capacitance of the device can be utilized to achieve soft-switching. However, the resonant current is much higher than the input current, which leads to the need for higher current-stress devices. In addition, the resonant-tank was implemented in current-fed push-pull converters and the ZVZCS was achieved in the same manner as that of the voltage-fed type. The topology in [10] can achieve ZVS turn-on for the primary switches and ZCS turn-off for the rectifier diode. However, the duty cycle has to be fixed at 0.5. In [11], Primary switches operate under ZCS turn-off whereas the rectifier diodes operate under hard turn-off. A simple and cost-effective method of paralleling one capacitor in the secondary winding of the HF transformer has been proposed in [12]. This is done to assist in ZCS turn-off of the primary switches and to clamp the winding voltage-spike. However, it still uses hard switching turn-on.
It should be noted that VFM makes the magnetic design and control strategy more complex and challenging while the PWM converters can eliminate these drawbacks. Therefore, many PWM push-pull converters have been proposed in recent years. PWM current-fed push-pull converters with one or two active-clamp circuits have been presented in [13], [14] to suppress the voltage surge, and to support ZVS turn-on. However, current-fed topologies usually require a larger input inductor, higher voltage rating switch, additional snubbers and an auxiliary soft-start circuit when compared with voltage-fed structures [13], [15], [16]. Therefore, it is not a preferred candidate in some applications. On the other hand, the voltage-fed type does not have these limitations. In view of the aforementioned shortcomings, in [17], [18], two complicated snubbers are paralleled with primary switches to suppress the voltage spike and to recycle the leakage inductance energy. However, the switches still operate under hard-switching. Voltage-fed push-pull converters with active- clamp circuits have been discussed in [19], [20], where all of the switches can realize ZVS turn-on and suppress the voltage spike. However, the ZVS condition is determined by the leakage inductance. Therefore, the switches lose the ZVS condition easily under a certain light load. Another attractive approach has been presented in [21], where only one switch is inserted between the input voltage source and the middle point of the HF transformer in the two primary windings. This structure possesses characteristics similar to those of the phase-shift full bridge topology. All of the switches can realize ZVS operation with the PWM control. However, a narrow ZVS range and a rectifier voltage ringing are two key problems. Therefore, one saturable inductance is implemented to suppress the voltage spike and to widen the ZVS range in [22]. However, this topology still loses ZVS operation until half-load. More importantly, the large circulating primary current increases the conduction loss and reduces the conversion efficiency.
Considering these problems, this paper proposes a new voltage-fed push-pull converter that features and extended ZVS load range, lower circulating losses and a lower voltage spike. The primary switches can achieve ZVS operation over a wide load range by the energy stored in the magnetizing inductance and output filter. A simple auxiliary circuit including two diodes and one capacitor in the secondary can reset the primary current to ILm/2 (ILm is the maximum value of the magnetizing current) during the circulation stage. It can also assist in clamping the rectifier diodes voltage. The operation, characteristics, design considerations, a performance comparison and a loss breakdown are illustrated. A 500 W 100 kHz prototype has been implemented and tested to verify the proposed concept.
This paper is organized as follows. Section II shows a diagram of the proposed converter and its steady-state operation. In Section III, the key characteristics and design considerations are discussed. Experimental results are presented in Section IV. Section V gives some conclusions.
Ⅱ. CIRCUIT DESCRIPTION AND STEADY-STATE OPERATION
Fig. 1 shows the circuit configuration of the proposed voltage-fed push-pull converter, where Tr is the HF transformer with a turns ratio of 1:1: n, which consists of the leakage inductances Llk1, Llk2 and Llks and the magnetizing inductances Lm1 and Lm2. The input source Vin is linked to two primary windings through the switches S1, S2 and S3. The secondary side circuit is made up of a full bridge rectifier; a simple auxiliary circuit consisting of one clamping capacitor Cb and two diodes Db1 and Db2; an LC filter and a load. Note that three switches are driven by the gate signals adopted in [22]. In addition, dead time is inserted between the gate signals to achieve ZVS operation.
Fig. 1. Circuit configuration of the proposed converter.
Before analyzing the steady-state operation of the proposed converter, some assumptions are made to simplify the explanation.
1) The switches S1~S3 are ideal MOSFETs with antiparallel body diodes D1~D3 and capacitors C1~C3, and the diodes D4~D7 are ideal devices.
2) The capacitance of Cf is large enough. Therefore, the voltage across it can be seen as a constant during the switching process.
3) C1=C2=C3, Llk1=Llk2=Llks/n2=Llk and Lm1=Lm2=Lm.
Based on the above assumptions, Fig. 2 illustrates typical steady-state waveforms of the proposed converter. During one complete switching period of S3, the operation principle can be divided nine intervals. The corresponding equivalent circuits of all the different intervals are shown in Fig. 3.
Fig. 2. Typical steady-state waveforms of the proposed converter.
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Interval 1 [t0≤t<t1, Fig. 3(a)]: S1 and S3 are conducting and the secondary current is reaches Io. At the same time, the voltage vAB increases to Vo. The diode Db1 starts turn-on and the clamping capacitor Cb is charged through Db1 and Cf via the resonance between Llks and Cb. Then, vAB continues increasing from Vo, and vCb begin rising from 0. The primary currents i1 and i3 rise along with an increase of the current is and the magnetizing current iLm1. In addition, the magnetizing current can be viewed as rising linearly. Equations during this process can be obtained by solving the equivalent circuit in Fig. 3(a). In addition, the voltage across Cb, i.e. vCb, the current through Cb i.e. iC, the primary switches currents i1~i3 and the magnetizing current iLm1 can expressed as:
where ωr0 and Zr0 represent the resonant angular frequency and the resonant impedance, which are given by:
In this interval, the power is transferred from the input source to the output. At t=t1, the current through Cb reaches 0, vCb goes up to its peak value 2(nVin-Vo), and this stage ends.
Interval 2 [t1≤t<t2, Fig. 3(b)]: At t1, Db1 is turned off and the voltage vAB is returned to nVin. In addition, vCb maintains its peak value until the next interval. Power is still transferred from the input to the load during this interval.
Interval 3 [t2≤t<t3, Fig. 3(c)]: At t2, S3 is turned off (ZVS due to C3) and the current through the primary starts charging the antiparallel capacitor C3 of S3 and discharging that of S2. To maintain the HF transformer flux-balance, the voltage across S3 and S2 can be considered as linearly charged and discharged because both the filter inductor and the magnetizing inductance are large enough. They are given by:
where vds3 and vds2 are the voltages across the switches S3 and S2, respectively.
During this interval, the primary winding voltage and the secondary rectifier voltage are also declined in accordance with the variations of vds3 and vds2. In addition, the decreasing of i3 leads to the reverse increasing of i2 to remain nIo+ILm constant.
Interval 4 [t3≤t<t4, Fig. 3(d)]: When the rectifier voltage vAB decreases to the value of VCb, the diode Db2 begins conducting and the capacitor Cb holds the rectifier voltage vAB. This implies that the rectifier voltage falls down much slower than the primary winding voltage. The difference voltage vs-vAB is applied to the secondary leakage inductance Llks, and the secondary current is starts going down from Io. Accordingly, the variation of the voltage vCb, vs and the secondary current is can be derived as:
where ωr1 and Ceq represent the resonant angular frequency and the equivalent capacitance in this stage, and are calculated as:
At t4, the primary winding voltage reaches 0. At the same time, the voltage across S2 also decreases to 0 and D2 conducts providing ZVS turn-on for S2. The secondary current is and the rectifier voltage vAB reach is(t4) and vCb(t4), and this interval ends.
Interval 5 [t4≤t<t5, Fig. 3(e)]: After t4, D2 and S1 are conducting and the winding voltage is maintained at 0. Therefore, vCb is applied to the leakage inductance Llks, and the secondary current falls down very fast. The secondary current is and the voltage vCb can be calculated as:
During this stage, note that the currents i1 and i2 fall down along with the decreasing of the current is. When i1 goes down to ILm, the magnetizing current is provided by two windings commonly. Later on, iLm1 descends from ILm to ILm/2, and iLm2 ascends from zero to -ILm/2. This interval finishes when is reaches zero.
Interval 6 [t5≤t<t6, Fig. 3(f)]: At t5, the secondary current is is 0 and the primary current resets to the magnetizing current. This implies that there remains a small magnetizing current during the next circulating interval. Then the energy stored in Cb supplies the load, and the voltage vCb drops quickly. This can be expressed by:
Interval 7 [t6≤t<t7, Fig. 3(g)]: This interval begins when Cb discharges completely. All of the rectifier diodes start to turn on and the load current commutates through the rectifier. In addition, the primary operates at the circulating stage with the half magnetizing current ILm/2.
Interval 8 [t7≤t<t8, Fig. 3(h)]: At t7, S1 is turned off (ZVS due to C1), and the turn-off current is ILm/2. The turn-off loss is small since only ILm/2 remains through the devices. Then ILm/2 starts discharging and charging C3 and C1, respectively. This means the voltage across S3 falls from Vin, and the voltage across S1 increases form 0. If the energy stored magnetizing inductance is large enough, vds3 decreases to 0 quickly providing the ZVS turn-on condition for S3.
During this interval, the secondary sate is the same as that of interval 7, and the energy stored in Lf and Cf offers the load current.
Interval 9 [t8≤t<t9, Fig. 3(i)]: At t8, S3 is turned on with ZVS. Then Vin is applied to the leakage inductance Llk2. The current i2 increases quickly and when it is larger than ILm, the secondary current is starts flowing through the secondary winding reversely. The diodes D4~D7 conduct commonly to deliver power until is increases to Io. Subsequently, the next cycle starts.
Ⅲ. CHARACTERISTICS AND DESIGN CONSIDERATIONS
A. Steady State Analysis
From the aforementioned description, the steady state features of the proposed converter can be derived in this section. Fig. 4 shows simplified operating waveforms in the secondary. The steady-state dc voltage gain of the converter by the flux balance of the filter inductor during the whole switching period can be derived as:
where D is the duty ratio of S3, and d1 and d2 represents two delay stages.
Fig. 4. Simplified waveforms in the secondary.
Delay stage d1: By the analysis in interval 9, the duration time of this process is such that the input voltage is applied to the leakage inductance and the secondary current is increases to Io. Therefore, it can be expressed by:
Delay stage d2: In this interval, the secondary voltage vAB decreases to zero due to the discharging process of Cb. Thus, d2 can be approximately obtained by:
By (16)-(18), the steady-state voltage gain can be further obtained. Taking the following prototype as an example, Fig. 5 shows a comparison of the voltage gain between the proposed converter and the topology presented in [22] under the same specifications. Obviously, it has a higher voltage gain than the concept in [22].
Fig. 5. Comparison of the steady state voltage gain with that of the topology in [22].
B. Soft-Switching for Devices
For S1 (S2): According to the description of intervals 3 and 4, the switches S1 (S2) realize ZVS turn-on by utilizing the energy stored in the output inductor Lf and the magnetizing inductance to discharge C1 (C2) and charge C3. Therefore, from the energy perspective, the ZVS condition of S1 (S2) can be expressed by:
The required dead time td1 can be obtained by:
For S3: From the explanation of interval 8, the ZVS operation of S3 is only determined by the charging and discharging energy from the magnetizing inductance. This expression is approximately given by:
In addition, the needed dead time td2 is:
From (19)-(22), it can be seen that the ZVS operation for S3 is more difficult than that for S1 (S2). It can also be seen that it is only decided by the maximum magnetizing current, which is determined by the input voltage and the conduction time of S3. The maximum magnetizing current ILm can be approximately derived as:
Combing (16)-(18), (21) and (23), the magnetizing inductance for achieving the ZVS operation of S1~S3 under different values of Vin and load currents Io can be determined. Here, by setting the specifications of the following prototype to Vin=45~56 V, Vo=200 V, turns ratio n=6, switching frequency fs=100 kHz, etc., the relationship among them is plotted as Fig. 6. Note that all of the switches can achieve ZVS turn-on if the converter works under the curve region. This curve is used to determine that the harshest ZVS operation conditions are with Vin=56V for the following prototype since the duty cycle D is small. This results in a smaller magnetizing current, which further reduces the energy charging and discharging capacitors C1~C3. From Fig. 6, Lm=25.2 μH can be designed to realize ZVS for all of the switches at more than a 20% load when the input voltage is 56 V.
Fig. 6. Plots of the relationships among Lm, Vin and Io.
For D4~D7: The diodes D4~D7 can be turned off naturally since the secondary current is decreases to zero before the circulating stage, where the secondary winding voltage is zero. Therefore, the reverse-recovery problem of the rectifier diodes can be eliminated in this converter.
C. Voltage and Current Stress of the Power Devices
Since the clamping capacitor Cb and the diode Db1 provide a clamping path to the filter capacitor Cf in this converter, the voltage spikes in the topologies of [19]-[22] caused by parasitic ringing between the leakage inductance and diode junction capacitors are released. The voltage stress of the rectifier diodes D4~D7 can be clamped to:
Formula (24) illustrates that the voltage stresses on the rectifier diodes are inversely proportional to the duty cycle. Thus, the lower voltage stress of the rectifier diode can be maintained as pushing up the duty cycle Deff., and this value is the minimal achievable voltage with Deff=1. In practice, the duty cycle can be selected as high as possible such as 0.8~0.9.
The average current through D4~D7 can be calculated by:
where Po represents the rated output power.
The voltage stresses across Db1 and Db2 are equal to Vo, and average current through them can be calculated by:
Similarly, the voltage stresses across S1 and S2 are 2Vin, and the stress across S3 is Vin. The average current through them can be expressed by:
where η and Po represent the conversion efficiency and output rated power.
D. Selection of the Clamping Capacitor Cb
To ensure that both the primary current and the secondary current are reset during the conduction intervals 4 and 5, the discharge time of the energy stored in the clamping capacitor Cb should be larger than that of the energy stored in the secondary leakage inductance Llks. Thus, the clamping capacitor Cb can be designed as:
E. Reduced Circulating Loss
Simplified primary and secondary waveforms of the proposed converter are compared to those of the topologies in [21], [22] in Fig. 7, where is and i1 are the currents though the secondary winding and the switch S1 in the proposed converter, and is_p and i1_p represent those in [21]-[22]. It can be seen that only a small magnetizing current flows through the primary side and that the secondary current is remains zero during the circulating interval. Therefore, the conduction loss during this stage can be minimized, which results in a higher efficiency when compared with the previous ones.
Fig. 7. Comparison of circulating currents with those of a similar converter.
F. Performance Comparison
The proposed converter is an improved version of the converters presented in [21], [22]. However, their performances and working principles are quite different. The proposed converter can realize a higher voltage gain and ZVS operation for all of the switches in a wider load range. The rectifier voltage ringing can be eliminated and more conduction loss during the circulating stage can be reduced through the secondary simple auxiliary circuit. More importantly, there are no active devices or resistors in the auxiliary circuit, which can be realized easily.
Ⅳ. EXPERIMENTAL RESULTS
A 500 W prototype has been built and tested in the laboratory to verify the analysis and performance of the proposed converter. The prototype is controlled by a DSP TMS320F2812 digital signal processor. The detailed specifications are listed in Table I.
| Names |
Parameters |
| Input voltage |
45~56V DC |
| Output voltage |
200 V DC |
| Switching frequency |
100 kHz |
| Output rated power |
500 W |
| Switches: S1~S3 |
IRFP260N. (External shunt capacitance: 1nF) |
| HF Transformer |
EE55/ PC40; Turn ratio: NP1:NP2:Ns =5:5:30 |
| Secondary diodes: D4~D7 |
MUR860 |
| Clamping diodes: Db1,Db2 |
MUR840 |
| Clamping capacitor Cb |
27 nF film capacitor |
| Output inductor Lf |
500 μH |
| Output capacitance Co |
470*2 μF |
From equations (16)-(18) and Fig. 5, taking the required dead time and the delay characteristics into account, the maximum duty cycle can be selected as 0.8 to keep enough voltage gain. The voltage stress on the rectifier diode can be calculated as 324V by (24). According to Fig. 6, the magnetizing inductance can be designed as 25 μH under the specified input voltage to ensure the realization of ZVS turn-on for all of the switches at more than a 20% load. The leakage inductance of the HF transformer Llks has been measured at about 2.6 μH. In addition, by (28), the clamping capacitor can be shown to be larger than 14 nF. In the prototype, Cb was selected as 27 nF.
Experimental results of the prototype under different input voltage and load conditions are shown in Fig. 8 and Fig. 9, respectively. Fig. 8 shows typical waveforms for Vin=45 V at a full load, and Fig. 9 shows them for Vin=56V at a 20% load (100W). It can be seen that the experimental waveforms match closely with those shown in Fig. 2. In addition, the currents in Fig. 8 and Fig. 9 have some distortion since the resonant power loop includes the winding resistance, parasitic capacitance of the transformer and filter, and forward voltage drops of the switch and diode, which can lead to additional power loss.
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Fig. 8(a) and Fig. 9(a) illustrate the gate-source voltage vgs1, drain-source voltage vds1 and switch current i3 waveforms of S1 at a full load and a 20% load, respectively. It can be seen that the current through S1 goes to the negative before conducting, which means that the ZVS turn-on for S1 can be realized easily under two conditions. In addition, it can be seen that the circulating currents decreases to about 3.5 A and 2.2 A, which are much smaller than half the maximum primary current. This implies that the conduction loss can be reduced dramatically during the circulating stage when compared to existing topologies.
Fig. 8(b) and Fig. 9(b) show voltage and current waveforms of the switch S3, which presents the ZVS realization of S3 at either a full load or a 20% load. However, note that there still exists a voltage ringing across S3. The reason is that when S3 is off, the higher leakage inductance energy resulting from the primary peak current transfers to the output capacitor of S3. In addition, other factors such as the stray inductances resulting from wiring connections, parasitic capacitors of the high frequency transformer and measurements produce some ringing.
Fig. 8(c)-(d) and Fig. 9(c)-(d) present secondary voltage and current waveforms. It can be seen that, by the simple auxiliary circuit, the transient overvoltage can be clamped to about 330 V and 470 V, which nearly match the designed values in (24). The clamping capacitor voltage is applied to the secondary leakage inductor in interval 5, which forces a decline of the diode current to 0 before the circulating stage, which is no voltage across the secondary diode. Hence, the diode can achieve a natural turn-off. These performances enable the use of low-voltage and low-cost diodes to reduce the conducting loss and reverse recovery loss.
Fig. 8(e) and Fig. 9(e) show the input and output voltage and current waveforms under two load conditions.
For comparison, the measured waveforms of D4 with Vin=45V at a full load from the converter in [21], [22] without a clamping circuit are presented in Fig. 10. Apparently, a much higher voltage spike, i.e., 700V occurs during the turn off process. In addition, it can be observed that the diode has a serious reverse recovery problem. However, it can be seen from Fig. 8 and 9(d) that this issue can be effectively resolved.
Fig. 10. Waveforms of vgs3, vD4 and iD4 without a clamping circuit at a full load.
An efficiency comparison, with different output powers at Vin=45V, between the calculated and measured results for the proposed prototype and the basic converter in [21], [22] is shown in Fig. 11. The loss calculation models presented in [8], [23] and [24] are adopted here to assess the power loss of the proposed converter at different output powers. From Fig. 11, it can be seen that they have similar values for calculated and measured efficiencies. The measured peak efficiency can reach or exceed 93.02% for the prototype. However, only 92.38% can be obtained from the basic converter. Overall, the proposed converter has a higher efficiency than the basic one over a wide load range. This is due to a lower circulating-loss, wider ZVS operation and lower rectifier stress.
Fig. 11. Efficiency comparison between the calculated and measured results for the proposed prototype and the basic converter in [21], [22].
Fig. 12 shows loss distribution assessments at a 20% load and the rated load. It is easy to see that the remarkable 42.75% loss in the rated load is the conduction loss of S1~S3, which results in a high on-resistance RDS(on) of 40 mΩ. This implies that the efficiency can be further improved by using lower on-resistance switches. In addition, the added clamping circuit loss occupies a small portion of the losses. However, it has a key function for reductions of the rectifier diode voltage stress and primary circulating current.
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Ⅴ. CONCLUSIONS
This paper proposes a new wide ZVS load range PWM voltage-fed push-pull converter. The steady-state operation, the characteristics and a performance comparison with similar converter have been presented. Experimental results from a 500 W prototype were obtained to verify the effectiveness of the proposed converter. The distinctive features of the proposed converter are summarized as follows.
1) All of the switches can realize ZVS turn-on over a wide load range with PWM control.
2) A higher voltage gain is obtained in comparison with similar converters.
3) The voltage stresses of the rectifier diodes can be suppressed and clamped by using a simple auxiliary circuit, which does not include any active devices or resistors.
4) The primary current can be reset by the secondary circuit during the circulating interval, and lower circulating current results in lower conduction loss and higher efficiency.
ACKNOWLEDGMENT
The authors gratefully acknowledge the National Natural Science Foundation of China (Grant NO.51767007) for its financial support.
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Manyuan Ye received his B.S. degree in Industrial Automation from the Anhui University of Science and Technology, Huainan, China, in 2001; and his M.S. degree in Traffic Control and Information Engineering from the East China Jiaotong University (ECJTU), Nanchang, China, in 2004, were he is presently working towards his Ph.D. degree. He is presently working as an Associate Professor in the School of Electrical and Automation Engineering, ECJTU. His current research interests include power electronics and electric drives, modular multilevel converters, pulse width modulation, and selective harmonic elimination techniques.
Pinggang Song received his M.S. degree in Railway Traction Electrification and Automation, and his Ph.D. degree in Power Electronics and Electric Drives from Southwest Jiaotong University, Chengdu, China, in 1991 and 2007, respectively. He is presently working as a Professor and as the Director of the National Characteristic Specialty of Electrical Engineering, School of Electrical and Automation Engineering, East China Jiaotong University, Nanchang, China. His current research interests include power electronics, electric drives and renewable energy systems
Song Li received her M.S. degree in Traffic Control and Information Engineering from the East China Jiaotong University (ECJTU), Nanchang, China, in 2005. She is presently working as an Associate Professor in the School of Electrical and Automation Engineering, East China Jiaotong University. Her current research interests include power electronics.
Yunhuang Xiao received his B.S. degree in Software Engineering and Electrical Engineering from the East China Jiaotong University (ECJTU), Nanchang, China, in 2013, where he is presently working toward his M.S. degree. His current research interests include power electronics and electric drives.