https://doi.org/10.6113/JPE.2018.18.4.1051

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Step-up Switched Capacitor Multilevel Inverter with a Cascaded Structure in Asymmetric DC Source Configuration

Tapas Roy^†, Bidrohi Bhattacharjee^*, Pradip Kumar Sadhu^*, Abhijit Dasgupta^**, and Srikanta Mohapatra^**

^†,*Department of Electrical Engineering, Indian Institute of Technology (ISM), Dhanbad, India

^**School of Electrical Engineering, KIIT University, Bhubaneswar, India

Abstract

This study presents a novel step-up switched capacitor multilevel inverter (SCMLI) structure. The proposed structure comprises 2 unequal DC voltage sources, 4 capacitors, and 14 unidirectional power switches. It can synthesize 21 output voltage levels. The important features of the proposed topology are its self-voltage boosting and inherent capacitor voltage balancing capabilities. Furthermore, a cascaded structure of the proposed SCMLI with an asymmetric DC voltage source configuration is presented. The proposed topology and its cascaded structure are compared with conventional and other recently developed topologies in terms of different aspects, such as the required components to produce a specific number of output voltage levels, the total standing voltage (TSV) and peak inverse voltage of the structure, and the maximum number of switches in the conducting path. Furthermore, a cost function is developed to verify the cost-effectiveness of the proposed topology with respect to other topologies. The TSV of the proposed topology is significantly lower than those of other topologies. Moreover, the developed topology is cost-effective compared with other topologies. A detailed operating principle, power loss analysis, and selection procedure for switched capacitors are presented for the proposed SCMLI structure. Extensive simulation and experimental studies of a 21-level inverter structure prove the effectiveness and merits of the proposed SCMLI.

Key words: Asymmetric, Boosting, Multilevel, Switched capacitor, Voltage balancing

Manuscript received Oct. 3, 2017; accepted Mar. 13, 2018

Recommended for publication by Associate Editor Yun Zhang.

^†Corresponding Author: tapas18roy@gmail.com Tel: +917749995249, Indian Institute of Technology (ISM)

*Dept. of Electrical Eng., Indian Institute of Technology (ISM), India

**School of Electrical Engineering, KIIT University, India

Ⅰ. INTRODUCTION

At present, multilevel inverters (MLIs) have become viable DC-to-AC power conversion systems for different applications, such as motor drives, renewable energy conversion systems, electric vehicles, active filters, and uninterruptible power supply (UPS) systems [1]-[5]. Compared with classic two- level inverters, MLIs exhibit numerous advantages, such as the generation of output voltage waveforms with better quality, lower electromagnetic interferences, higher power handling capability, higher efficiency, and lower voltage stress on switches [4]. MLIs consist of power electronic switches, diodes, capacitors, and DC voltage sources, which are arranged in a manner that enables them to synthesize a stepped voltage waveform at their output terminals. In general, three conventional MLI topologies exist, namely, diode-clamped (D-C), flying capacitor (FC), and cascaded H-bridge (CHB). Although these conventional topologies exhibit many advantages compared with classic two-level inverters, they become extremely bulky, costly, and complex as output voltage level increases. Another major limitation of conventional MLI topologies is that they require auxiliary circuits or complex algorithms to balance capacitor voltages; these circuits or algorithms increase the size, cost, and complexity of the entire conversion system [5], [6].

The topological improvement of MLIs is an interesting and popular research field to achieve efficient, cost-effective, and compact energy conversion systems. Several innovative MLI topologies, known as “reduced device count (RDC),” have been reported in recent years [7]-[15]. The main objective of these topologies is to generate a high number of output voltage levels using fewer devices, such as switches, gate drivers, diodes, capacitors, and power supplies. Important “RDC–MLI” topologies include the cascaded half-bridge- based multilevel DC link (MLDCL) inverter [7], the T-type inverter [8], switched series/parallel source (SSPS) MLI [9], packed U-cell (PUC) [10], and series-connected switched sources [11]. The authors of [12] proposed a new cascaded multilevel converter topology in which the number of DC voltage sources is reduced. A new MLI structure with a high number of steps associated with a low number of power switches was recommended in [13]. A new cascaded MLI based on a novel H-bridge circuit was proposed in [14]. The authors of [14] also presented nine algorithms for determining the magnitude of DC voltage sources. A new switched capacitor (SC)–diode structure was developed in [15]. This topology requires a large number of capacitors and diodes to produce high voltage levels. The major disadvantage of “RDC–MLIs” is that they do not exhibit self-voltage boosting capability, which is desirable for inverter systems in certain applications, such as renewable energy conversion systems.

Another interesting research field is mitigating the capacitor voltage unbalancing problem associated with conventional MLI topologies. To overcome this issue, auxiliary circuits and complex control strategies have been introduced in the literature. The authors of [16] presented a novel chopper circuit topology for capacitor voltage balancing in D-C MLIs (D-CMLIs). In this chopper circuit, one switch is turned on during each operating interval. A resonant SC converter was proposed in [17] to balance capacitor voltages in D-CMLIs. A number of algorithms were developed based on redundant switching states (RSS) to balance capacitor voltages in [18], [19]. Although these topologies mitigate the capacitor voltage unbalancing problem, the solution methodologies increase system size, cost, and complexity without providing other advantages, such as self-voltage boosting capability, to a structure.

To achieve self-voltage boosting capability and mitigate the capacitor voltage unbalancing problem without using auxiliary circuits or developing complex algorithms, the SC multilevel inverter (SCMLI) is introduced. In SCMLI, capacitors function as alternative DC sources. SCMLI can generate multilevel output voltage using a reduced number of power supplies and switching devices. In addition, SCMLI can boost the input voltage to the desired output voltage by switching the capacitors in charging and discharging modes. Another major advantage of SCMLI is achieving capacitor voltage balancing by using a simple switching strategy.

The concept of SCMLI was proposed by Mak and Ioinovici in 1998 [20]. In their study, an SC unit that consists of two power switches, one capacitor, and two diodes was used to generate DC multilevel voltage. Two of these SC units were fed to a developed H-bridge circuit to generate AC multilevel output voltage. The topology proposed in [20] requires a large number of components and complex control of capacitor voltages. A number of innovative SCMLI structures have been reported in recent years [21]-[25]. In [21], the authors presented a novel SCMLI structure that can produce different output voltage levels and maintain capacitor voltages at desired values by switching capacitors in series/parallel mode with respect to the input source. However, the required number of power switches and capacitors increases significantly as the output voltage level is enhanced. To reduce the required number of components, the authors of [22] presented a basic SC unit that consists of two power switches, one diode, and one capacitor. They proposed two SCMLI structures based on this basic unit. The structures were then analyzed for symmetric and asymmetric DC source configurations. However, the presented structures require H-bridge circuits that enhance the total standing voltage (TSV) of the inverters. The authors of [23] presented an SCMLI structure for high-frequency applications based on the same basic unit presented in [22]. A novel step-up 19- level inverter structure was proposed in [24]. This structure consists of an SC unit and a floating capacitor-based unit. The TSV and peak inverse voltage (PIV) of the presented structure are high for a specific output voltage level. A new SC DC–DC converter structure was presented in [25]. Furthermore, the authors developed a novel cascaded MLI structure based on the proposed DC–DC converter structure. However, the TSV and PIV of the proposed inverter increase significantly as the output voltage level increases.

One of the major drawbacks of SCMLI is the high stress voltage on the switches and diodes. Consequently, the TSV and PIV of a structure are extremely high. The cost of an inverter is proportional to its TSV and PIV. Thus, high TSV and PIV are undesirable qualities for a cost-effective inverter structure. To reduce the TSV and PIV of an SCMLI structure and to produce output voltage levels with an optimum number of components, a novel SCMLI structure is proposed in the current study. The presented topology is analyzed for asymmetric DC sources. Furthermore, a cascaded structure of the proposed SCMLI is developed and an algorithm for asymmetric DC voltage sources is presented. For a fair comparison with other topologies, a cost function (CF) is provided. The CF includes all the parameters, such as number of sources, required switches, power diodes, drivers, capacitors, and per unit TSV and PIV. This CF parameter verifies the cost-effectiveness of the proposed topology. Furthermore, this topology possesses all the qualities of an SCMLI, such as self-voltage boosting capability, simultaneous charging and discharging of switched capacitors, and capacitor voltage balancing. In addition, the proposed topology does not require any power diode.

The rest of this paper is organized as follows. The proposed 21-level SCMLI structure and its detailed operating principle are presented in Section II. The cascaded structure of the proposed SCMLI is explained in Section III. Section IV describes the switched  capacitor  selection procedure. The power loss analysis of the proposed 21-level SCMLI is provided in Section V. An extensive  comparison  is conducted in Section VI. The simulation and experimental results of the 21-level proposed inverter are discussed in Section VII.

Ⅱ. PROPOSED 21-LEVEL SCMLI

Fig. 1 shows the proposed SCMLI structure. The structure contains 2 unequal DC power supplies (V_i and 4V_i), 14 unidirectional power switches (S_i1, S_i1', S_i2, S_i2', S_i3, S_i3', S_i4, S_i4', S_i5, S_i5', S_i6, S_i6', S_i7, and S_i7’), and 4 capacitors (C_i1, C_i1’, C_i2, and C_i2'). This structure can generate 21 voltage levels (10 positive voltage levels, 10 negative voltage levels, and 1 zero level) across load terminals x_i and y_i. In this topology, capacitors C_i1 and C_i1' are charged to V_i, whereas capacitors C_i2 and C_i2' are charged to 4V_i with appropriate switching arrangements as shown in Fig. 2. In the figure, the charging current path is presented by a blue line, whereas the load current path is presented by a red line. The charging currents for capacitors C_i1 and C_i1’ are assumed the same and represented by i_C1, whereas the charging currents for C_i2 and C_i2' are assumed the same and indicated by i_C2. As shown in Fig. 2(a), capacitor C_i1 is connected in parallel to V_i and is charged to V_i when switches S_i2' and S_i3 are in the ON position. Concurrently, capacitor C_i1' is connected in series to V_i through S_i2' and is in the discharging mode for positive load current i_L+. Similarly, capacitor C_i1' is in charging mode while capacitor C_i1 is in discharging mode for a negative load current i_L− when switches S_i2 and S_i3' are kept in the ON position, as shown in Fig. 2(b). Fig. 2(c) presents the current flow paths when switches S_i5 and S_i6' are in the ON position and capacitor C_i2 is in charging mode while capacitor C_i2' is in discharging mode for a negative load current i_L−. Under such circuit condition, capacitor C_i2 is charged to 4V_i . Similarly, capacitor C_i2' is charged to 4V_i and capacitor C_i2 is in discharging mode for a positive load current i_L+ when S_i5' and S_i6 are in the ON position, as shown in Fig. 2(d). This discussion indicates that the proposed topology can simultaneously charge and discharge the capacitors, which is beneficial for maintaining capacitor voltages at desired voltage levels with minimum voltage ripple.

Fig. 1. Proposed 21-level SCMLI.

Fig. 2. Equivalent circuit and current flow paths when: (a) C_i1 and C_i1', (b) C_i1' and C_i1, (c) C_i2 and C_i2', (d) C_i2' and C_i2 are in charging and discharging states.

(a)	(b)
(c)	(d)

Table I presents the ON switches and the capacitor states of the proposed SCMLI for generating different output voltage levels. For simplicity, the load current is considered positive (i_L+) for a positive half cycle and negative (i_L−) for a negative half cycle. In this table, C and D represent the charging and discharging modes of the capacitors. Furthermore, the disconnected state of the capacitors is indicated by . The generation of zero, , , , , and are explained in detail; and the equivalent circuits and current flow paths of these voltage levels are shown in Fig. 3.

TABLE I SWITCH AND CAPACITOR STATES FOR THE PROPOSED 21-LEVEL SCMLI

Voltage level number		ON switches					Load current polarity
1
2
3
4
5
6
7
8
9
10
11	0
12
13
14
15
16
17
18
19
20
21

Fig. 3. Equivalent circuits and different current flow paths of the proposed 21-level SCMLI. (a) Zero voltage level. (b) Zero voltage level. (c) +V_i voltage level. (d) −V_i voltage level. (e) +2V_i voltage level. (f) −2V_i voltage level. (g) +3V_i voltage level. (h) −3V_i voltage level. (i) +8V_i voltage level. (j) −8V_i voltage level. (k) +10V_i voltage level. (l) −10V_i voltage level.

(a)	(b)
(c)	(d)
(e)	(f)
(g)	(h)
(i)	(j)
(k)	(l)

A. Generation of Zero Voltage Level

Zero output voltage level is produced by two switching states, as indicated in Table I. In one switching state, when switches S_i1, S_i3, S_i5', and S_i7' are in the ON position, zero voltage is produced across the load terminals. Then, C_i1 and C_i2' can be maintained in charging mode by turning ON switches S_i2 and S_i6', respectively, as shown in Fig. 3(a). Furthermore, capacitors C_i1' and C_i2 are in disconnected mode under this circuit condition. In the other switching state, when switches S_i1', S_i3', S_i5, and S_i7 are in the ON position, zero output voltage appears across the load terminals. Under this circuit condition, capacitors C_i1' and C_i2 can be kept in charging mode by turning ON switches S_i2 and S_i6', respectively, whereas capacitors C_i1 and C_i2' are in disconnected mode, as shown in Fig. 3(b). Hence, the capacitors can be charged to the desired voltage level at zero output voltage level.

B. Generation of Voltage Level

A +V_i voltage level is generated across the output terminals when switches S_i1', S_i3', S_i4, S_i5', and S_i7' are in the ON position. In this switching state, capacitors C_i1' and C_i2' are charged to V_i and 4V_i, respectively, when switches S_i2 and S_i6 are turned ON, respectively, as shown in Table I and Fig. 3(c). In addition, capacitors C_i1 and C_i2 are in disconnected mode in this switching state. Similarly, −V_i can be produced at the output terminals by turning ON switches S_i1, S_i3, S_i4', S_i5, and S_i7. Simultaneously, capacitors C_i1 and C_i2 can be in charging mode by turning ON switches S_i2' and S_i6', respectively, whereas capacitors C_i1' and C_i2' are in disconnected mode, as shown in Table I and Fig. 3(d). The switching and capacitor states for generating +V_i and −V_i voltage levels are complementary to each other.

C. Generation of Voltage Level

When switches S_i1', S_i2', S_i4, S_i5', and S_i7' are turned ON, capacitor C_i1' is connected in series to V_i. Hence, the voltage across capacitor C_i1', i.e., v_Ci1' (which is nearly equal to V_i), is added with V_i and capacitor C_i1' is in discharging mode, as shown in Fig. 3(e). The output voltage is approximately equal to 2Vi (V_i + v_Ci1' + 2V_i). In this switching state, capacitors C_i1 and C_i2' can shift to charging mode by turning on switches S_i3 and S_i6, respectively, as shown in Table I and Fig. 3(e). The simultaneous charging and discharging of capacitors is possible in this switching state. Similarly, −2V_i can be developed at the output terminals by adding voltage across capacitor C_i1 with the input voltage V_i, as shown in Fig. 3(f) and Table I. The switching and capacitor states for generating +2V_i and −2V_i are complementary to each other, as shown in Figs. 3(e) and 3(f).

D. Generation of Voltage Level

A +3V_i voltage level is developed in the output terminals by subtracting capacitor voltage v_Ci1 from supply voltage 4V_i. This condition can be achieved by turning on switches S_i1, S_i2, S_i4, S_i5, and S_i7, as shown in Table I. Capacitor C_i1 is in charging mode under a positive load current (i_L+) during this switching state. In addition to C_i1, capacitors C_i1' and C_i2 can be maintained in charging mode by turning ON switches S_i3' and S_i6', respectively, as shown in Fig. 3(g). Fig. 3(h) presents the current flow paths when the output voltage level is −3V_i . Evidently, a −3V_i voltage level is generated by subtracting capacitor voltage v_Ci1' from input supply voltage 4V_i by turning ON switches S_i1', S_i2', S_i4', S_i5', and S_i7'. Capacitor C_i1' is in charging mode under a negative load current (i_L−), and capacitors C_i1 and C_i2 can be maintained in charging mode by turning on switches S_i3 and S_i6, respectively.

E. Generation of Voltage Level

A +8V_i voltage level can be developed in the output terminals by adding capacitor voltage v_Ci2 and supply voltage 4V_i. Hence, capacitor C_i2 is in discharging mode. This condition can be achieved by turning on switches S_i1, S_i3, S_i4, S_i6, and S_i7, as shown in Table I. Under this circuit condition, capacitors C_i1 and C_i2' can be maintained in charging mode by turning ON switches S_i2' and S_i5', respectively, as shown in Fig. 3(i). Fig. 3(j) presents the current flow path when the output voltage level is −8V_i. Evidently, the switching and capacitor states for generating +8V_i and −8V_i are complementary to each other.

F. Generation of Voltage Level

Figs. 3(k) and 3(l) present the equivalent circuits and current flow paths for output voltage levels +10V_i and −10V_i respectively. As shown in Table I, when switches S_i1', S_i2', S_i4, S_i6, S_i7, S_i3, and S_i5' are turned ON, capacitors C_i1' and C_i2 are connected in series to both supply voltages, whereas capacitors C_i1 and C_i2' are connected in parallel to V_i and 4V_i, respectively. Hence, capacitors C_i1' and C_i2 are in discharging mode, whereas capacitors C_i1 and C_i2' are in charging mode. In this state, the output voltage is the summation of the supply voltages, i.e., the voltages of C_i1' and C_i2, which are near +10V_i. Similarly, −10V_i can be produced by turning ON the complementary switches, such as that for +10V_i voltage generation, as shown in Table I and Fig. 3(l).

Moreover, other voltage levels can be produced in a similar manner across the load terminals, as shown in Table I. The following points can be noted with regard to the operating principle of the proposed SCMLI.

⋅ The proposed SCMLI exhibits boosting capability by using two voltage sources of magnitudes V_i and 4V_i. The proposed topology can generate a maximum output voltage of 10V_i. Hence, the boosting factor of the proposed topology is 2.

⋅ From Table I and Fig. 3, capacitors C_i1' and C_i2 are used to generate positive voltage levels. By contrast, capacitors C_i1 and C_i2' are used to generate negative voltage levels. This feature of the proposed topology reduces the discharging period of each capacitor, which further reduces the size of a capacitor. In addition, as shown in Table I and Fig. 3, the simultaneous discharging state of capacitors C_i1 and C_i1' or C_i2 and C_i2' will never occur under any operating state condition of the proposed circuit. Hence, when capacitor C_i1 is in discharging state, capacitor C_i2 simultaneously appears across the supply voltage in charging state, and vice-versa. The same observation is applied to capacitors C_i2 and C_i2'. Thus, the proposed topology can simultaneously charge and discharge the capacitors and exhibits inherent capacitor voltage balancing capability.

⋅ Furthermore, as shown in Table I and Fig. 3, a number of possibilities are clearly available to charge the capacitors in fundamental cycles. This feature can help prevent the capacitor voltage unbalancing problem in the proposed inverter.

Ⅲ. CASCADED STRUCTURE OF THE PROPOSED SCMLI

The cascaded structure of the proposed SCMLI is presented in this section. This structure is developed to generate a large number of output voltage levels that can enhance the quality of output voltage and the efficiency of the inverter system. Here, an m number of the proposed SCMLI modules are connected in series to develop the cascaded structure, as shown in Fig. 4. The voltage sources of each module are (V₁, 4V₁) for module 1, (V₂, 4V₂) for module 2, and (V_m, 4V_m) for module m. The output voltage (v_o(t)) of this structure can be expressed as follows:

       (1)

where v₀₁(t), v₀₂(t), and v_om(t) are the output voltage of module 1, module 2, and module m, respectively. The required power switches (N_s/w), required capacitors (N_cap), required DC sources (N_DC), switches in the charging path of a capacitor (N_cpath), and maximum conducting switches (N_cpath) for the proposed topology in terms of m can be expressed by (2) to (6).

       (2)

       (3)

        (4)

       (5)

    (6)

Fig. 4. Cascaded structure of the proposed SCMLI.

Each module can produce bipolar output voltage levels; thus, an asymmetric DC voltage source configuration is proposed for generating the maximum output voltage level. In the proposed configuration, the magnitudes of DC voltage sources for modules 1 and 2 can be expressed by (7) and (8).

     &sp;               (7)

   (8)

where v_o1max is the maximum voltage generated by module 1. Similarly, the magnitudes of DC voltage sources for modules 3 and 4 can be expressed by (9) and (10), respectively.

        (9)

         (10)

where v_o2max and v_o3max are the maximum voltage generated by modules 2 and 3, respectively. Likewise, the input voltage for the m^th module can be expressed by (11).

           (11)

In this DC voltage source configuration, the capacitor voltages for different modules can be expressed by (12) and (13).

   (12)

        (13)

Moreover, the generated output voltage levels (N_L) and TSV of the cascaded structure can be expressed by (14) and (15).

       (14)

     (15)

Ⅳ. SELECTION PROCEDURE FOR SC CAPACITANCE

The selection procedure for the capacitance of the utilized capacitors in the proposed 21-level SCMLI structure is presented in this section. The output voltage with the inverted negative cycle is shown in Fig. 5 when the fundamental switching frequency scheme is considered. On the basis of the switching state presented in Table I, the largest discharging time (LDT) of the capacitors is shown in Fig. 5. The maximum discharge amount from the capacitors is presented by (16) and (17) when the sinusoidal load current is considered.

   (16)

   (17)

where I_out , f, and φ are the peak magnitude of the load current, fundamental frequency, and phase angle between the output voltage and current, respectively. When (P₁×V_i) and (P₂×4V_i) are regarded as the highest allowable voltage ripples for capacitors C_i1 (or C_i1') and C_i2 (or C_i2'), respectively, the optimum values of the capacitance can be given by (18) and (19).

      (18)

        (19)

where P₁ and P₂ are constants. This procedure for selecting switched capacitors can be extended to a higher voltage level of the proposed inverter structure.

Fig. 5. LDT of the SCs for the proposed 21-level SCMLI.

Ⅴ. POWER LOSS ANALYSIS

The power losses and efficiency of the proposed 21-level SCMLI structure are presented in this section. Three major power losses are associated with the proposed structure, namely, switching losses (P_sw), conduction losses (P_con), and capacitor ripple losses (P_ripple). The total loss (P_loss) of the inverter can be defined by (20).

   (20)

The efficiency (η) of the proposed inverter can be expressed by (21)

    (21)

where P_out is the output power of the inverter. The different losses are presented in detail in the following subsections.

A. Switching Losses

The switching losses of a power switch occur when the switch is in a transition state; that is, when the switch position is changed from OFF to ON or from ON to OFF. When linear approximation between the switch current and the switch voltage during the transition periods t_on and t_off is considered, the energy losses that occur in the i^th power switch can be expressed by (22) and (23).

   (22)

       (23)

where f_sw is the switching frequency; and I_i and I_i' present the switch current after ON and before OFF conditions, respectively. To find the energy losses per fundamental cycle of the i^th switch, the number of ON transitions (N_on,i) and OFF transitions (N_off,i) per cycle should be calculated. Then, the energy losses per cycle for the i^th switch can be expressed by (24).

         (24)

The switching power losses of the i^th switch per cycle can be expressed by (25).

         (25)

where T is the time for a fundamental cycle.

The overall switching losses of the proposed 21-level inverter can be evaluated by (26).

      (26)

B. Conduction Losses

To determine the conduction losses of the proposed inverter structure, the internal resistance of each component, such as power switches and capacitors, should be considered. For simplicity, all the capacitors are assumed to have the same equivalent series resistance (ESR) r_esr and all the power switches have the same on-state resistance r_on. The resistive load condition results in the worst case conduction loss due to the absence of negative current; thus, the resistive load is considered to calculate conduction losses. Figs. 6(a) and 6(b) show the equivalent circuits with r_on and r_esr when the output voltage level is +V_i and −V_i. The equivalent circuits are clearly complementary to each other. Hence, the same amount of conduction losses will occur in these voltage levels. As shown in Fig. 6(a), the different Kirchhoff’s voltage law equations can be expressed by (27) to (29).

           (27)

        (28)

          (29)

where i_C1, i_C2, and i_L+ are the charging current for C_i1', charging current for C_i2', and positive load current, respectively. The instantaneous conduction power loss during the first positive voltage level can be expressed by (30).

        (30)

Fig. 6. Equivalent circuits for evaluating conduction losses of the proposed inverter structure when output voltage: (a) +V_i , (b) −V_i , (c) +2V_i,, (d) +10V_i.

(a)	(b)
(c)	(d)

Similarly, the instantaneous conduction power loss during the first negative voltage level can be depicted by (31).

        (31)

where i_L− is the negative load current. The load current is symmetrical in both half cycles; hence, i_L+ is equal to i_L−. Moreover, the capacitor charging current is the same in both half cycles. Thus, the conduction power loss remains the same during the first positive and negative voltage levels. Similarly, as shown in Figs. 6(c) and 6(d), the instantaneous conduction power losses during the second and tenth positive voltage levels can be depicted by (32) and (33).

          (32)

           (33)

From the preceding discussion, the conduction power losses in both half cycles are the same. Furthermore, the average conduction power losses over a cycle can be evaluated by determining the duration of each level. As shown in Fig. 5, the duration of the first positive voltage level is (t₂−t₁) s in T. Hence, the average conduction power loss during the first positive and negative voltage levels can be expressed by (34).

    (34)

Similarly, the average conduction power losses for other voltage level durations can be evaluated. Thus, the average conduction losses over a cycle can be evaluated by (35).

     (35)

C. Capacitor Ripple Losses

Capacitor ripple losses occur due to voltage difference between the capacitor voltage and the respective input voltage. If a capacitor C_k is connected in discharging mode for a maximum duration of (t_j+1−t_j), then the maximum voltage ripple of the corresponding capacitor C_k can be expressed by (36).

       (36)

i_Ck(t) is the capacitor current when the capacitor is in discharging mode. This current is typically the same as the load current. Hence, the capacitor ripple losses over a cycle of C_k can be expressed by (37).

    (37)

Similarly, the ripple losses for capacitors C_i1, C_i1', C_i2, and C_i2' over a cycle can be determined. The total capacitor ripple losses per cycle can be expressed by (38).

           (38)

Ⅵ. COMPARISON STUDY

This section presents a comparison study of the proposed SCMLI with other topologies in terms of different aspects, such as the required switches, drivers, diodes, capacitors, TSV, and PIV for generating a specific output voltage level. In addition, a CF is defined as presented by (39) to prove the cost-effectiveness of the proposed topology relative to other topologies.

          (39)

where (TSV+PIV)_pu represents the per unit (TSV+PIV), which is defined by (40); and α is a weighting factor.

    (40)

where v_omax is the maximum output voltage. This section is divided into two subsections. In the first subsection, the proposed 21-level SCMLI is compared with other topologies. In the second subsection, the cascaded SCMLI structure is compared with other cascaded structures for asymmetric DC source configurations.

A. Comparison of the Proposed 21-level SCMLI with other MLI Topologies

Table II presents the comparison of the proposed 21-level SCMLI with a binary CHB structure, a recently published “RDC” MLI structure [15], a novel step-up SCMLI structure [24], and a hybrid MLI structure (second proposed topology) using SC basic units [22]. On the basis of Table II, the proposed SCMLI can produce a higher number of output voltage levels using reduced DC power supplies compared with the binary CHB structure. Although the CHB structure does not require any capacitor, CF/N_L is higher than that of the proposed topology, which signifies that the cost of the proposed topology is less than that of the CHB structure at the same output voltage level. Compared with [15], the proposed topology requires higher power switches to produce the same output voltage levels, but [15] requires power diodes. Moreover, (TSV+PIV)_pu is higher than that of the proposed topology. Although the topology in [15] achieves less CF/N_L than the proposed topology, it does not possess voltage-boosting and capacitor voltage-balancing capabilities. Compared with the SCMLI structures, the (TSV+PIV)_pu of the proposed topology is less than those of [22] and [24]. With respect to CF/N_L, the proposed topology is less costly than the topologies presented in [22] and [24] at the same output voltage level.

TABLE II COMPARISON OF THE PROPOSED 21-LEVEL SCMLI WITH OTHER TOPOLOGIES

Parameters	CHB binary	[15]	[24]	[22]	Proposed topology
NL	15	23	19	17	21
Ns/w	12	13	12	10	14
Ndr	12	13	12	10	14
Ndc	3	2	2	2	2
Ndiode	0	3	6	4	0
Ncap	0	5	4	2	4
TSV+PIV	28VDC	19VDC	51VDC	52VDC	50VDC
(TSV+PIV)pu	4	5.18	5.67	6.5	5
Ncpath	6	9	5	6	5
Vm	4VDC	2.6VDC	8VDC	8VDC	8VDC
CF/Nlevels α=0.5	5.2	3.18	3.87	3.44	3.28
CF/Nlevels α=1.5	6	3.63	4.47	4.03	3.76
Boosting Feature	No	No	Yes	Yes	Yes
Capacitor Voltage Balance Capability	Not required	No	Yes	Yes	Yes

B. Comparison of the Cascaded Structure of the Proposed SCMLI with other Cascaded MLI Topologies

In this section, the cascaded structure of the proposed SCMLI is compared with binary CHB, a novel cascaded H-bridge-based MLI structure [14], a hybrid MLI (second topology) using basic SC units [22], and a new cascaded SCMLI structure [25]. All the suggested MLI structures are modular and asymmetrical. Table III presents the general equations for the different parameters of the proposed SCMLI and the other MLI structures in terms of N_L.

TABLE III COMPARISON OF THE CASCADED STRUCTURE OF THE PROPOSED SCMLI WITH OTHER TOPOLOGIES

Topology presented in	Nsw	Nvar = Ndc	Ncap	Ndiode	Ncpath	(TSV+PIV)×VDC	Boosting capability
CHB [Binary]			-	-			No
[14]			-	-			No
[22]							Yes
[25]							Yes
Proposed topology				-			Yes

Figs. 7(a) to 7(f) show the variations in the required power switches, required DC power supplies and their varieties, required power diodes, required capacitors, TSV and PIV, and the maximum conducting switches versus the output voltage levels N_L of the proposed SCMLI and other MLI structures, respectively. As shown in Fig. 7(b), the proposed topology requires less number and variety of DC sources compared with all the other suggested topologies when generating a specific output voltage level. Although the proposed topology requires more switches and capacitors than the topologies presented in [22] and [25], the TSV and PIV of these topologies are significantly higher than those of the proposed topology when generating a specific output voltage level. Fig. 7(f) shows that the proposed topology requires the minimum number of switches in the conducting path compared with the other suggested topologies. The variation in CF/N_L for α=1.5 between the proposed and suggested topologies is illustrated in Fig. 8. The proposed topology provides less CF/N_L than the binary CHB and the topology presented in [22]. The variations in CF/N_L of the proposed topology and the topology presented in [14] are similar, but the topology developed in [14] does not exhibit self-voltage boosting capability. Although the variation in CF/N_L of the topology presented in [25] is less than that of the proposed topology, the application of the former  can be restricted due to the significantly higher TSV and PIV of the structure compared with that of the proposed topology.

Fig. 7. Variation: (a) Required power switches, (b) Required DC sources and variety of DC sources, (c) Required power diodes, (d) Required capacitors, (c) TSV of the switches and PIV of the power diodes, (e) Maximum number of components in the current- conducting path with respect to output voltage level.

(a)	(b)
(c)	(d)
(e)	(f)

Fig. 8. Variation in CF/N_L vs. N_L.

Ⅶ. SIMULATION AND EXPERIMENTAL RESULTS

To verify the performance of the proposed topology, extensive simulation and experimental studies are conducted on the 21-level proposed topology. MATLAB/Simulink software is used for simulation. In both studies, the magnitudes of the DC power supplies are set as 10 V and 40 V. With these DC sources, the proposed topology can produce a maximum output voltage of 100 V. For simplicity, all the capacitor values are set as 5000 µF. The experimental setup for the proposed SCMLI is shown in Fig. 9. Different switching pulses based on fundamental switching frequency schemes are generated by the dSPACE (DS1104) controller. An IRF840 (n-channel metal-oxide-semiconductor field-effect transistor) is selected as the power-switching device.

Fig. 9. Prototype of the proposed 21-level SCMLI.

The simulation and experimental results under different load conditions are shown in Figs. 10 to 20. The load voltage and load current for R–L load (R=36 Ω, L=50 mH) condition are shown in Fig. 10. Fig. 10(a)presents the simulated 21-level load voltage and load current, whereas the experimental 21-level load voltage and load current are presented in Fig. 10(b). From Fig. 10, the simulation and experimental results are verified to be comparable with each other. The experimental maximum output voltage is 99 V, and the peak load current is 2.5 A. Figs. 11(a) and 11(b)show the 21-level output voltage waveforms in the simulation and experimental studies in a quarter time frame (T/4), respectively. Figs. 12 and 13 present the load voltage when only one source is active in the simulation and experimental studies, respectively. When the V_i (10 V) source is active, the variation in load voltage is between +20 V and −20 V. When the 4V_i (40 V) source is active, the variation in load voltage is between +80 V and −80 V. When both sources are active, waveforms are added and subtracted to generate the 21-level output voltage waveform, as shown in Fig. 1.

Fig. 10. Load voltage and load current waveforms: (a) Simulation, (b) Experiment (50 V/div and 2 A/div) for R–L load (R=36 Ω, L=50 mH).

(a)

(b)

Fig. 11. Twenty-one output voltage levels: (a) Simulation, (b) Experiment (26.4 V/div).

(a)

(b)

Fig. 12. Simulation output voltage when only one source is active.

Fig. 13. Experimental output voltage when only one source is active.

The capacitor voltages and the ripple associated with them are shown in Figs. 14 and 15, respectively. As clearly shown in Fig. 14, the capacitor voltages are maintained at the desired voltage levels with the switching scheme presented in Table I. The voltage magnitudes of C_i2 and C_i2' are approximately 40 V, as depicted in Fig. 14, whereas the voltage magnitude of C_i1' is approximately 10 V. Similarly, the voltage of capacitor C_i1 is produced at approximately 10 V. The simulated capacitor voltage ripples for capacitors C_i2 and C_i1 are shown in Fig. 15(a). Likewise, the experimental voltage ripples for capacitors C_i2 and C_i1 are presented in Fig. 15(b). With the selected capacitor values, the peak-to-peak voltage ripple for capacitors C_i1 and C_il' is 0.75 V (7.5% of 10 V), whereas that for capacitors C_i2 and C_i2' is 1.9 V (4.75% of 40 V). Figs. 14 and 15 clearly show that the proposed topology can produce the desired capacitor voltages.

Fig. 14. Experimental waveforms of capacitor voltages.

Fig. 15. Capacitor voltage ripple waveforms: (a) Simulation, (b) Experiment.

(a)

(b)

The proposed topology provides the minimum total standing voltage compared with the SCMLI topologies discussed in the comparison section. The blocked voltages of power switches S_i4, S_i7, and S_i3 are shown in Fig. 16. The TSV of the proposed SCMLI is calculated as 495 V.

Fig. 16. Stress voltage across switches S_i4, S_i7, and S_i3.

To examine the effectiveness of the proposed topology under an inductive load condition, the topology is loaded with 275 mH inductive load. The load voltage and current are shown in Fig. 17. This figure clearly illustrates that the generated load voltage has 21 levels, whereas the output current is a pure sinusoid. Furthermore, the output current exhibits a phase lag of approximately 90° with respect to the voltage waveform, which proves the effectiveness of the proposed topology under an inductive load condition.

Fig. 17. Load voltage and current waveforms under an inductive load (L=275 mH) condition (50 V/div and 1 A/div).

Meanwhile, to prove the effectiveness of the proposed topology under a dynamic load condition, the inverter load is suddenly increased or decreased, and the performance of the inverter is verified by observing the changes in load current and capacitor voltage. Figs. 18(a) and 18(b) show the variations in load current and capacitor voltages under suddenly decreasing and increasing load conditions, respectively. The figures clearly indicate that due to a sudden load change, the capacitor voltages are maintained at the desired values and the desired load current is generated. This result proves the effectiveness of the proposed topology under a dynamic load condition.

Fig. 18. Variation in experimental load current and capacitor voltages: (a) Decreasing, (b) Increasing load conditions.

(a)

(b)

The variations in source currents in the simulation and experimental studies under R–L load condition (R=36 Ω and L=50 mH) are shown in Figs. 19(a) and 19(b), respectively. The simulation and experimental input currents are comparable. In addition, the drawn input currents are discontinuous because of the switching operation of capacitors. Furthermore, the variation in currents through capacitors C_i1' and C_i2' in the simulation and experimental studies are shown in Figs. 20(a) and 20(b), respectively, under the same load condition. The simulated and experimental capacitor currents are in agreement with each other. The variations in currents through capacitors C_i1 and C_i2 are similar to those through C_i1' and C_i2', respectively.

Fig. 19. Variation in source currents: (a) Simulation, (b) Experiment for R–L load (R=36 Ω, L=50 mH).

(a)

(b)

Fig. 20. Variation in currents of capacitors C_i1' and C_i2': (a) Simulation, (b) Experiment for R–L load (R=36 Ω, L=50 mH).

(a)

(b)

The fast Fourier transform (FFT) analyses of load voltage and load current under R–L load (R=36 Ω and L=50 mH) condition are presented in Figs. 21(a) and 21(b), respectively. As shown in Fig. 21(a), the peak fundamental and total harmonic distortion (THD) of load voltage are 92 V and 4.33%, respectively. Similarly, the peak fundamental and THD of load current are 2.46 A and 3.32%, respectively, as shown in Fig. 21(b). The output power of the proposed inverter is 104 W. The total power loss of the inverter is 8.1 W. The experimental conduction loss is 7.05 W, whereas the other losses are approximately 1.05 W. When the fundamental switching frequency scheme is used, switching loss is considerably less. By contrast, when the maximum ripple voltage is  2 V and capacitor values are 5000 µF, capacitor ripple loss is also smaller than conduction loss. The efficiency of the inverter is approximately 92.7%. Compared with the topologies presented in [22] and [25], the efficiency of the proposed topology is more similar to that shown in Table IV. The efficiency of the inverter is reduced with an increase in output power, as shown in Fig. 22.

Fig. 21. FFT analysis: (a) Load voltage, (b) Load current for R–L load (R=36 Ω, L=50 mH).

(a)

(b)

Fig. 22. Efficiency variation of the proposed inverter with respect to output power.

TABLE IV EFFICIENCY COMPARISON OF THE PROPOSED TOPOLOGY WITH THE TOPOLOGIES PRESENTED IN [22] AND [25]

Topology	Output power (W)	Experimental efficiency (%)	Switch used
Proposed	104	92.7	IRF840
[22]	129	86	BUP306D
[25]	364	88	SPW47N60C3

Ⅷ. CONCLUSION

A novel SCMLI structure is proposed in this study. The proposed topology exhibits the capability to boost input voltages. Furthermore, the topology can balance capacitor voltages by using a simple switching strategy. A cascaded structure of the proposed SCMLI is also developed. An asymmetric DC source configuration is proposed for the cascaded structure. A CF is developed to prove the cost- effectiveness of the proposed topology compared with other topologies. The proposed topology provides significantly lower TSV than the other topologies. Therefore, the proposed topology can be utilized in high-voltage applications. To prove the advantages of the proposed topology, the results of extensive simulation and experimental studies are presented. The proposed topology can be applied to renewable energy conversion systems.

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Tapas Roy obtained his B.S. in Electrical Engineering from Jadavpur University, Kolkata, India in 2009 and his M.S. in Electrical Engineering from the Indian Institute of Science, Bangalore, India in 2013. He is working as a part-time Ph.D. research scholar in the Department of Electrical Engineering, Indian Institute of Technology, Dhanbad, India. His current research interests include switched capacitor multilevel inverters (MLIs), Z-source inverters, and control strategies for MLIs.

Bidrohi Bhattacharjee obtained his B.S. in Electrical Engineering and M.S. in Illumination Technology and Design from Jadavpur University, West Bengal, Kolkata, India. He is working as a part-time Ph.D. research scholar in the Department of Electrical Engineering, Indian Institute of Technology, Dhanbad, India. His research interests include power electronics, drives, solar energy, switched capacitor multilevel inverters, and DC–DC converters.

Pradip Kumar Sadhu obtained his B.S., M.S., and Ph.D. in Electrical Engineering from Jadavpur University, Kolkata, India in 1997, 1999, and 2002, respectively. He is currently working as a professor and head of the Department of Electrical Engineering of the Indian Institute of Technology (Indian School of Mines), Dhanbad, India. His current research interests include power electronics applications, the application of high-frequency converters, energy-efficient devices, and energy-efficient drives.

Abhijit Dasgupta obtained his B.S. in Electrical Engineering from REC Durgapur, Durgapur, India in 1977 and his M.S. in Power Electronics from the Indian Institute of Technology, Kanpur, India in 1980. He has been a professor at the School of Electrical Engineering, KIIT University, Bhubaneswar, India since 2004. He has several journal and conference publications at the national and international levels. His current research interests include power electronics, the digital control of electric drives, automatic generation control, and the implementation of new optimization techniques.

Srikanta Mohapatra obtained his M.S. in Electrical Engineering with specialization in Power Electronics and Drives from SOA University, Bhuabneswar, India in 2009. He obtained his Ph.D. in Electrical Engineering from KIIT University, Bhubaneswar, India in 2014. He is currently an associate professor in the School of Electrical Engineering, KIIT University, Bhubaneswar, India. He has over one decade of research experience. He has published many papers in conferences and international journals. His areas of interest are DC–DC converters for solar photovoltaic applications, multilevel inverters, and flexible AC transmission system controllers for electric power systems.