사각형입니다.

https://doi.org/10.6113/JPE.2018.18.4.1223

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Mitigation of Voltage Unbalances in Bipolar DC Microgrids Using Three-Port Multidirectional DC-DC Converters


Taha Ahmadi*, Esmaeel Rokrok, and Mohsen Hamzeh**


†,*Department of Electrical and Electronics Engineering, Lorestan University, Lorestan, Iran

**School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran



Abstract

In this paper, a new three-port multidirectional DC-DC converter is proposed for integrating an energy storage system (ESS) to a bipolar DC microgrid (BPDCMG). The proposed converter provides a voltage-balancing function for the BPDCMG and adjusts the charge of the ESS. Thanks to the multi-functional operation of the proposed converter, the conversion stages of the system are reduced. In addition, the efficiency and weight of the system are improved. Therefore, this converter has a significant capability when it comes to use in portable BPDCMGs such as electric DC ships. The converter modes are analyzed and small-signal models of the converter in each of the independent modes are extracted. Finally, comprehensive simulation studies are carried out and a BPDCMG laboratory prototype is implemented in order to verify the performance of the proposed voltage balancer using the burst mode control scheme.


Key words: Bipolar DC microgrid, Line voltage unbalance rate, Multidirectional converters, Three-port converters (TPCs), Voltage balancer


Manuscript received Nov. 9, 2017; accepted Feb. 13, 2018

Recommended for publication by Associate Editor Kai Sun.

Corresponding Author: rokrok.e@lu.ac.ir Tel: +98-66-33120005, Lorestan University

*Dept. of Electrical and Electronics Engineering, Lorestan University, Iran

**School of Electr. and Comp. Eng., College of Eng., Univ. of Tehran, Iran



Ⅰ. INTRODUCTION

DC microgrids, when compared to AC microgrids, have received a lot of attention in the pursuit of operational solutions for new structure energy delivery problems. There are many power quality issues encountered with DC microgrids such as DC voltage drop, voltage oscillations, circulating current and voltage fluctuations. These issues have been carefully considered and have been discussed in previous studies [1], [2]. DC microgrids are categorized into two types [3]: unipolar-type and bipolar-type [4]. Unipolar DC microgrids have one voltage level in a two-wire DC distribution network. On the other hand, BPDCMG type microgrids have two voltage levels in a three-wire DC distribution network (positive, neutral, and negative). BPDCMGs are more reliable due to the possibility of supplying loads under abnormal operating conditions such as the loss of one polarity. As a result, in Intel and IBM data centers, power distributions of ± 190V or ± 200V have been utilized, in order to increase the reliability of the power supplies [5]. A BPDCMG can also increase the power transmission capability and overall efficiency of systems due to their lower current levels. In addition to the advantages of the BPDCMG, it also has some challenges. In fact, when loads are connected to the upper and lower terminals, they may have different powers. Therefore, the voltage of the terminals may drift from the rated value, which results in a voltage imbalance in BPDCMGs [6]. To quantify this voltage imbalance, the line voltage unbalances rate equation (LVUR) is utilized [7].

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원본 그림의 이름: CLP000007d0000c.bmp
원본 그림의 크기: 가로 1041pixel, 세로 378pixel     (1)

Where 그림입니다.
원본 그림의 이름: CLP000007d0000d.bmp
원본 그림의 크기: 가로 61pixel, 세로 73pixel and 그림입니다.
원본 그림의 이름: CLP000007d0000e.bmp
원본 그림의 크기: 가로 65pixel, 세로 73pixel are the positive and negative buses voltages. The voltage unbalance and voltage drop are closely related to the power quality in distribution systems. In [8], a technique for voltage regulation in BPDCMGs that employs neutral to line drop compensation is used to restrain the LVUR. This method uses the neutral current and neutral line equivalent impedance to solve the neutral line potential fluctuation. In [9]-[12], the effects of an imbalanced voltage in the BPDCMG are presented and various interlink converters (IC) have been proposed to mitigate them. In [5], various voltage balancer circuits have been proposed. The IC structure is composed of a voltage balancer in series with a voltage-source inverter (VSI). However, these circuits tend to only balance the voltage at one end of the BPDCMG. A number of disadvantages can be found in these papers. 1) There is a reduction of system reliability (which is one of the main features of BPDCMGs) due to supplying loads using a single converter. 2) Due to a series connection of the VSI and the voltage balancer, the power of the voltage balancer should be equal to that of the VSI. 3) In the island mode, when the IC is disconnected from the power grid, the voltage balancer control system should be switched to the island mode, which causes significant voltage transients [13]. 4) In a BPDCMG with a long feeder length, these methods cannot bring the neutral line current to zero. A new structure has been proposed in [6] to compensate for these issues. In this structure, each of the distribution generator (DG) units provides the voltage- balancing function in addition to the interlink converter connected to the BPDCMG. Although this topology improves voltage balancing, due to the increasing number of converters, the system efficiency (which is also another main advantage of bipolar DC microgrids) is decreased.

To overcome the above-mentioned problems, an interleaved dc-dc converter was introduced in [7] to mitigate the unbalanced voltage. In [14], the concept of the BPDCMG was introduced. In this configuration, it is assumed that the voltage control units are distributed on the positive and negative buses. Therefore, a new configuration for the two-layer control strategy is applied on the IC converter in order to balance and manage the power. The authors of [15] focused on comparing single half-bridge and three phase half-bridge current redistributors. A new half-bridge voltage, which can adjust the unequal voltage between the positive and the negative terminals, is described in [16]. In [17], a method is introduced to mitigate the voltage unbalance and to reduce the power loss due to the neutral current in a BPDCMG by using a static load transfer switch. The advantage of these methods is that there is no need to have active sources as the compensator. In this regard, due to the fact that batteries play an important role in BPDCMGs, it is possible to achieve a new structure for the battery converter in order to mitigate unbalanced voltage in addition to charging and discharging the battery. Therefore, the benefits of this new converter are: 1) enhanced loadability of the BPDCMG due to the ability of transferring the loads of one terminal to another terminal; 2) a reduction in the number of converters by integrating the voltage balancing converter and the battery converter; 3) reductions in the current of the neutral line and its associated power losses, while the IC converters cannot eliminate the neutral line current for a BPDCMG with a long feeder length, due to the fact that they only attempt to balance the voltage at one end of the BPDCMG [7]; 4) the possibility of balancing the voltage in the island condition of the BPDCMG by disconnecting the interlink converter.

Multi-port bi-directional DC-DC converters have attracted special interest in applications where multiple energy sources are used [18]. In [19], a family of non-isolated DC-DC three- port converters (TPCs) for integrating renewable-energy sources (RESs) and energy storage systems into a DC bus has been proposed. In [20], a multi-port converter to integrate the energies of a PV panel, a fuel cell and a battery to supply local loads has been introduced. In [21], a three-port DC-DC boost converter has been introduced. The introduced converter interfaces two unidirectional input power ports and a bidirectional port for a battery. This converter can supply a load, charging or discharging a battery by the sources connected to the ports either individually or simultaneously. Since multiple voltages are required in some applications, several studies have been done for different types of single- input multiple-output converters [22]. In [23], a single- inductor dual-output boost converter has been presented. This topology can be extended to have multiple outputs and can be applied to buck, flyback and other kinds of converters. In [24], based on the flyback converter, a new three-port dc-dc converter to integrate PV and battery systems to feed loads connected to the converter has been proposed. The flyback converter has many advantaged, such as a high output voltage range, isolation of the ports voltages and a cost effective structure [25]. As can be seen, although a lot of investigation have been done on TPCs, these topologies are mostly designed to integrate multiple energy sources at certain polarities for consuming loads at other polarities and cannot transfer power from all three of the polarities to each other. Therefore, solutions for integrating batteries and BPDCMGs are still farily limited. Within this context, this paper focuses on the voltage balancing of a BPDCMG while proposes a new isolated three-port multidirectional converter by integrating a battery system with a BPDCMG, which has the ability to balance the positive and negative terminal voltages, in addition to charging and discharging the battery. The proposed three-port multidirectional converter is based on the three-port flyback converter.



Ⅱ. DESCRIPTION OF THE PROPOSED THREE-PORT MULTIDIRECTIONAL CONVERTER

The structure of a BPDCMG is shown in Fig. 1. In the BPDCMG, loads can be connected between the positive and negative terminals, the positive and neutral terminals, and the negative and neutral terminals. Since the last two cases may cause voltage imbalances between the upper and lower buses, it is necessary to utilize a voltage balancing strategy. Therefore, the proposed three-port multidirectional converter is integrated into the BPDCMG to balance the voltages of the positive and negative terminals.


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원본 그림의 이름: CLP000007d0000f.bmp
원본 그림의 크기: 가로 1298pixel, 세로 901pixel

Fig. 1. Typical isolated BPDCMG with the proposed converter.


The proposed three-port multidirectional converter is depicted in Fig. 2. As can be seen in this figure, in the primary side of the transformer,그림입니다.
원본 그림의 이름: CLP000007d00011.bmp
원본 그림의 크기: 가로 108pixel, 세로 68pixel, 그림입니다.
원본 그림의 이름: CLP000007d00012.bmp
원본 그림의 크기: 가로 55pixel, 세로 65pixel and 그림입니다.
원본 그림의 이름: CLP000007d00013.bmp
원본 그림의 크기: 가로 70pixel, 세로 69pixel stand for the ESS voltage, ESS output current and magnetization inductance. Dual secondary windings are available on the other side of the transformer. In this side, 그림입니다.
원본 그림의 이름: CLP000007d00014.bmp
원본 그림의 크기: 가로 76pixel, 세로 68pixel and 그림입니다.
원본 그림의 이름: CLP000007d00015.bmp
원본 그림의 크기: 가로 70pixel, 세로 66pixel are the currents of the secondary windings, 그림입니다.
원본 그림의 이름: CLP000007d00016.bmp
원본 그림의 크기: 가로 60pixel, 세로 71pixel and 그림입니다.
원본 그림의 이름: CLP000007d00017.bmp
원본 그림의 크기: 가로 63pixel, 세로 67pixel denote the output voltage filter capacitors, 그림입니다.
원본 그림의 이름: CLP000007d00018.bmp
원본 그림의 크기: 가로 64pixel, 세로 68pixel and 그림입니다.
원본 그림의 이름: CLP000007d00019.bmp
원본 그림의 크기: 가로 71pixel, 세로 71pixel are the equivalent load resistors of the BPDCMG, 그림입니다.
원본 그림의 이름: CLP000007d0001a.bmp
원본 그림의 크기: 가로 59pixel, 세로 54pixel and 그림입니다.
원본 그림의 이름: CLP000007d0001b.bmp
원본 그림의 크기: 가로 69pixel, 세로 53pixel are the output DC voltages, 그림입니다.
원본 그림의 이름: CLP000007d0001c.bmp
원본 그림의 크기: 가로 68pixel, 세로 60pixel 그림입니다.
원본 그림의 이름: CLP000007d0001d.bmp
원본 그림의 크기: 가로 87pixel, 세로 53pixel and 그림입니다.
원본 그림의 이름: CLP000007d0001e.bmp
원본 그림의 크기: 가로 88pixel, 세로 55pixel denote for the primary, secondary and tertiary turns numbers.


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원본 그림의 이름: CLP000007d00010.bmp
원본 그림의 크기: 가로 1532pixel, 세로 693pixel

Fig. 2. Proposed three-port multidirectional converter for integrating a battery system to a BPDCMG.


The proposed converter was analyzed under the island operating mode of the BPDCMG. In this mode, the interplay of the battery and the RESs has a considerable role. Usually, the proposed three-port multidirectional converter operates under constant-voltage mode control, and causes additional power losses such as switching loss and conduction loss [26]. To increase the system efficiency and reliability, the proposed three-port multidirectional converter operates under the burst mode or with the skip mode control method. The burst control mode operates using the cycle-skipping method to reduce the switching loss in a low power switching converter and to increase the operational efficiency. During cycle skipping, each skip of the switching can be started at the minimum-allowed voltage value and stopped at the maximum-allowed-voltage value [27].

Based on the burst control scheme, a similar strategy can be employed for the proposed converter in low-voltage bipolar DC microgrids. Fig. 3 shows the seven operation modes of the proposed converter for operating in the BPDCMG. To simplify the analysis of the proposed converter, it is assumed that the indexes ‘I ’ and ‘J ’ are defined as: 그림입니다.
원본 그림의 이름: CLP000007d00020.bmp
원본 그림의 크기: 가로 344pixel, 세로 68pixel.


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원본 그림의 이름: CLP000007d0001f.bmp
원본 그림의 크기: 가로 1069pixel, 세로 866pixel

Fig. 3. Operation modes of the proposed converter.


A. Mode 1: Natural Balance Mode (NBM)

Based on the idea of burst mode, a two-dimensional burst mode control scheme was considered for the proposed converter. As shown in Fig. 3, when VI and VJ are inherently kept between Vmin-allowed and Vmax-allowed, the proposed converter does not operate and the battery is isolated.


B. Mode 2: Dual Input Single Output-Charging of the Battery (DISO-C)

When 그림입니다.
원본 그림의 이름: CLP000007d00021.bmp
원본 그림의 크기: 가로 762pixel, 세로 84pixel, the RESs generation potential is more than the load demands at any two terminals. In this condition, if the battery does not reach its maximum state of charge (SOC), it is charged by the redundant power of both the negative and positive terminals. The operation states of this mode are defined as follows (see Fig. 4):


Fig. 4. States of mode 2: (a) State I; (b) State II.

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원본 그림의 이름: CLP000007d00025.bmp
원본 그림의 크기: 가로 1533pixel, 세로 726pixel

(a)

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원본 그림의 이름: CLP000007d00026.bmp
원본 그림의 크기: 가로 1525pixel, 세로 683pixel

(b)


State I: S12, S13, S22, S23 and Sp1 are turned ON. Therefore, Lm absorbs energy from V1 and V2.

State II: SP1 stays ON and the absorbed energy is sent to the battery by DP2.


C. Mode 3: Single Input Single Output-Charging of the Battery (SISO-C)

When 그림입니다.
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원본 그림의 크기: 가로 678pixel, 세로 81pixel and the battery does not reach its maximum SOC, it is charged by the redundant power of terminal ‘I ’. The states of this mode are defined as follows (see Fig. 5):


Fig. 5. States of mode 3, assuming I=1: (a) State I; (b) State II.

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원본 그림의 이름: CLP000007d00027.bmp
원본 그림의 크기: 가로 1546pixel, 세로 682pixel

(a)

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원본 그림의 이름: CLP000007d00028.bmp
원본 그림의 크기: 가로 1540pixel, 세로 649pixel

(b)


State I: SI3, SI2 and Sp1 are ON. The transformer absorbs energy from VI.

State II: Sp1 stays ON. The transformer sends energy to charge the battery through the forward-biased Dsp2.


D. Mode 4: Single Input Dual Output-Charging of the Battery and Transferring of Redundant Power (SIDO-C)

When 그림입니다.
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원본 그림의 크기: 가로 417pixel, 세로 80pixel, 그림입니다.
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원본 그림의 크기: 가로 682pixel, 세로 89pixel and 그림입니다.
원본 그림의 이름: CLP000015e4140c.bmp
원본 그림의 크기: 가로 663pixel, 세로 79pixel, the redundant power of terminal ‘I’ is transferred to both the battery and terminal ‘J’. The states of this mode are defined as follows (see Fig. 6):


Fig. 6. States of mode 4, assuming I=1: (a) State I; (b) State II.

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원본 그림의 이름: CLP000007d0002b.bmp
원본 그림의 크기: 가로 1514pixel, 세로 646pixel

(a)

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원본 그림의 이름: CLP000007d0002c.bmp
원본 그림의 크기: 가로 1510pixel, 세로 661pixel

(b)


State I: SI3, SI2 and Sp1 are turned ON. The transformer absorbs energy from VI.

State II: Sp1 and SI2 stay ON. Therefore, the transformer sends power to charge the battery through the forward- biased Dsp2 and terminal ‘J’ through SI2, DI1, DJ3 and Dm.


E. Mode 5: Single Input Single Output-Buck-Boost (SISO-B)

When 그림입니다.
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원본 그림의 크기: 가로 740pixel, 세로 87pixel and 그림입니다.
원본 그림의 이름: CLP000007d00030.bmp
원본 그림의 크기: 가로 717pixel, 세로 86pixel, the battery is isolated from the BPDCMG. Under this condition, the proposed converter operates as a bidirectional buck-boost converter and transfers power from bus ‘I’ to bus ‘J’. The states of this mode are defined as follows (see Fig. 7):


Fig. 7. States of mode 5, assuming I=1: (a) State I; (b) State II.

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원본 그림의 이름: CLP000007d0002d.bmp
원본 그림의 크기: 가로 1545pixel, 세로 646pixel

(a)

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원본 그림의 이름: CLP000007d0002e.bmp
원본 그림의 크기: 가로 1530pixel, 세로 665pixel

(b)


State I: SI2 and SI3 are turned ON. Therefore, the magnetizing inductor current through the transformer increases linearly.

State II: When SI3 is turned OFF, the transformer magnetizing inductor current continues to discharge through SI2, DI1, DJ3 and Dm on the load RJ.


F. Mode 6: Single Input Single Output-Discharging of the Battery (SISO-D):

When 그림입니다.
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원본 그림의 크기: 가로 636pixel, 세로 78pixel, 그림입니다.
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원본 그림의 크기: 가로 638pixel, 세로 74pixel

and 그림입니다.
원본 그림의 이름: CLP000007d00035.bmp
원본 그림의 크기: 가로 401pixel, 세로 76pixel, the proposed converter starts to compensate the bus ‘J’ voltage through discharging the battery (under the assumption that the battery can supply that amount of required power). The operation states of this mode are defined as follows (see Fig. 8):


Fig. 8. States of mode 6, assuming I=1: (a) State I; (b) State II.

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원본 그림의 이름: CLP000007d00031.bmp
원본 그림의 크기: 가로 1522pixel, 세로 680pixel

(a)

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원본 그림의 이름: CLP000007d00032.bmp
원본 그림의 크기: 가로 1520pixel, 세로 700pixel

(b)


State I: SJ1 and Sp2 are turned ON. The transformer magnetizing inductor current increases linearly through the battery.

State II: When SP2 is turned OFF, the transformer magnetizing inductor current continues to discharge through SJ1, DJ2 and DJ3.


G. Mode 7: Single Input Dual Output-Discharging of the Battery (SIDO discharge):

When 그림입니다.
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원본 그림의 크기: 가로 759pixel, 세로 80pixel and 그림입니다.
원본 그림의 이름: CLP000007d00037.bmp
원본 그림의 크기: 가로 403pixel, 세로 73pixel, to balance the upper and lower terminal voltages, the battery discharges through the buses according to the load requirements, independently. The operation states of this mode are defined as follows (see Fig. 9):


Fig. 9. States of mode 7: (a) State I; (b) State II.

그림입니다.
원본 그림의 이름: CLP000007d00038.bmp
원본 그림의 크기: 가로 1503pixel, 세로 711pixel

(a)

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원본 그림의 이름: CLP000007d00039.bmp
원본 그림의 크기: 가로 1534pixel, 세로 693pixel

(b)


State I: SP2, S12 and S21 are ON. Therefore, Lm absorbs energy form VBat. C1 and C2 are discharged through R1 and R2.

State II: S12 and S22 stay ON and the absorbed energy is sent to R1 and R2 by the transformer.



Ⅲ. AVERAGE SMALL-SIGNAL MODEL OF THE PROPOSED CONVERTER

Fig. 10 shows a control block diagram of the proposed converter. To adjust the transient response and to meet the small steady-state error, the duty cycle to the output voltage small-signal transfer function is acquired using the average state-space method.


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원본 그림의 크기: 가로 1753pixel, 세로 757pixel

Fig. 10. Control block diagram of the proposed converter.


This transfer function is employed to obtain the frequency response of the proposed converter system. A current and voltage controller is used to improve the dynamic and steady- state behavior of the system. These equations are written for power transmission from the battery to R1. Therefore, the state-space equations for the two states of mode 6 are derived and averaged over one switching cycle. The state variables are the voltages of the C1 (V1), and the inductor current (iLm). The input vector is the source voltage, which in this mode is the battery voltage (Vb).

In reference to Fig. 8(a), the state-space equation obtained from the equivalent circuit of the shoot-through state is:

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원본 그림의 이름: CLP000007d0003a.bmp
원본 그림의 크기: 가로 433pixel, 세로 153pixel              (2)

Where:

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원본 그림의 크기: 가로 686pixel, 세로 70pixel

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원본 그림의 이름: CLP000007d0003c.bmp
원본 그림의 크기: 가로 728pixel, 세로 231pixel

In addition, the state-space equation in the non-shoot- through state (Fig. 8(b)) is:

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원본 그림의 이름: CLP000007d0003e.bmp
원본 그림의 크기: 가로 425pixel, 세로 158pixel              (3)

Where:

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원본 그림의 크기: 가로 927pixel, 세로 301pixel

Averaging the state-space equations (2) and (3) over one switching cycle leads to:

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원본 그림의 이름: CLP000007d00040.bmp
원본 그림의 크기: 가로 529pixel, 세로 143pixel              (4)

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원본 그림의 이름: CLP000007d00041.bmp
원본 그림의 크기: 가로 645pixel, 세로 82pixel          (5)

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원본 그림의 이름: CLP000007d00042.bmp
원본 그림의 크기: 가로 640pixel, 세로 82pixel          (6)

To deduce the small-signal model of the proposed converter, (6) are perturbed (denoted by hat) around their steady-state values (denoted by capital) and the system is linearized. The small ac variations are 그림입니다.
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원본 그림의 크기: 가로 49pixel, 세로 68pixel,그림입니다.
원본 그림의 이름: CLP000015e40002.bmp
원본 그림의 크기: 가로 48pixel, 세로 71pixel, and 그림입니다.
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원본 그림의 이름: CLP000007d00043.bmp
원본 그림의 크기: 가로 1167pixel, 세로 185pixel         (7)

Where 그림입니다.
원본 그림의 이름: CLP000007d00044.bmp
원본 그림의 크기: 가로 269pixel, 세로 72pixel. Therefore, the transfer function in the s-domain is represented by:

그림입니다.
원본 그림의 이름: CLP000007d00045.bmp
원본 그림의 크기: 가로 1375pixel, 세로 135pixel          (8)

Since in the proposed converter, the number of turns of the transformer in each winding is equal, the transfer function of the output voltage (y) versus the inductance current 그림입니다.
원본 그림의 이름: CLP000007d00046.bmp
원본 그림의 크기: 가로 94pixel, 세로 68pixel, 그림입니다.
원본 그림의 이름: CLP000007d00047.bmp
원본 그림의 크기: 가로 139pixel, 세로 67pixel and the inductance current 그림입니다.
원본 그림의 이름: CLP000007d00046.bmp
원본 그림의 크기: 가로 94pixel, 세로 68pixel versus the duty cycle (d), 그림입니다.
원본 그림의 이름: CLP000007d00048.bmp
원본 그림의 크기: 가로 146pixel, 세로 75pixel by the substituting the parameters shown in Table I are obtained as (9) and (10).

그림입니다.
원본 그림의 이름: CLP000007d00049.bmp
원본 그림의 크기: 가로 782pixel, 세로 168pixel      (9)

그림입니다.
원본 그림의 이름: CLP000007d0004a.bmp
원본 그림의 크기: 가로 895pixel, 세로 170pixel           (10)


TABLE I SYSTEM PARAMETER VALUES

Parameter

Value

Inductor Lm

2.5 mH

Capacitor C1 and C2

200 μF

Duty cycle D

0.5

Load Rload

200 Ω

Transformer winding turns NP=Ns1=Ns2

1

Battery 

2000 Ah, 400 V

Reference voltage (Vref)

400 V

Maximum voltage (Vmax)

408 V

Minimum voltage (Vmin)

392 V

Maximum-allowed voltage (Vmax-allowed)

404 V

Minimum-allowed voltage (Vmin-allowed)

396 V

Inductor current upper limit (iMAX)

10 A

Duty cycle upper limit (DMAX)

0.8


In Fig. 12, the reference voltage is obtained by the droop control. In order to reduce the steady state error and to improve the overall stability of the system, an appropriate closed-loop controller is designed so that the controller provides a sufficient phase margin and bandwidth. Therefore, the transfer function of the voltage control system (Gcv(s)) and current control system (Gcc(s)) in Fig. 10 are represented by (11) and (12).

그림입니다.
원본 그림의 이름: CLP000015e40004.bmp
원본 그림의 크기: 가로 993pixel, 세로 181pixel       (11)

그림입니다.
원본 그림의 이름: CLP000007d0004e.bmp
원본 그림의 크기: 가로 641pixel, 세로 142pixel   (12)


그림입니다.
원본 그림의 이름: CLP000007d0004b.bmp
원본 그림의 크기: 가로 1131pixel, 세로 537pixel

Fig. 11. Bumpless transfer that switches smoothly between two control systems.


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원본 그림의 이름: CLP000007d0004c.bmp
원본 그림의 크기: 가로 1439pixel, 세로 934pixel

Fig. 12. Bode diagram of plant transfer functions with and without compensation.


Due to the same numbers of the proposed converter transformer in the primary, secondary and tertiary, this method is similar in the other modes of power transfer to load.

In order to avoid the kicks in the control signal caused by setpoint changes from the voltage control and battery charge control strategy, a bumpless transfer has been used. Using the model introduced in [28] and [29], as shown in Fig. 11, bumpless transfer is achieved by adding (Iref,i – I’ref,i) to the integral coefficient term of Gcv(s). Where I’ref,i is the output value of the voltage control block, the index i represents the bus number and Kt is a constant coefficient that is related to the reverse of the reset time.

With the parameters mentioned above, a Bode diagram of the open-loop and closed-loop control system is shown in Fig. 12. By analyzing the amplitude-frequency characteristic and phase-frequency response curves in the Bode diagram, it can be seen that the designed controller provides a good stability margin for the system.



Ⅳ. SIMULATION RESULTS

In order to verify performance of the proposed converter, computer simulations studies were carried out in Matlab- Simulink software. The parameters of proposed converter are listed in Table I.

It is assumed that, RES1 and RES2 are able to product a maximum power of 2kW. Simulation waveforms of the voltages (V1, V2 and Vbat), the inductor current (iL) and the converter modes under different load currents are shown in Fig. 13. As analyzed previously, these simulations were carried out in seven different operational modes.


Fig. 13. Simulation results: (a) Modes; (b) Inductor current; (c) Voltage of the battery; (d) Output voltage of the negative and positive terminals; (e) Load currents.

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원본 그림의 이름: image19.jpeg
원본 그림의 크기: 가로 645pixel, 세로 381pixel

(a)

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원본 그림의 이름: image20.jpeg
원본 그림의 크기: 가로 644pixel, 세로 381pixel

(b)

그림입니다.
원본 그림의 이름: image21.jpeg
원본 그림의 크기: 가로 645pixel, 세로 381pixel

(c)

그림입니다.
원본 그림의 이름: image22.jpeg
원본 그림의 크기: 가로 645pixel, 세로 381pixel

(d)

그림입니다.
원본 그림의 이름: image23.jpeg
원본 그림의 크기: 가로 652pixel, 세로 381pixel

(e)


A. 0~0.01: DISO-C Mode

During 0~0.01, the load currents connected to the upper and lower terminals are 400 Ω. As a result, the RESs inject a constant current to support the local loads while the extra generated power is used to charge the battery. In this scenario, the RESs have the ability to continuously charge the battery. Therefore, V1 and V2 stay between Vmax and Vmax-allowed. As a result, the converter operates in mode 2.


B. 0.01~0.02: SISO-C Mode

When reducing R2 to 80Ω, the value of V2 decreases and stays between Vmin-allowed and Vmax-allowed. Therefore, the system changes to mode 3. In this mode, the redundant power transferred from the positive terminal charges the battery. Because RES1 does not have the ability to continuously charge the battery, V1 is decreased. After V1 reaches Vmax-allowed, the converter changes to mode 1. At this time, the converter does not work and iL become zero. Then V1 begins to increase during a burst-mode switching period, where the positive terminal voltage satisfies the condition of V1 < Vmax-allowed. After that, when V1 reaches Vmax-allowed again, the converter operates in mode 3.


C. 0.02~0.03: SIDO-C Mode

With a further reduction in R2 (R2 = 57Ω), the value of V2 decreases and stays between Vmin-allowed and Vmax-allowed, while the value of V1 stays between Vmax and Vmax-allowed. In this condition, the redundant power of the positive bus is transferred to charge the battery and to regulate the negative bus voltage. Similar to mode 3, the operational mode changes to mode 1 during the burst mode switching period.


D. 0.03~0.04: SISO-B Mode

When the reduction of R2 continues to 40Ω (R1 stays at 400Ω), the redundant power-generated potential of the RES1 is enough to supply the R1 and R2 load demand. In this condition, the proposed converter changes to mode 5. Therefore, the upper bus only compensates the voltage of the negative bus. Then, V2 begins to increase to the allowed voltage lower limit (Vmin-allowed). After that, the operation mode changes to mode 1 until V2 is reached Vmin again.


E. 0.04~0.05: SISO-D Mode

When R1 is reduced to 80 (R2 stays at 40), the value of V1 decreases and stays between Vmin-allowed and Vref. Therefore, the proposed converter starts to compensate the negative bus voltage through discharging the battery. In this condition, the proposed converter operates in mode 6. Similar to the previous conditions, the operational mode changes to mode 1 during the burst mode switching period.


F. 0.05~0.06: SIDO-D Mode

With a greater reduction in R1 (R1=40Ω, R2=40Ω), both of the bus voltages stay between Vmin and Vmin-allowed. Therefore, the battery discharges on both buses to increase the voltages V1 and V2. Finally, these voltages come back to the allowed values during the droop control. Then, V1 and V2 begin to increase to the allowed voltage lower limit (Vmin-allowed). Similar to the previous conditions, the operational mode changes to mode 1.


G. 0.06~0.07: NBM Mode

When R1 = 80Ω, R2 = 80Ω, the voltages V1 and V2 naturally tend to stay balanced without control. Eventually they stay equal. Since V1 and V2 stay between Vmin-allowed and Vmax-allowed, the balancer does not operate and changes to mode 1. In this mode, the inductor current is constantly zero.



Ⅴ. EXPERIMENTAL RESULTS

In order to verify the proposed converter, a low voltage and low power (24V-50W) experimental setup of the proposed converter, shown in Fig. 14, is designed and implemented. The experimental testbench includes two 24V DC input voltage sources with a maximum current of 2A, the proposed three-port multidirectional converter, two cascaded VRLA 12V batteries and loads. The converter parameters are listed in Table II.


그림입니다.
원본 그림의 이름: CLP000007d0004f.bmp
원본 그림의 크기: 가로 578pixel, 세로 882pixel

Fig. 14. Photograph of the proposed converter prototype.


TABLE II MAIN PARAMETERS OF THE EXPERIMENTAL SETUP

Parameter

Value

 NP=Ns1=Ns2

15

Transformer wire size

AWG 18

Transformer core size

EE 55

Reference voltage (Vref)

24V

Maximum voltage (Vmax)

26V

Minimum voltage (Vmin)

21V

Maximum-allowed voltage (Vmax-allowed)

25V

Minimum-allowed voltage (Vmin-allowed)

23V

Battery 

12V-100AH

Battery fully charged voltage

13.06 V

Switching Frequency

10kHz

Inductor Lm

0.288 µH

Capacitor C1 and C2

220 μF

Duty cycle upper limit (DMAX)

0.8

Inductor current upper limit (iMAX)

2.5A


When R1 = R2 = 47Ω (loads of less than 2A), the voltage source power generations is more than the load demands in both buses. Therefore, the proposed converter operates in mode 2 and the battery can be charged with the positive and negative buses. Under this condition, the voltages of R1 and R2, the output current of the positive voltage source and the battery charging current are shown in Fig. 15. It should be noted that the current waveform of the negative voltage source has not been shown due to its similarity to the current waveform of the positive voltage source.


그림입니다.
원본 그림의 이름: CLP000007d00050.bmp
원본 그림의 크기: 가로 874pixel, 세로 739pixel

Fig. 15. Voltages of R1 and R2, the output current of the positive voltage source and the battery charging current in mode 2.


By changing R2 to 12Ω, the negative voltage source delivers 2A to R2. At this moment, the maximum possible power is taken from the negative voltage source. Under this condition, the proposed converter operates in mode 3. Therefore, the redundant power transferred from the positive terminal charges the battery. The voltage of R1 and R2 and the current of the positive voltage source are shown in Fig. 16.


그림입니다.
원본 그림의 이름: CLP000007d00051.bmp
원본 그림의 크기: 가로 870pixel, 세로 720pixel

Fig. 16. Voltages of R1 and R2 and the output current of the positive voltage source in mode 3.


When R2=9Ω (load demand of more than 2A) and R1 = 47Ω (load demand of less than 2A), the redundant power of the positive bus has the ability to regulate the negative bus voltage and to charge the battery. Under this condition, the system operates in mode 4. Fig. 17 shows the R1 and R2 voltages, the output current of the positive voltage source and the current of R2 before and after compensation. From Fig. 17, it can be seen that LVUR is reduced from 35.8% (before compensation) to 6.6% (after compensation).

When the reduction of R2 continues to 7.2Ω (R1 stays at 47Ω), the power-generation potential of the positive voltage source is more than the R1 load demand. Under this condition, the proposed converter operates in mode 5. The upper bus only considers compensating the voltage of the negative bus. Fig. 18 shows the R1 and R2 voltages, the output current of the positive voltage source and the current of R2 before and after compensation. Under this condition LVUR is reduced from 54.3% (before compensation) to 13.4% (after compensation).


그림입니다.
원본 그림의 이름: CLP000007d00052.bmp
원본 그림의 크기: 가로 899pixel, 세로 739pixel

Fig. 17. Voltages of R1 and R2, the output current of the positive voltage source and the current of R2 in mode 4.


그림입니다.
원본 그림의 이름: CLP000007d00053.bmp
원본 그림의 크기: 가로 918pixel, 세로 772pixel

Fig. 18. Voltages of R1 and R2, the output current of the positive voltage source and the current of R2 in mode 5.


With a decrease in R1 (R1 = 11.75Ω, R2 = 7.2Ω), the voltage sources generations are no longer enough to supply the loads. Therefore, the proposed converter operates in mode 6 and the battery can participate to compensate the lower bus voltage. In this mode, the battery compensates the lower bus voltage. The voltage of R1 and R2, the current of the battery and the current of R2 before and after compensation are shown in Fig. 19.


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원본 그림의 이름: CLP000007d00055.bmp
원본 그림의 크기: 가로 976pixel, 세로 809pixel

Fig. 19. Voltages of R1 and R2, the current of R2 and the battery discharging current in mode 6.


When, R1 and R2 are 8.2Ω, the amount of power generated by the voltage sources in order to provide the available loads is not enough. In this case, the battery compensates the positive and negative bus voltages through the proposed converter. The voltage of R1 and R2, the current of the battery and the current of R2 before and after compensation are shown in Fig. 20.


그림입니다.
원본 그림의 이름: CLP000007d00056.bmp
원본 그림의 크기: 가로 963pixel, 세로 807pixel

Fig. 20. Voltages of R1 and R2 and the battery discharging current in mode 7.


The conversion efficiencies of representative operation modes are shown in Fig. 21. The duty cycle is adjusted to meet different load current levels, and the input voltages are kept the same during the measurements. Although the converter has many switches, since some of the switches always remain in the ON state during the switching time, the conduction loss is small and the proposed converter can still achieve a high conversion rate. The efficiencies of the proposed converter are in the range of 76.1%-90.2%, which verifies the good performances of the proposed converter in different operation states. The blue line depicts the power transfer efficiency from the DC bus to the battery which is the efficiency curve of battery charging/discharging modes (mode 2, mode 3, mode 6 and mode 7). The red line depicted the power transfer efficiency from one DC bus to the other DC bus (mode 5). Since the efficiency curve of mode 4 can be represented by a combination of the two curves, this curve can be placed between the two curves, depending on the amount of current being shared between the battery and the other DC bus.


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원본 그림의 이름: CLP000007d00057.bmp
원본 그림의 크기: 가로 1057pixel, 세로 640pixel

Fig. 21. Conversion efficiencies of the DC bus to battery and DC bus to DC bus modes.



Ⅵ. CONCLUSION

In this paper, a new three-port multidirectional converter with a burst-time control scheme has been proposed for bipolar DC microgrids. The structure of the proposed three-port multidirectional converter mitigated the bus voltage unbalancing and enhanced the system efficiency thanks to the fact that it can be used instead of several converters due to its multi-mode operation. A small-signal model was developed to study its stability and to design the outer voltage and inner current controller. The operation principles of the proposed converter were presented in seven modes. Finally, simulation and experimental results verified that the proposed converter has the ability to balance bus voltages with unbalanced loads.



REFERENCES

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[11] P. Prajof and V. Agarwal, “Novel boost-SEPIC type interleaved DC-DC converter for low-voltage bipolar dc microgrid-tied solar pv applications,” in 2015 IEEE 42nd Photovoltaic Specialist Conference, PVSC 2015, 2015.

[12] M. Ferrera, S. Litrán, E. Durán, and J. Andújar, “A SEPIC- Cuk converter combination for bipolar DC microgrid applications,” in Industrial Technology (ICIT), 2015 IEEE International Conference on, pp. 884-889, 2015.

[13] S. D. Tavakoli, G. Kadkhodaei, M. Mahdavyfakhr, M. Hamzeh, and K. Sheshyekani, “Interlinking converters in application of bipolar dc microgrids,” in Power Electronics, Drive Systems & Technologies Conference (PEDSTC), 2017 8th, pp. 37-42, 2017.

[14] J. Ma, M. Zhu, Q. Li, and X. Cai, “From voltage balancer to interlinking converter; A shift of operation concept for distributed bipolar DC system,” in IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, pp. 1166-1171, 2017.

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[21] F. Nejabatkhah, S. Danyali, S. H. Hosseini, M. Sabahi, and S. M. Niapour, “Modeling and control of a new three-input DC-DC boost converter for hybrid pv/fc/battery power system,” IEEE Trans. Power Electron., Vol. 27, No. 5, pp. 2309-2324, May 2012.

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[23] M. Dongsheng, K. Wing-Hung, T. Chi-Ying, and P. K. T. Mok, “Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode,” IEEE J. Solid-State Circuits, Vol. 38, No. 1, pp. 89-100, Jan. 2003.

[24] Y. Hu, W. Xiao, W. Cao, B. Ji, and D. J. Morrow, “Three-port DC-DC converter for stand-alone photovoltaic systems,” IEEE Trans. Power Electron., Vol. 30, No. 6, pp. 3068-3076, Jun. 2015.

[25] J. Dong, G. Chen, Y. Deng, K. Wang, and X. He, “A family of integrated dual-output DC-DC converters: Synthesis methodology and performance analysis,” in 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), pp. 342-347, 2016.

[26] C. Liu, D. Zhu, J. Zhang, H. Liu, and G. Cai, “A Bidirectional dual buck-boost voltage balancer with direct coupling based on a burst-mode control scheme for low- voltage bipolar-type DC microgrids,” J. Power Electron., Vol. 15, No. 6, pp. 1609-1618, Nov. 2015.

[27] M. Evzelman and R. Zane, “Burst mode control and switched-capacitor converters losses,” in Applied Power Electronics Conference and Exposition (APEC), 2016 IEEE, pp. 1603-1607, 2016.

[28] G. Herbst, “Practical active disturbance rejection control: Bumpless transfer, rate limitation, and incremental algorithm,” IEEE Trans. Ind. Electron., Vol. 63, No. 3, pp. 1754-1762, Mar. 2016.

[29] K. J. Astrom, Control System Design, 2002.



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원본 그림의 이름: image32.jpg
원본 그림의 크기: 가로 151pixel, 세로 216pixel

Taha Ahmadi was born in Tehran, Iran, in 1987. He received his B.S. degree in Electrical Engineering from the Shahrood University of Technology, Shahrud, Iran, in 2010; and his M.S. degree in Electrical Engineering from Mazandaran University, Babolsar, Iran, in 2012. He is presently working towards his Ph.D. degree in Electrical Engineering at Lorestan University, Khoramabad, Iran. His current research interests include distribution generation, microgrid control and the application of power electronics in power distribution systems.


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원본 그림의 이름: image34.png
원본 그림의 크기: 가로 157pixel, 세로 194pixel

Esmaeel Rokrok was born in Khoramabad, Iran, in 1972. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 1985, 1997 and 2010, respectively. He is presently working as an Assistant Professor in the Department of Electrical Engineering, Lorestan University, Khoramabad, Iran. His current research interests include power system control and dynamics, dispersed generation, microgrids, power electronics and robust control.


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원본 그림의 이름: image33.png
원본 그림의 크기: 가로 166pixel, 세로 216pixel

Mohsen Hamzeh received his B.S. and M.S. degrees in Electrical Engineering from the University of Tehran, Tehran, Iran, in 2006 and 2008, respectively. He received his Ph.D. degree in Electrical Engineering from the Sharif University of Technology, Tehran, Iran, in 2012. Since 2010, he has been a Senior Research Engineer with SGP Company, Tehran, Iran. He joined the Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran, in 2013, where he is presently working as an Assistant Professor. His current research interests include renewable energies, microgrid control and the application of power electronics in power distribution systems.