사각형입니다.

https://doi.org/10.6113/JPE.2018.18.5.1303

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



H-type Structural Boost Three-Level DC-DC Converter with Wide Voltage-Gain Range for Fuel Cell Applications


Huakun Bi*, Ping Wang*, and Yanbo Che


†,*School of Electrical and Information Engineering, Tianjin University, Tianjin, China



Abstract

To match the dynamic lower voltage of a fuel cell stack and the required constant higher voltage (400V) of a DC bus, an H-type structural Boost three-level DC-DC converter with a wide voltage-gain range (HS-BTL) is presented in this paper. When compared with the traditional flying-capacitor Boost three-level DC-DC converter, the proposed converter can obtain a higher voltage-gain and does not require a complicate control for the flying-capacitor voltage balance. Moreover, the proposed converter, which can draw a continuous and low-rippled current from an input source, has the advantages of a wide voltage-gain range and low voltage stress for power semiconductors. The operating principle, parameters design and a comparison with other converters are presented and analyzed. Experimental results are also given to verify the aforementioned characteristics and theoretical analysis. The proposed converter is suitable for application of fuel cell systems.


Key words: Boost three-level DC-DC converter, Fuel cell systems, H-type structural, Voltage stress, Wide voltage-gain range


Manuscript received Apr. 20, 2018; accepted Jul. 15, 2018

Recommended for publication by Associate Editor Chun-An Cheng.

Corresponding Author: ybche@163.com Tel: +86-13820672692, Tianjin University

*School of Electrical and Information Eng., Tianjin University, China



Ⅰ. INTRODUCTION

With the shortage of global energy and movements for environmental protection, clean energy sources such as fuel cells are becoming increasingly important worldwide [1]. Due to their low output voltage, high output current [2] and soft output characteristic [3], fuel cells need a step-up DC-DC converter with a wide range of voltage-gain to interface with a DC bus. In addition, ripples in input current of a converter must be low enough to extend the service life of a fuel cell [4]. In [5], a Nexa proton-exchange membrane (PEM) power module was used to demonstrate a wide range of changes in the fuel cell output voltage by theoretical calculations and experiments. Fig. 1 shows the relationship between the fuel cell output current IF and the output voltage VF. It can be seen that the output voltage VF of a fuel cell decreases rapidly with an increase of the output current IF. However, this characteristic is not beneficial for fuel cell systems unless the wide output voltage range of the fuel cell source can be converted by a wide input-voltage range boost DC–DC converter, obtaining a fairly constant dc bus voltage. Theoretically, the classical Boost converter can achieve a high voltage-gain as long as the duty cycle is large enough. However, the maximum duty cycle is limited due to parasitic resistances and the consideration of system stability. Nowadays, diodes and switches that are economic, efficient and high- voltage-stressed are still unavailable. Therefore, the voltage gain of the traditional boost converter is limited in practice, and cannot meet practical needs [6]-[9].


그림입니다.
원본 그림의 이름: CLP00000f3c3956.bmp
원본 그림의 크기: 가로 1293pixel, 세로 844pixel

Fig. 1. Fuel cell stack polarization curve.


Some existing isolated converters, such as active-clamp dual boost converters and active-clamp full-bridge boost converters [10], [11], can realize high efficiency and a high voltage-gain. However, their start-up operations must be considered separately. Moreover, the cost is increased for many of the extra power components and isolated sensors or feedback controllers are required. From the viewpoint of system cost savings and improved system efficiency, a non-isolated DC-DC converter is more suitable for renewable or clean energy applications [12], [13].

A lot of the existing non-isolated topologies can achieve a high voltage-gain as stated in [14]. Coupled inductor-based converters can achieve a high voltage-gain [15]-[17]. However, the input current ripple of single-stage single-phase-coupled inductor-based converters is relatively large, which may shorten the service life of the input source [18]. The voltage stress of the power semiconductors in the Boost three-level DC-DC converter in [19] can be reduced by half the output voltage. However, its voltage-gain is limited. In addition, the output and input sides of this converter are connected by a diode, and the voltage potential difference between the two sides contains high frequency PWM signals, which may cause maintenance issues and EMI problems. The output and input sides of the Boost three-level DC-DC converter in [20] share a common ground. However, the voltage-gain of this converter is still limited. In addition, the flying-capacitor voltage requires a complex control to achieve balance. The converter in [21], which applied a switched-inductor structure, can achieve a high voltage-gain. However, a diode in the converter suffers from the high voltage stress. Similarly, high step-up DC-DC converters with switched capacitor have been proposed in [22]-[25], which can provide any voltage gain.

Z-source and quasi-Z-source networks can be applied to DC-DC power converter to protect devices in case of a short circuit [26]. A quasi-Z-source DC-DC converter with the voltage-lift technique has been proposed in [27], where a voltage-lift cell is combined with a quasi-Z-source network. The voltage gain is significantly improved. However, the range of duty cycle decreases. In [28], a common grounded Z source DC-DC converter with a high voltage-gain was presented by changing the connection method of the input source and the load. It is shown in [28] that the voltage stress of power semiconductors is reduced in the range of half of the output voltage to nearly the output voltage, when increasing the duty cycle (voltage-gain). In addition, the current stress of the power switch is several times higher than the output current while increasing the duty cycle. In [29], a Z-source DC-DC converter with a cascaded switched-capacitor was presented, where the voltage-gain can be improved by using the voltage multiplier function of the switched-capacitor. However, EMI problems can be increased since the input current is discontinuous, and the input voltage source side and the load side are not common grounded. Additional safety issues can also be induced. In [30], the advantages of a Boost three-level DC-DC converter with a diode rectification quasi-Z source are reflected in the lower voltage stress for the power semiconductors and the fact that the voltage of the flying-capacitor can be well clamped at half of the output voltage in both the static and dynamic states. However, it has disadvantages such as its narrow duty cycle range. In addition, the volume and weight of the aforementioned converter are increased for the Z-source or quasi-Z-source networks. Furthermore, it requires two or more inductors and capacitors.

The DC-DC converters just described could not provide a low input current ripple, a high voltage-gain, a low voltage stress of the power semiconductors and a simple control at the same time. In this paper, a H-type structural Boost three- level DC-DC converter with a wide voltage-gain range is proposed as a solution. This converter can reduce the voltage stresses of all the semiconductors to half of output voltage. In addition, it operates well with a high voltage-gain and a proper duty cycle (0<d<0.5). The output-input potential difference of this converter is a constant capacitor voltage rather than a high frequency PWM voltage. In addition, the equivalent frequency of the inductor current in this topology is double the switching frequency, with switches that are driven by two gate signals phase-shifted by 180°. These features are beneficial for improving efficiency and reducing the input current ripple.

This paper is organized as follows. In Section II, the topology of the HS-BTL for renewable and clean energy sources is presented and the operation principles of the converter topology are discussed. In Section III, the parameters for all of the components are designed, and a comparison with other converters is analyzed. Then experimental results obtained from a prototype are analyzed in Section IV. Finally, some conclusions are presented in Section V.



Ⅱ. OPERATING PRINCIPLES OF THE PROPOSED CONVERTER


A. Configuration of the Proposed Converter

The configuration of the proposed converter is depicted in Fig. 2. With a simple structure, the proposed converter consists of an H-type structural (Q1, Q2, C1, D1 and D2), an inductor L, two diodes D3 and D4, and two filter capacitors C2 and C3. The H-type structure is adopted at the input voltage side to reduce the input current ripple, to avoid the narrow pulse of PWM voltage waveforms, and to decrease the conduction losses of the power switches. The two filter capacitors at the output side are connected in series to obtain a high voltage-gain and to decrease the voltage stress for all of the power semiconductors and capacitors.


그림입니다.
원본 그림의 이름: CLP00000f3c0001.bmp
원본 그림의 크기: 가로 1245pixel, 세로 829pixel

Fig. 2. Configuration of the proposed converter.


To simplify the analysis, the following assumptions are made.

1) All of the components are ideal.

2) The capacitors in the converter are large enough so that their voltages are approximately constant, and C1=C2=C3.

3) The current of L changes linearly.


B. Operating Principles

The operating principles of the proposed converter are analyzed when the input current is continuous. In this case, suppose that d1=d2=d, where d1 and d2 are the duty cycles of Q1 and Q2, respectively. In addition, the phase difference between their gate driving signals is 180°. According to the operation of Q1 and Q2, there are four switching states "S1S2"= {00, 01, 10, 11}, where "1" means that the power switch Q1 or Q2 is "ON", and "0" means that it is "OFF". It can be seen from Fig. 2 that either Q1 or Q2 is on for 0.5≤d<1. Therefore, the inductor L is always being charged. As a result, the duty cycle of this converter is limited to the range of 0<d<0.5. Thus, during one switching period, the converter has three switching states, and their sequence is "10-00-01- 00-10". Main waveforms of the proposed converter are shown in Fig. 3, while the energy flow paths in each of the switching states of the converter are shown in Fig. 4.


그림입니다.
원본 그림의 이름: CLP00000f3c0004.bmp
원본 그림의 크기: 가로 658pixel, 세로 836pixel

Fig. 3. Main waveforms of the proposed converter.


Fig. 4. Energy flow paths in each switching state: (a) S1S2=10, (b) S1S2=00, (c) S1S2=01.

그림입니다.
원본 그림의 이름: CLP00000f3c0007.bmp
원본 그림의 크기: 가로 1302pixel, 세로 862pixel

(a)

그림입니다.
원본 그림의 이름: CLP00000f3c0009.bmp
원본 그림의 크기: 가로 1316pixel, 세로 867pixel

(b)

그림입니다.
원본 그림의 이름: CLP00000f3c000a.bmp
원본 그림의 크기: 가로 1282pixel, 세로 871pixel

(c)


When S1S2=10, as shown in Fig. 4(a), S1 is in the ON state and S2 is in the OFF state. The diodes D2 and D3 are directly polarized, while D1 and D4 are inversely polarized. The inductor L is charged with a linearly rising current iL from the input source. The capacitor C2 is charged by C1. The load is supplied by C1 and the output capacitor C3. The switching state 10 refers to an operating stage.

The following equations can be derived in state 10:

그림입니다.
원본 그림의 이름: CLP00000f3c0002.bmp
원본 그림의 크기: 가로 694pixel, 세로 510pixel                  (1)

그림입니다.
원본 그림의 이름: CLP00000f3c0003.bmp
원본 그림의 크기: 가로 568pixel, 세로 208pixel                      (2)

where Uin is the input voltage, uLa and iLa are the voltage and current of the inductor, and uC1a, uC2a and uC3a are the voltages over C1, C2 and C3. In addition, uoa is the output voltage and R is the load resistor. The subscript ‘a’ indicates a variable in state 10.

When S1S2=00, as shown in Fig. 4(b), both of the switches S1 and S2 are OFF. The diodes D1, D2 and D3 are directly polarized, while D4 is inversely polarized. The current of the inductor decrease linearly, C1 is charged from L, and the load is supplied by L and C3. The switching state 00 refers to an operating stage.

The following equations can be derived in state 00:

그림입니다.
원본 그림의 이름: CLP00000f3c0005.bmp
원본 그림의 크기: 가로 748pixel, 세로 524pixel          (3)

그림입니다.
원본 그림의 이름: CLP00000f3c0006.bmp
원본 그림의 크기: 가로 566pixel, 세로 210pixel                        (4)

where Uin is the input voltage, uLb and iLb are voltage and current of the inductor, and uC1b, uC2b and uC3b are the voltages over C1, C2 and C3. In addition, uob is the output voltage and R is the load resistor. The subscript ‘b’ indicates a variable in state 00.

When S1S2=01, as shown in Fig. 4(c), S1 is OFF and S2 is ON. The diodes D1 and D4 are directly polarized, while D2 and D3 are inversely polarized. The inductor L is charged from the input source. The current iL rises linearly. The capacitor C3 is charged from C1. The current of D4 is limited by the parasitic resistance of the converter. The load is supplied by the output capacitor C2. Switching state 01 refers to an operating stage.

The following equations can be derived in state 01:

그림입니다.
원본 그림의 이름: CLP00000f3c000f.bmp
원본 그림의 크기: 가로 730pixel, 세로 513pixel                  (5)

그림입니다.
원본 그림의 이름: CLP00000f3c0010.bmp
원본 그림의 크기: 가로 434pixel, 세로 179pixel                              (6)

where Uin is the input voltage, uLc and iLc are voltage and current of the inductor, and uC1c, uC2c, and uC3c are the voltages over C1, C2 and C3. In addition, uoc is the output voltage and R is the load resistor. The subscript ‘c’ indicates a variable in state 01.


C. Steady-State Analysis

1) Voltage Gain

For the sake of simplicity, the circuit performance of the proposed converter in the CCM will be analyzed with the same assumptions as stated in the previous section. The approximately constant voltages across C1, C2 and C3 are denoted as UC1, UC2 and UC3, and the approximately constant output voltage is denoted as Uo. These constant voltages can be obtained from (2), (4) and (6), as follows:

그림입니다.
원본 그림의 이름: CLP00000f3c0011.bmp
원본 그림의 크기: 가로 694pixel, 세로 195pixel           (7)

then the voltage uLb is:

그림입니다.
원본 그림의 이름: CLP00000f3c0012.bmp
원본 그림의 크기: 가로 477pixel, 세로 170pixel                    (8)

Applying the volt-second balance principle to the inductor L in the CCM yields:

그림입니다.
원본 그림의 이름: CLP00000f3c0013.bmp
원본 그림의 크기: 가로 1242pixel, 세로 145pixel      (9)

From (1), (5), (8) and (9) the following is obtained:

그림입니다.
원본 그림의 이름: CLP00000f3c0014.bmp
원본 그림의 크기: 가로 479pixel, 세로 146pixel   (10)

Thus, the voltage-gain M of the proposed converter can be expressed as:

그림입니다.
원본 그림의 이름: CLP00000f3c0015.bmp
원본 그림의 크기: 가로 352pixel, 세로 156pixel        (11)

where 0<d<0.5. The proposed converter can obtain a high-voltage gain with a small duty cycle, which brings a lot of advantages:

a. If the duty cycle is varied within a wider region of 0 to 1, when a high-step-up voltage gain is required, a larger duty cycle should be used. The use of a larger duty cycle results in high conduction losses on the switches [23]. The proposed converter can obtain a high-voltage gain with a small duty cycle, which decreases the conduction losses on the power switches. During one switching period, the converter has four operating stages, and their switching state sequence is "10-00-01-00". However, during one switching period, all of the power semiconductors just make a connection and break once, which does not increase the switching losses or the reverse recovery losses.

b. The connections and breaks of power semiconductors all need a little time. Thus, the narrow pulse of an ideal PWM voltage waveform is difficult to realize. The proposed converter can obtain a higher voltage gain when the duty cycle is closer to 0.5, resulting in a closer time for all of the power semiconductors to turn on and off. This feature is beneficial for avoiding the narrow pulse of the PWM voltage waveforms when a high voltage gain is achieved.


2) The Average Inductor Current and Inductor Current Ripple

Applying the ampere-second balance principle to the capacitors C1, C2 and C3 in the CCM yields:

그림입니다.
원본 그림의 이름: CLP00000f3c0016.bmp
원본 그림의 크기: 가로 1124pixel, 세로 893pixel        (12)

From (1), (3), (5) and (12), the average inductor current IL is given by:

그림입니다.
원본 그림의 이름: CLP00000f3c0017.bmp
원본 그림의 크기: 가로 440pixel, 세로 155pixel       (13)

In state 10, the inductor current increase linearly. Therefore:

그림입니다.
원본 그림의 이름: CLP00000f3c0018.bmp
원본 그림의 크기: 가로 1103pixel, 세로 468pixel        (14)

where f is the switching frequency and iL is the inductor current ripple.

From (13) and (14), the current ripple ratio r of the inductor can be obtained as:

그림입니다.
원본 그림의 이름: CLP00000f3c0019.bmp
원본 그림의 크기: 가로 662pixel, 세로 182pixel              (15)

The current ripple ratio of the classical Boost converter is:

그림입니다.
원본 그림의 이름: CLP00000f3c001a.bmp
원본 그림의 크기: 가로 502pixel, 세로 179pixel   (16)

where 그림입니다.
원본 그림의 이름: CLP00001d1c3f03.bmp
원본 그림의 크기: 가로 65pixel, 세로 53pixel is the duty cycle of the converter.

If the proposed converter and the classical Boost converter have the same output power, inductor and switching frequency, it can be obtained that:

그림입니다.
원본 그림의 이름: CLP00000f3c001b.bmp
원본 그림의 크기: 가로 342pixel, 세로 147pixel         (17)

It can be seen from Fig. 5 that inductor current ripple ratio in the proposed converter is lower than that in the classical Boost converter, which means a lower input current ripple.


그림입니다.
원본 그림의 이름: CLP00000f3c001c.bmp
원본 그림의 크기: 가로 1541pixel, 세로 881pixel

Fig. 5. Ratio of the inductor current ripple ratio versus the wider voltage-gain range from 5 to 16.


3) Voltage Stresses on the Semiconductor Components

From Fig. 4, the voltages of the power semiconductors are given by:

그림입니다.
원본 그림의 이름: CLP00000f3c001d.bmp
원본 그림의 크기: 가로 715pixel, 세로 522pixel            (18)

It means that the voltage stress for all of the power semiconductors is only half of the output voltage.


D. Small-Signal Modeling and Voltage Mode Control

When the proposed converter operates in the range of 0<d<0.5, the main power semiconductors Q1 and Q2 have three effective switching states: S1S2= [10, 00, 01]. uin, uo and d are the input variable, the output variable and the control variable, respectively. iL, uC1, uC2 and uC3 are the state variables. When S1S2=10, the converter operates in state 10 (as shown in Fig. 4(a)), and its operating time is d×T. Thus, the state space average model can be obtained as follows:

그림입니다.
원본 그림의 이름: CLP00000f3c001e.bmp
원본 그림의 크기: 가로 1319pixel, 세로 722pixel   (19)

When S1S2=00, the converter is operating in state 00 (as shown in Fig. 4(b)), and its operating time is (1-2d) ×T. The state space average model can be written as:

그림입니다.
원본 그림의 이름: CLP00000f3c001f.bmp
원본 그림의 크기: 가로 1315pixel, 세로 757pixel   (20)

When S1S2=01, the converter operates in state 01 (as shown in Fig. 4(c)), and its operating time is d×T. The state space average model can be achieved as:

그림입니다.
원본 그림의 이름: CLP00000f3c0020.bmp
원본 그림의 크기: 가로 1322pixel, 세로 748pixel   (21)

Combining (19) and (20) with (21), the average model of the converter can be obtained as:

그림입니다.
원본 그림의 이름: CLP00000f3c0021.bmp
원본 그림의 크기: 가로 1376pixel, 세로 772pixel          (22)

The state variables, the input variable, the output variable and the control variable can be described by using the small-signal disturbance variables as:

그림입니다.
원본 그림의 이름: CLP00000f3c0022.bmp
원본 그림의 크기: 가로 536pixel, 세로 598pixel                    (23)

where IL, UCx, Uin, Uo and D are steady state components, 그림입니다.
원본 그림의 이름: CLP00000f3c0023.bmp
원본 그림의 크기: 가로 49pixel, 세로 83pixel, 그림입니다.
원본 그림의 이름: CLP00000f3c0024.bmp
원본 그림의 크기: 가로 86pixel, 세로 71pixel, 그림입니다.
원본 그림의 이름: CLP00000f3c0025.bmp
원본 그림의 크기: 가로 78pixel, 세로 79pixel, 그림입니다.
원본 그림의 이름: CLP00000f3c0026.bmp
원본 그림의 크기: 가로 58pixel, 세로 74pixel and 그림입니다.
원본 그림의 이름: CLP00000f3c0027.bmp
원본 그림의 크기: 가로 58pixel, 세로 83pixel are their corresponding small-signal disturbance variables, and r is the equivalent series resistance for C1. The subscript ‘x’ indicates 1, 2 and 3.

As a result, the small-signal model of the proposed converter is:

그림입니다.
원본 그림의 이름: CLP0000277838b9.bmp
원본 그림의 크기: 가로 1087pixel, 세로 1064pixel           (24)

According to (24) and the experimental parameters in Table II, when the input voltage is Uin=25V, the control- to-output transfer function can be achieved from the time domain to the complex frequency domain as:

그림입니다.
원본 그림의 이름: CLP00000f3c002a.bmp
원본 그림의 크기: 가로 1210pixel, 세로 368pixel       (25)

The small-signal model derived above is helpful for the design of the controller. For a fuel cell power system, the converter must be able to provide a stable output voltage despite a varying input voltage. Therefore, a voltage mode control based on the developed small-signal model is adopted. As shown in Fig. 6, a PI regulator is used to stabilize the output voltage. According to the small-signal model, the parameters of the PI regulator can be determined.


그림입니다.
원본 그림의 이름: CLP00000f3c0028.bmp
원본 그림의 크기: 가로 1559pixel, 세로 656pixel

Fig. 6. Voltage mode control of the proposed converter.



Ⅲ. PARAMETERS DESIGN


A. Parameter Design of an Inductor

As shown in Fig. 7, when the minimum value of the inductor current iLmin is greater than 0, the converter operates in the CCM. When iLmin is equal to 0, the converter operates in the boundary conduction mode (BCM). When iLmin is less than 0, the converter operates in the discontinuous conduction mode (DCM). The converter in this paper is used to interface a fuel cell stack. In order to allow the fuel cell stack to output a continuous current, this converter should operate in the CCM.


그림입니다.
원본 그림의 이름: CLP00000f3c002b.bmp
원본 그림의 크기: 가로 1537pixel, 세로 394pixel

Fig. 7. Converter operating mode.


The inductor current ripple ratio r can be calculated by (26).

그림입니다.
원본 그림의 이름: CLP00000f3c002c.bmp
원본 그림의 크기: 가로 617pixel, 세로 189pixel                (26)

where iLmax is the maximum value of the inductor current. When the converter operates in the BCM, r is equal to 200%.

그림입니다.
원본 그림의 이름: CLP00000f3c002d.bmp
원본 그림의 크기: 가로 1043pixel, 세로 178pixel     (27)

Therefore, when the converter operates in the CCM, r should not be more than 200%. The parameters design of the inductor depends on the permitted inductor current ripple ratio r, the nominal input voltage Uin, the nominal output voltage Uo, the nominal load resistor and the switching frequency f. According to (15), the inductance L can be expressed as:

그림입니다.
원본 그림의 이름: CLP00000f3c002e.bmp
원본 그림의 크기: 가로 502pixel, 세로 170pixel   (28)

When the proposed converter is operated, the input voltage is between 25-70V, the output voltage is 400V, and the output power is 400W. At this time, the corresponding duty ratio d is between 0.325 and 0.4375. According to (28), the value of L is at its maximum when d is 0.325. In other words, when the voltage gain is at its lowest, the inductance of L required by the converter is maximized. As long as the inductor current is still continuous in this case, the converters always operates in the CCM. In this case, the inductance of L is:

그림입니다.
원본 그림의 이름: CLP00000f3c002f.bmp
원본 그림의 크기: 가로 1364pixel, 세로 177pixel          (29)

In order to avoid a large inductor current ripple at a light load of the converter as much as possible, considering a margin, the selected inductor value is 118uH.

At the rated power, according to (15), when the voltage gain is 16, the inductor current ripple ratio r is:

그림입니다.
원본 그림의 이름: CLP00000f3c0030.bmp
원본 그림의 크기: 가로 1171pixel, 세로 173pixel         (30)


B. Parameter Design of Capacitors

Assume that the voltages of C1, C2 and C3 increase or decrease linearly. From (1), (3), (5) and (12) the following is obtained:

그림입니다.
원본 그림의 이름: CLP00000f3c0031.bmp
원본 그림의 크기: 가로 1042pixel, 세로 877pixel     (31)

When the current into the capacitor is positive, the capacitor voltage increases linearly, and vice versa. The capacitance mainly depends on u, which is the permitted fluctuation range of the capacitor voltage. Thus:

그림입니다.
원본 그림의 이름: CLP00000f3c0032.bmp
원본 그림의 크기: 가로 916pixel, 세로 531pixel    (32)

where u1-u3 are the voltage ripples of C1-C3, respectively.

The output voltage ripple uo is affected by the capacitors C2 and C3. Therefore, the output voltage ripple can be expressed as:

그림입니다.
원본 그림의 이름: CLP00000f3c0033.bmp
원본 그림의 크기: 가로 513pixel, 세로 103pixel   (33)

In order to facilitate the later maintenance, capacitors of equal capacitance are selected, that is C1=C2=C3=C. From (31), it can be seen that in switching state 10, the currents flowing through the capacitors C2 and C3 have the same magnitude but opposite directions. The output voltage is almost constant. In switching state 00, the capacitor C2 is neither charged nor discharged, and the capacitor C3 is discharged. The output voltage decreases linearly. In switching state 01, C2 is discharged and C3 is charged. However, the charging speed of C3 is greater than the discharging speed of C2. Therefore, the output voltage increases linearly. The voltage ripples of C2 and C3 and the ripple of the output voltage are shown in Fig. 8. The output voltage ripple can be calculated in switch state 01.

그림입니다.
원본 그림의 이름: CLP00000f3c0034.bmp
원본 그림의 크기: 가로 1092pixel, 세로 173pixel   (34)


그림입니다.
원본 그림의 이름: CLP00000f3c0036.bmp
원본 그림의 크기: 가로 912pixel, 세로 861pixel

Fig. 8. Output voltage ripple of the proposed converter.


Set uo to 0.08V and calculate the capacitance C when the duty cycle d is between 0.325 and 0.4375. The output voltage ripple is at its maximum when d is 0.325. Similarly, the output voltage of the converter is 400V and the load resistance is 400Ω.

그림입니다.
원본 그림의 이름: CLP00000f3c0035.bmp
원본 그림의 크기: 가로 1418pixel, 세로 205pixel        (35)

In order to avoid a large output voltage ripple at a heavy load of the converter, considering a margin, the selected capacitor value is 260uF.

When 260uF capacitors are used, the voltage ripples of C1-C3 can be calculated based on (32) when the duty cycle d is between 0.325 and 0.4375. When d is 0.4375, the voltage ripples of the capacitors C1 and C2 are at their largest, which are ∆u1max and ∆u2max, respectively. When d is 0.325, the voltage ripples of the capacitor C2 and the output voltage are at their largest, which are ∆u3max and ∆uomax, respectively.

그림입니다.
원본 그림의 이름: CLP00000f3c0037.bmp
원본 그림의 크기: 가로 1229pixel, 세로 717pixel      (36)

From (36), it can be seen that when the capacitance of 260uF is selected, the voltage ripples of the capacitors C1-C3 and the output voltage ripple are relatively small. In addition, the largest output voltage ripple is less than the three capacitors largest voltage ripples.


C. Parameter Design of Power Switches and Diodes

For the power switches and diodes, their voltage stresses can be determined by equation (18), and their current stresses (namely the average currents in the ON state) can be deduced according to the energy flow paths among the voltage source, inductor and capacitors during their effective switching states as shown in Fig. 4. Therefore, from (13) and (31), the current stresses on the switches and diodes can be described as:

그림입니다.
원본 그림의 이름: CLP00000f3c0039.bmp
원본 그림의 크기: 가로 604pixel, 세로 891pixel            (37)

where IQ1, IQ2, and ID1-ID4 are the average currents of Q1, Q2 and D1-D4 when they are in the ON state.


D. Comparisons with other Step-Up Solutions

The ideal voltage-gain of A three-level Boost DC-DC converter is limited due to the effects of the parasitic resistance and extreme duty cycles, where the voltage-gain is (1/(1-d)). Although the voltage stresses of the four semiconductors can be reduced by half the output voltage Uo, the flying-capacitor voltage requires a complex control to achieve a proper balance. Comparisons between the proposed and other step-up solutions are drawn and shown in Table I and Fig. 9. When compared with the converters in [27] and [28], the proposed converter has a higher voltage-gain. The voltage stresses of all the semiconductors in [27] are between Uo/2 and Uo, e.g. 0.75Uo, rather than Uo/2. The voltage stresses of all the semiconductors in [28] are also greater than 0.5Uo. The converter in [29] presents a duty cycle limitation, since 0.5≤d<0.75. The static gain variation is highly nonlinear at this operation point, where a relatively small variation in d can results in a large variation of the output voltage, which results in control problems. However, the proposed converter can simultaneously provide high voltage- gain low voltage stresses for the power semiconductors and a simple control, where the voltage-gain is (2/(1-2d)) with modest duty cycles in (0, 0.5), and the voltage stress is 0.5Uo. Moreover, the equivalent frequency of the inductor current in the proposed converter is double the switching frequency, which helps reduce the volumes of the inductor and the series-connected capacitor.


TABLE I COMPARISON WITH OTHER STEP-UP SOLUTIONS

 

Voltage-gain

Voltage stress for power switches

Maximum voltage stress for diodes

Inductors

Frequency

Converter in [27]

2(1-d)/(1-2d)

Uo/2(1-d)

Uo/2(1-d)

2

f

Converter in [28]

(1+d)/(1-2d)

Uo/(1+d)

Uo(2-d)/(1-d)

3

f

Converter in [29]

2/(3-4d)

Uo/2

Uo/2

2

2f

Proposed converter

2/(1-2d)

Uo/2

Uo/2

1

2f


그림입니다.
원본 그림의 이름: CLP00000f3c0038.bmp
원본 그림의 크기: 가로 1417pixel, 세로 872pixel

Fig. 9. Comparisons of voltage gain versus duty cycle for four types of Boost DC-DC converters.



Ⅳ. EXPERIMENTAL RESULTS AND ANALYSES

In order to verify the feasibility of the theoretical analysis, an experimental prototype of the proposed converter has been constructed as shown in Fig. 10. An adjustable DC source with a range of 25V-70V is used to replace the renewable and clean energy sources. The converter voltage loop is implemented by a TMS320F28335 DSP. The PWM gate signals are also generated by the DSP. The load is a resistor. The experiment parameters are shown in Table II.


TABLE II EXPERIMENT PARAMETERS

Parameters

Values

Rated power Pn

400W

Series-connected capacitor C1

260그림입니다.
원본 그림의 이름: CLP00000f3c003a.bmp
원본 그림의 크기: 가로 73pixel, 세로 67pixel

Filtering capacitors C2 and C3

260그림입니다.
원본 그림의 이름: CLP00000f3c003a.bmp
원본 그림의 크기: 가로 73pixel, 세로 67pixel

Inductor L

118그림입니다.
원본 그림의 이름: CLP00000f3c003b.bmp
원본 그림의 크기: 가로 100pixel, 세로 72pixel

Output voltage Uo

400 V

Input voltage Uin

25-70 V

Switching frequency f

20kHz

Power switches Q1-Q2

IXTH 88N30P (300V, 88A)

Diodes D1-D4

DSEC 60-03A (300V, 60A)


그림입니다.
원본 그림의 이름: CLP00000f3c003c.bmp
원본 그림의 크기: 가로 1311pixel, 세로 903pixel

Fig. 10. Experimental prototype of the proposed converter.


With the voltage control loop, the proposed QZSS-BTL converter operates well under an output voltage of Uo =400V and an output power of Po=400W. The output voltage Uo, the PWM voltages of the power switches Q1 and Q2, and the inductor current iL with the input voltages of Uin=25V and Uin=70V are shown in Fig. 11(a) and Fig. 11(b). The inductor L is charged and discharged twice during each switching period. When the instantaneous PWM voltage of Q1 or Q2 is zero (S1S2=01 or S1S2=10), it is charged. When UQ1 and UQ2 stay at Uo/2=200V (S1S2=00), it is discharged. The equivalent switching frequency of the proposed converter is double the real switching frequency f. Therefore, the volumes of the series-connected capacitor and inductor can be reduced by almost half, resulting in a significant reduction in the total volume of the converter. In addition, this feature is beneficial to improve efficiency and to reduce the input current ripple.


Fig. 11. Waveforms of the output voltage and PWM voltages of the power switches Q1 and Q2 and the inductor current: (a) Input voltage Uin=25V and M=16, (b) Input voltage Uin=70V and M=5.71.

그림입니다.
원본 그림의 이름: CLP00000f3c003d.bmp
원본 그림의 크기: 가로 1348pixel, 세로 833pixel

(a)

그림입니다.
원본 그림의 이름: CLP00000f3c003e.bmp
원본 그림의 크기: 가로 1348pixel, 세로 829pixel

(b)


When the converter is operated at the rated power, the PWM voltages of the power switches Q1 and Q2 are shown in Fig. 11, and the PWM voltages for each of the diodes with an input voltage of Uin=25V are shown in Fig. 12. The voltage stresses for each of the power semiconductors are slightly higher than 200V, which is about half the output voltage when the output voltage is 400V. In one switching period, the two power switches have the same duty cycle but a phase difference of 180°. The voltage stresses of the power semiconductors are concluded to be half the output voltage.


Fig. 12. Output voltage and PWM voltages for each of the diodes with an input voltage of Uin=25V: (a) Uo, UD1 and UD2, (b) Uo, UD3 and UD4.

그림입니다.
원본 그림의 이름: CLP00000f3c003f.bmp
원본 그림의 크기: 가로 1452pixel, 세로 851pixel

(a)

그림입니다.
원본 그림의 이름: CLP00000f3c0040.bmp
원본 그림의 크기: 가로 1428pixel, 세로 858pixel

(b)


The differences between the theoretical results and the experimental results are caused by the forward voltage drop of the diodes and the ESR for each of the devices.

Fig. 13 shows voltage waveforms for all of the capacitors in the proposed converter, where the voltages across capacitors C1, C2 and C3 are approximately 200V. This is consistent with the calculated values. It can be seen from Fig. 11-Fig.15 that the ripples of the capacitor voltage and output voltage are very small. This is consistent with the analysis in Section III.


그림입니다.
원본 그림의 이름: CLP00000f3c0041.bmp
원본 그림의 크기: 가로 1423pixel, 세로 877pixel

Fig. 13. Capacitors voltage stresses when Uo=400V.


그림입니다.
원본 그림의 이름: CLP00000f3c0042.bmp
원본 그림의 크기: 가로 1444pixel, 세로 878pixel

Fig. 14. Output voltage and load current.


그림입니다.
원본 그림의 이름: CLP00000f3c0043.bmp
원본 그림의 크기: 가로 1393pixel, 세로 852pixel

Fig. 15. Output voltage and input current with a wide-range changed input voltage from 25V to 70V in the dynamical state.


The output voltage can stay around the reference voltage 400V with the help of a voltage control loop. The output voltage and input voltage in the dynamical state are shown in Fig. 15, where the input voltage changes gradually and widely from 25V to 70V, and the output voltage stays around 400V. As a result, the proposed converter can achieve a wide range of voltage-gain from 5.7 to 16. Correspondingly, the input current (from 17.1A to 5.9A) decreases gradually with a wide-range changed input voltage (from 25V to 70V), as shown in Fig.15. The proposed converter can operate well in a wide voltage gain range (from 5.71 to 16). Correspondingly, the duty cycles are change from 0.325 to 0.4375, which avoid extreme duty cycles.

For the wide input-voltage range operation of the proposed converter, the conversion efficiencies related to the variable input voltages (e.g. 25V, 30V, …, 55V, 60V) and the different output powers (e.g. 300W, 400W, 500W) are measured by a Power Analyzer (Yokogawa-WT3000). Then the relationship between the efficiency, the variable input voltages and the different output powers are illustrated in Fig. 16. It is noticed that the minimum efficiency is 91.80%, while the voltage-gain is 16 and the output power is 500W.

The maximum efficiency is 95.28%, while the voltage-gain is 6.67 and the output power is 500W. In addition, when the output power is constant and the input voltage declines, the efficiency also decreases. This is due to the increasing losses caused by the growing input current.


그림입니다.
원본 그림의 이름: CLP00000f3c0044.bmp
원본 그림의 크기: 가로 1450pixel, 세로 883pixel

Fig. 16. Efficiencies with different output powers when the output voltage is 400V.


The calculated loss distribution for the experiment when Uin=25V and Pn=400W is shown in Fig. 17. The total loss of the converter is 30.06W, 40.91% of which is the turn-on and turn-off (switching) losses and the conduction losses of Q1 and Q2. In addition, 41.57% is made up of the conduction losses for all of the diodes D1-D4 a little more than losses of Q1 and Q2.


그림입니다.
원본 그림의 이름: CLP00000f3c0045.bmp
원본 그림의 크기: 가로 1180pixel, 세로 878pixel

Fig. 17. Calculated loss distribution for the experiment when Uin=25V and Pn=400W.



Ⅴ. CONCLUSION

A HS-BTL converter has been proposed in this paper. It has the advantages of a lower voltage stress (Uo/2) for the power semiconductors and capacitors, a wider range of the voltage-gain with modest duty cycles (0, 0.5) for the power switches, and the ability to avoid the narrow pulse of the PWM voltage waveforms when a high voltage gain is achieved. In addition, only three capacitors and one inductor are used in this converter, and the inductor is charged and discharged twice during each switching period. This results in a low input current ripple and a small size. In order to demonstrate the feasibility of the proposed converter, it was implemented in the laboratory with an output voltage of 400V and input voltages from 25V to 70V. A theoretical analysis and experimental results verified that the proposed DC-DC converter is able to serve as a power interface for fuel cell systems, where a wide voltage-gain range and a low input current ripple are often demanded.



REFERENCES

[1] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, “Novel high step-up dc-dc converter for distributed generation systems,” IEEE Trans. Ind. Electron., Vol. 60, No. 4, pp. 1473-1482, Apr. 2013.

[2] M. Jang and V. G. Agelidis, “A boost-inverter-based, battery-supported, fuel-cell sourced three-phase stand- alone power supply,” IEEE Trans. Power Electron., Vol. 29, No. 12, pp. 6472-6480, Dec. 2014.

[3] J. Xiao,X. Zhang, S. Wen, and D. Wang, “DC-DC converter based on real-time PWM control for a fuel cell system,” Advanced Mechatronic Systems, pp. 561-566, Feb. 2014.

[4] P. Thounthong, P. Sethakul, and B. Davat, “Modified 4-phase interleaved fuel cell converter for high-power high-voltage applications,” Industrial Technology, pp. 1-6, 2009.

[5] Y. A. Zúñiga-Ventura, D. Langarica-Córdoba, J. Leyva- Ramos, L. H. Díaz-Saldierna, and V. M. Ramírez-Rivera, “Adaptive Backstepping Control for a Fuel Cell/Boost Converter System,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 6, No. 2, pp. 686-695, June 2018.

[6] W. Li and X. He, “Review of nonisolated high-step-up dc/dc converters in photovoltaic grid-connected applications,” IEEE Trans. Ind. Electron., Vol. 58, No. 4, pp. 1239-1250, Apr. 2011.

[7] R. J. Wai and R. Y. Duan, “High step-up converter with coupled inductor,” IEEE Trans. Power Electron., Vol. 20, No. 5, pp. 1025-1035, Sep. 2005.

[8] Q. Zhao and F. C. Lee, “High-efficiency, high step-up dc-dc converters,” IEEE Trans. Power Electron., Vol. 18, No. 1, pp. 65-73, Jan. 2003.

[9] A. Ioinovici, Power Electronics and Energy Conversion Systems. Hoboken, NJ, USA: Wiley, 2013.

[10] J. M. Kwon and B. H. Kwon, “High step-up active-clamp converter with input-current doubler and output-voltage doubler for fuel cell power systems,” IEEE Trans. Power Electron., Vol. 24, No. 1, pp. 108-115, Jan. 2009.

[11] L. Zhu, “A novel soft-commutating isolated boost full- bridge ZVS-PWM DC-DC converter for bidirectional high power applications,” IEEE Trans. Power Electron., Vol. 21, No. 2, pp. 422-429, Mar. 2006.

[12] R. J. Wai, W. H. Wang, and C. Y. Lin, “High-performance stand-alone photovoltaic generation system,” IEEE Trans. Ind. Electron., Vol. 55, No. 1, pp. 240-250, Jan. 2008.

[13] R. J. Wai and W. H. Wang, “Grid-connected photovoltaic generation system,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 55, No. 3, pp. 953-964, Apr. 2008.

[14] M. Forouzesh, Y. P. Siwakoti, S. A. Gorji, F. Blaabjerg, and B. Lehman, “Step-Up DC-DC converters: A comprehensive review of voltage boosting techniques, topologies, and applications,” IEEE Trans. Power Electron. Vol. 32, No. 12, pp. 9143-9178, Dec. 2017.

[15] L. S. Yang, T. J. Liang, H. C. Lee, and J. F. Chen, “Novel high step-up DC-DC converter with coupled-inductor and voltage-doubler circuits,” IEEE Trans. Ind. Electron., Vol. 58, No. 9, pp. 4196-4206, Sep. 2011.

[16] S. K. Changchien, T. J. Liang, J. F. Chen, and L. S. Yang, “Novel high step-up DC-DC converter for fuel cell energy conversion system,” IEEE Trans. Ind. Electron., Vol. 57, No. 6, pp. 2007-2017, Jun. 2010.

[17] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, “A novel high step-up DC-DC converter for a microgrid system,” IEEE Trans. Power Electron., Vol. 26, No. 4, pp. 1127-1136, Apr. 2011.

[18] W. Li, X. Xiang, C. Li, W. Li, and X. He, “Interleaved high Step-Up ZVT converter with built-in transformer voltage doubler cell for distributed PV generation system,” IEEE Trans. Ind. Electron., Vol. 28, No. 1, pp. 300-313, Jan. 2013.

[19] X. Ruan, B. Li, and Q. Chen, “Three-level converters-a new approach for high voltage and high power DC-to-DC conversion,” Power Electronics Specialists Conference, Vol. 2, pp. 663-668, Oct. 2002.

[20] A. Ponniran, K. Orikawa, and J. Itoh, “Minimum flying capacitor for N-level capacitor DC/DC boost converter,” International Conference on Power Electronics and Ecce Asia, Jun. 2015.

[21] Y. Tang, D. Fu, T. Wang, and Z. Xu, “Hybrid switched- inductor converters for high step-up conversion,” IEEE Trans. Ind. Electron., Vol. 62, No. 3, pp. 1480-1490, Oct. 2015.

[22] M. Prudente, L. L. Pfitscher, G. Emmendoerfer, E. F. Romaneli, and R. Gules, “Voltage multiplier cells applied to non-isolated converters,” IEEE Trans. Power Electron., Vol. 23, No. 2, pp. 871 -887, Mar. 2008.

[23] M. Nguyen, T. Duong, and Y. C. Lim, “Switched- capacitor-based dual-switch high-boost DC-DC converter,” IEEE Trans. Power Electron., Vol. 23, No. 2, pp. 871-887, Mar. 2017.

[24] G. Wu, X. Ruan, and Z. Ye, “Nonisolated high step-up dc-dc converters adopting switched-capacitor cell,” IEEE Trans. Ind. Electron., Vol. 62, No. 1, pp. 383-393, Jan. 2015.

[25] T. J. Liang, S. M. Chen, L. S. Yang, J. F. Chen, and A. Ioinovici, “Ultra-large gain step-up switched-capacitor dc-dc converter with coupled inductor for alternative sources of energy,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 59, No. 4, pp. 864-874, Apr. 2012.

[26] D. Cao and F. Z. Peng, “A family of Z-source and quasi- Z-source dc-dc converters,” in Proc. IEEE Appl. Power Electron. Conf., pp. 1093-1101, 2009.

[27] T. Takiguchi and H. Koizumi, “Quasi-Z-source dc-dc converter with voltage-lift technique,” in Proc. 39th Annu. Conf. IEEE Ind. Electron. Soc. (IECON), pp. 1191-1196, 2013.

[28] H. Shen, B. Zhang, D. Qiu, and L. Zhou, “A common grounded Z-source DC-DC converter with high voltage gain,” IEEE Trans. Ind. Electron., Vol. 63, No. 5, pp. 2925-2935, May 2016.

[29] Y. Shindo, M. Yamanaka, and H. Koizumi, “Z-source DC-DC converter with cascade switched capacitor,” in Proc. 37th Annu. Conf. IEEE Ind. Electron. Soc. (IECON), pp. 1665-1670, 2011.

[30] Y. Zhang, J. Shi, L. Zhou, J. Li, M. Sumner, P. Wang, and C. Xia, “Wide input-voltage range boost three-level DC- DC converter with quasi-Z source for fuel cell vehicles,” IEEE Trans. Power Electron., Vol. 32, No. 9, pp. 6728- 6738, Sep. 2017.



그림입니다.
원본 그림의 이름: image66.jpeg
원본 그림의 크기: 가로 190pixel, 세로 248pixel

Huakun Bi was born in Shandong, China. He received his B.S. degree in Electrical Engineering from the Changchun University of Technology, Changchun, China, in 2013; and his M.S. degree in Electrical Engineering from the Hebei University of Technology, Tianjin, China, in 2016, where he is presently working towards his Ph.D. degree in Electrical Engineering. His current research interests include dc–dc converters, electric vehicles and DC microgrids.


그림입니다.
원본 그림의 이름: image67.png
원본 그림의 크기: 가로 190pixel, 세로 225pixel

Ping Wang was born in Tianjin, China, in 1959. She received her B.S., M.S. and Ph.D. degrees in Electrical Engineering from Tianjin University, Tianjin, China, in 1981, 1991 and 2005, respectively. In 1981, she joined Tianjin University as a Teacher and a Researcher, where she is presently working as a Professor. Her current research interests include power electronic control of renewable energy sources, PWM converters, and intelligent detection and control.


그림입니다.
원본 그림의 이름: image68.png
원본 그림의 크기: 가로 190pixel, 세로 225pixel

Yanbo Che was born in Liaocheng, China. He received his B.S. degree form Zhejiang University, Hangzhou, China, in 1993; and his M.S. and Ph.D. degrees from Tianjin University, Tianjin, China, in 1996 and 2002, respectively. Since 1996, he has been actively involved in the teaching and scientific research of power electronic technology and power systems. He is presently working as an Associate Professor in the School of Electrical and Information Engineering, Tianjin University. His current research interests include power systems, renewable energy resources and microgrids.