사각형입니다.

https://doi.org/10.6113/JPE.2018.18.5.1347

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Frequency Synchronization of Three-Phase Grid-Connected Inverters Controlled as Current Supplies


Zhenbin Fu*, Zhihua Feng*, Xi Chen**, Xinxin Zheng, and Jing Yin*


*Department of Precision Machinery and Precision Instrumentation, University of Science and Technology of China, Hefei, China

**Department of Substation Maintenance, State Grid Hefei Power Supply Company, Hefei, China

Institute of Automotive Engineering Technology, Hefei University of Technology, Hefei, China



Abstract

In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from –π to π. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.


Key words: Current control, Frequency locked loops, Pulse width modulation inverters, Space vector pulse width


Manuscript received Jan. 24, 2018; accepted May 11, 2018

Recommended for publication by Associate Editor T. Dragicevic.

Corresponding Author: zhengxinin@gmail.com Tel: +86-0551-62919030, Fax: +86-0551-62919033, Hefei Univ. Tech.

*Department of Precision Machinery and Precision Instrumentation, University of Science and Technology of China, China

**Department of Substation Maintenance, State Grid Hefei Power Supply Company, China



Ⅰ. INTRODUCTION

Three-phase PWM controlled grid-connected inverters are widely applied in the field of new energy power generation [1]-[4]. A coordinate transformation provides a time-invariant model of the inverter, which makes the control design similar to that of a DC/DC converter [5], [6]. The phase-locked technique of a three-phase grid-connected inverter is important. The synchronous reference frame phase-locked loop (SRF- PLL) is a conventional PLL method [7], [8]. It includes a phase detector (PD), a loop filter (LF) and a voltage controlled oscillator (VCO) [9], [10]. However, the performance of a SRF-PLL is deteriorated when the utility grid is non-ideal.

To adapt to non-ideal grids and to avoid the compromise between steady-state accuracy and a fast transient response, many advanced PLL methods have been proposed. The positive and negative sequence components of grid voltage are separated by a pre-filter in methods such as the decoupled double synchronous reference frame PLL (DDSRF-PLL) [11], the second-order generalized integrator PLL (SOGI-PLL) [12], [13] and the delayed signal cancellation PLL (DSC-PLL) [14]. The DDSRF-PLL employs two sets of oppositely rotating dq-frames to separate and cancel the negative-sequence components in grid voltage. Hence, it avoids the steady-state error caused by voltage unbalance. The SOGI-PLL has a generalized integrator (GI) as the main block, which generates the in-phase and quadrature-phase sinusoidal components of the input signal [15]. The DSC-PLL can effectively eliminate the oscillatory errors due to voltage unbalance by combining the original α-components and β-components of the grid voltage and their quarter-cycle delayed versions [16].

To simplify the control system, control strategies without a PLL have been proposed. In the traditional control strategy of three-phase grid-connected inverters, the grid angle takes part in the coordinate transformation. In fact, the grid angle can be replaced by a periodic linear changing angle from –π to π. The changing angle should have the same frequency as the grid angle. However, the grid frequency is changing and this control strategy cannot explain how to realize frequency locking. In [17], a structure simplification of the SOGI-PLL that replaces the PLL with a frequency-adaptive loop SOGI- FLL is introduced. To reject harmonics from the grid, a multiple SOGI (MSOGI-FLL) that uses a cross-feedback network consisting of multiple-SOGIs is proposed in [18]. The FLL estimates the frequency of the input signal and is used to tune the GI with the grid voltage frequency. It also needs a complex pre-filter to deal with a non-ideal grid. A new structure of the Adaptive Linear Neuron (ADALINE) with a Frequency Locked Loop (ADALINE-FLL) is presented in [19]. It offers good transient and steady state responses for frequency tracking, orthogonal signals generation and harmonics estimation. If the ADALINE-FLL is used in a three- phase inverter system based on coordinate transformation control, the ADALINE neuron can also be seen as a pre-filter of the grid voltage. These kinds of FLL have a common characteristic. When compared to PLLs with pre-filters, the FLLs do not need loop filters. However, complex pre-filters cannot be avoided.

In [20], [21], a current reference is generated by using the instantaneous power control scheme and a positive-sequence voltage detector. The closed-loop control is realized in the α-β coordinate system instead of the d-q coordinate system and a PLL is not necessary. Under this condition, the current reference is an AC signal and a double resonant filter is applied to realize zero steady state. When the grid frequency is changing, the parameters of a double resonant filter are difficult to design. In [22], a synchronization function is embedded into the power controller and a PLL unit is not required. A PR regulator is applied in the current loop. In a grid with a changing frequency, a regulator with fixed parameters cannot completely realize zero steady state. These kinds of PLL-less methods have some common characteristics. The references of the control loop are no longer DC signals and the loop filters should deal with the problems caused by an unfixed frequency. The design of the filters needs further research.

Grid synchronization techniques without a dedicated synchronization unit have attracted a lot of attention [23], [24]. However, the inverter should be controlled as a voltage supply. The proposed grid synchronization technique does not apply to current type inverters with a current control method. Inverters controlled as a current supply can provide high steady state and dynamic features [25]. This is most suitable for strong grid applications in which the output voltage of the inverter is clamped by the grid [26]. Non-ideal conditions also exist in strong grids. Therefore, when a inverter is controlled as a current supply, research on control strategies without a PLL is significant.

In this paper, a novel current control strategy of three- phase grid-connected inverters without a PLL is proposed. The frequency synchronization is realized by a FLL. A periodic linear changing angle from –π to π with the frequency of the grid is generated by a DSP controller, and it takes part in coordinate transformations instead of the grid phase angle. The FLL is realized by negative feedback of the reactive power. The frequency of the changing angle does not affect the frequency of the output voltage. Therefore, the proposed FLL is not incompatible with the theory that the frequency mainly affects the active power of an inverter. When compared to the traditional current control strategy, the proposed strategy can realize a balance and a low THD of the grid current in a non-ideal grid. In addition, there is no need to design the complex pre-filters of PLLs.

This paper is organized as follows. Section II discusses the impact of the changing angle that takes part in coordinate transformations. Section III describes the principle of the grid frequency tracking method. Section IV shows the proposed control strategy, which is applied to a non-ideal grid. A complex pre-filter is necessary in the traditional control strategy with a PLL. However, it can be saved in the proposed control strategy without a PLL. Control diagrams of the FLL and PLL are established and compared. Section V presents experimental results obtained with an 18 kW three-phase grid-connected inverter with the proposed control strategy. Section VI is the conclusion of this work.



Ⅱ. IMPACT OF COORDINATE TRANSFORMATIONS

A basic topology of a three-phase grid-connected inverter is shown in Fig. 1. ea, eb and ec are the grid voltages. ia, ib and ic are the grid currents. ua, ub and uc are the output voltages of the inverter. La, Lb and Lc are the AC side filters.


그림입니다.
원본 그림의 이름: image50.emf
원본 그림의 크기: 가로 430pixel, 세로 267pixel

Fig. 1. Topology of a three-phase grid-connected inverter.


The control strategy based on a coordinate transformation is shown in Fig. 2. In Fig. 2(a), θ1 is the grid angle which is detected by a PLL. It takes part in coordinate transformations and the three-phase grid current can be transformed into a two-phase DC current. A PI regulator can realize zero steady state error of the current loop. ud* and uq* are the references of the output voltage in the dq-frame. After a coordinate transformation, they are transformed into two-phase AC voltages uα* and uβ*. The frequencies of uα* and uβ* are the same as those of ua, ub and uc.


Fig. 2. Control strategy based on coordinate transformation: (a) With a PLL, (b) Without a PLL.

그림입니다.
원본 그림의 이름: image51.emf
원본 그림의 크기: 가로 468pixel, 세로 306pixel

(a)

그림입니다.
원본 그림의 이름: image52.emf
원본 그림의 크기: 가로 468pixel, 세로 306pixel

(b)


The control strategy without a PLL proposed in [24] is shown in Fig. 2(b). The differences between control strategies with and without a PLL are reflected in the dashed box. f1 is given directly. This is the frequency of the periodic linear changing angle. With the integration of f1, it is possible to generate θ1 to take part in coordinate transformation. θ1 changes linearly from –π to π with a frequency of f1. The initial value of θ1 is random. It depends on the parallel time. θ1 takes part in both the coordinate transformation and the inverse transformation. Therefore, the initial value does not affect the control loop. It is unnecessary to determine the initial value of the integration. Therefore, θ1 is not the grid phase angle. They have the same frequency. However, their phase difference can be random.

However, the grid frequencies are different in different grids. For example, the frequency of an aircraft power grid is 400Hz, the frequency of a US city power grid is 60Hz, and the frequency of a Chinese city power grid is 50Hz. In addition, even in a certain grid, the grid frequency is continuously changing within an allowed range. It cannot always keep a standard value. If f1 is given directly, it may be different from the real grid frequency, which is defined as f0. The phase angel of the grid is θ0. If the initial phase angle of θ0 is set as 0, θ0 and θ1 can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc020d.bmp
원본 그림의 크기: 가로 427pixel, 세로 173pixel   (1)

where Δθ is the initial phase of θ1. The value of Δθ is random. The three-phase grid voltages can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0001.bmp
원본 그림의 크기: 가로 608pixel, 세로 275pixel    (2)

θ1 takes part in the coordinate transformation, and the projection of the grid voltage on the dq-axis can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0002.bmp
원본 그림의 크기: 가로 1254pixel, 세로 199pixel     (3)

The phase angle of the grid current is defined as θ2. In a current type inverter, the frequency of the grid current and the grid voltage are the same. θ2 can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0003.bmp
원본 그림의 크기: 가로 432pixel, 세로 82pixel   (4)

where Δφ is the phase difference of the grid current and the grid voltage. The grid current can be expressed as the following equations in the d-q frame:

그림입니다.
원본 그림의 이름: CLP000013dc0004.bmp
원본 그림의 크기: 가로 1405pixel, 세로 198pixel         (5)

According to (3) and (5), the relationship among ed, eq, id and iq can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0005.bmp
원본 그림의 크기: 가로 711pixel, 세로 198pixel         (6)

The output active and reactive powers of the inverter P and Q can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0006.bmp
원본 그림의 크기: 가로 951pixel, 세로 322pixel         (7)

Δθ is cancelled in this equation, which means that (7) applies to the dq-frame with different values of Δθ. In Fig. 2 (b), if Δθ is not 0, id* and iq* are no longer the references of the active and reactive currents. They should be calculated by the following equations:

그림입니다.
원본 그림의 이름: CLP000013dc0007.bmp
원본 그림의 크기: 가로 561pixel, 세로 403pixel      (8)

where P* and Q* are the references of the active and reactive powers of the inverter. ed and eq are projections of the grid voltage on the dq-axis, with θ1 taking part in the coordinate transformation.

According to (3) and (8), the reference current can be obtained by using the following equation:

그림입니다.
원본 그림의 이름: CLP000013dc0008.bmp
원본 그림의 크기: 가로 1424pixel, 세로 373pixel        (9)

The frequency of id* and iq* is the difference of f1 and f0. If f1 is equal to f0, id* and iq* are DC components. On the other hand, id* and iq* are AC components. There are two ways to realize zero steady-state error of the current error regulator. One is to use regulators with zero steady-state error to AC signals. The other is to force f1 to be equal to f0. Thus, the PI regulator can realize zero steady-state error to DC signals. The authors of [27] proposed regulators with zero steady-state error to AC signals. However, the difference between f1 and f0 should be obtained to design the parameters of the regulators, which are difficult to realize.

According to (7), Im and 그림입니다.
원본 그림의 이름: CLP000013dc0009.bmp
원본 그림의 크기: 가로 98pixel, 세로 70pixel can be obtained as:

그림입니다.
원본 그림의 이름: CLP000013dc000a.bmp
원본 그림의 크기: 가로 627pixel, 세로 377pixel   (10)

If the current error regulator can realize zero steady-state error, the feedback is equal to the reference current. i.e. id is equal to id*, and iq is equal to iq*. According to (5), (9) and (10), the relationship among P, Q and P* can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc000b.bmp
원본 그림의 크기: 가로 1382pixel, 세로 189pixel          (11)

where A and B can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc000c.bmp
원본 그림의 크기: 가로 341pixel, 세로 188pixel     (12)

The premise of (11) is that the current error regulator can realize zero steady-state error. According to (11), the relationship between A and B can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc000d.bmp
원본 그림의 크기: 가로 335pixel, 세로 97pixel      (13)

Regardless of whether f1 is equal to f0 or not, A and B are 0. P is equal to P* and Q is equal to Q*. Through an analysis, it can be concluded that a FLL is necessary to force f1 to be equal to f0. Only in this way is the premise of (11) possible.

id* and iq* may be AC components without a FLL, and a PI regulator has steady-state error for the AC components. id*, iq* and id, iq have phase differences. The closed-loop transfer function of the grid current to the current reference can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc000f.bmp
원본 그림의 크기: 가로 1148pixel, 세로 193pixel          (14)

where GPI(s) is the transfer function of the PI regulator, GINV(s) is the transfer function of the inverter, and GFIL(s) is the transfer function of the AC side filter. Fig. 3(a) shows the magnitude and phase-frequency characteristic curves of (14). The current loops of the control methods shown in Fig. 2(a) and 2(b) are the same. Thus, the PI regulator in Fig. 2(b) can be designed as a normal error regulator of the inverter current loop. According to the conventional design, the proportional coefficient of the PI regulator is 0.15 and the integral coefficient is 20.


Fig. 3. Impact of coordinate transformation: (a) Magnitude and phase-frequency characteristic curve, (b) Relationship between f1 and both P and Q.

그림입니다.
원본 그림의 이름: image67.emf
원본 그림의 크기: 가로 339pixel, 세로 209pixel

(a)

그림입니다.
원본 그림의 이름: CLP000013dc000e.bmp
원본 그림의 크기: 가로 651pixel, 세로 644pixel

(b)


The references of the three-phase current have the same phase as the grid voltage. The phase-frequency characteristic curve shows different Δφ at different frequencies. The magnitude-frequency characteristic curve shows different amplitude ratios at different frequencies. Thus, Δφ and Im can be obtained. Fig. 3(b) shows the relationship between f1 and both P and Q, which is obtained by (7). The grid frequency f0 is 50Hz, P* is 18kW and Q* is 0. P and Q can only track the reference when f1 and f0 are the same.



Ⅲ. THE PROPOSED CONTROL STRATEGY


A. Grid Frequency Tracking Method

In Fig. 3(b), the relationship between Q and f1 is a one-to-one correspondence. If f1 does not track f0, Q cannot track Q*. However, P - f1 is not a monotonic function. For example, the dot ‘A’ and ‘B’ both correspond to 18kW of P. A certain value of P may correspond to more than one value of f1. The negative feedback of Q can clamp the value of f1. The control strategy is shown in the dashed box in Fig. 4. It can replace the dashed boxes in Fig. 2. Another PI regulator PI1 is applied as the error regulator of the reactive power. Q can be calculated by (7).


그림입니다.
원본 그림의 이름: image70.emf
원본 그림의 크기: 가로 512pixel, 세로 342pixel

Fig. 4. Proposed control strategy.


The output of PI1 is f1. When f0 increases, it becomes higher than f1. According to Fig. 3(b), Q increases. In addition, the input of PI1 increases. The proportional regulation leads to increment of f1. If f0 is reduced, f1 is larger than f0. Similarly, f1 tends to reduce. The grid frequency tracking method can ensure that f1 is equal to f0 in the steady state. This method is applicable to any value of Q*.

It should be noted that f1 is the frequency of the changing angle. It is not the frequency of the output voltage ua, ub and uc. According to the above analysis, the difference between f1 and f0 can affect the phase and amplitude of ua, ub and uc, which may result in the output power of the inverter deviating from the reference. However, the frequency of ua, ub and uc is always f0 regardless of whether f1 is equal to f0. Therefore, the grid frequency tracking method is not incompatible with the theory that the frequency mainly affects the active power of the inverter.


B. Solution of Non-Ideal Grid

The proposed control strategy is shown in Fig. 4. A Low Pass Filter (LPF) is added to separate the positive sequence fundamental component of the grid voltage. Negative sequence voltage compensation is always added to inhibit the negative sequence grid current in unbalanced grids [28]. In this paper, the negative sequence fundamental component and the harmonics of the voltage are compensated. edp and eqp are the positive-sequence fundamental grid voltages. The feed-forward of ed minus edp and eq minus eqp are added to inhibit the negative sequence component and the harmonics of the grid current. uα* and uα* are references of the output voltage after compensation. After SVPWM is applied, the driving signals can be obtained. da, db and dc are the driving signals of the inverter.

In a non-ideal grid, the positive and negative sequence component of the grid voltage should be separated to take part in the control of the inverter. Therefore, a filter of the grid voltage is necessary. Filters such as the MCCF, CDSC and MSOGI are applied as the pre-filtering stage of a PLL or a FLL. In the proposed control strategy, the complex pre- filter is replaced by a simple LPF, which can simplify the control strategy.


C. Comparison of FLL and PLL

The feedback of negative power forms a FLL, which is shown in Fig. 5(a). Δf is the difference between f0 and f1. Δω is the angular frequency of Δf. δ is the integration of Δω. It is close to zero. According to (5), iq* can be approximated as:

그림입니다.
원본 그림의 이름: CLP000013dc0010.bmp
원본 그림의 크기: 가로 549pixel, 세로 171pixel      (15)

iq can be obtained after the current loop. According to (4), (14) and (15), Q can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0011.bmp
원본 그림의 크기: 가로 659pixel, 세로 101pixel   (16)

where GCL(s) is the closed-loop transfer function of the current loop, and GLPF(s) is the transfer function of the LPF. It can be seen that the current loop is the inner loop of the FLL. To design the parameters of the FLL, the closed-loop transfer function of the current loop GCL(s) can be seen as 1. The transfer function of the LPF can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0012.bmp
원본 그림의 크기: 가로 486pixel, 세로 270pixel         (17)

where ωc is the cut-off angular frequency of the LPF. Table I shows the harmonic order of the grid voltage in the abc-frame and the corresponding order in the dq-frame. It can be seen that in the dq-axis, only the projections of the fundamental positive sequence component are DC signals. To filter the AC components of ed and eq, the value of ωc should less than the grid angular frequency. When the grid frequency is 50Hz, ωc can be chosen as 310 rad/s.


TABLE I HARMONIC ORDER IN THE ABC FRAME AND THE CORRESPONDING ORDER IN THE DQ FRAME

Harmonic order in abc-frame

Harmonic order in dq-frame

Positive sequence

Negative sequence

1

0

2

2

1

3

3

2

4

4

3

5

k

k-1

k+1


Fig. 5. Control diagrams: (a) FLL, (b) PLL.

그림입니다.
원본 그림의 이름: image74.emf
원본 그림의 크기: 가로 475pixel, 세로 86pixel

(a)

그림입니다.
원본 그림의 이름: CLP000013dc0013.bmp
원본 그림의 크기: 가로 1533pixel, 세로 356pixel

(b)


Fig. 5(b) shows a control diagram of the PLL. The PLL and the current loop are separated. GL-F(s) is the transfer function of the loop-filter, which can also be designed as a PI regulator. The transfer function of PI1 in Fig. 5(a) and the loop-filter in Fig. 5(b) can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0014.bmp
원본 그림의 크기: 가로 667pixel, 세로 230pixel           (18)

where Kp1 and Ki1 are the proportional and integral coefficients of PI1. Kpf and Kif are the proportional and integral coefficients of the loop-filter.

GP-F(s) in Fig. 5(b) is the transfer function of the pre-filter. It can be seen as an inertial element and is expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0015.bmp
원본 그림의 크기: 가로 475pixel, 세로 175pixel         (19)

If Td is short enough, the pre-filter can be regarded as an ideal filter and its transfer function is 1 in the grid frequency. It can be seen that the LPF in Fig. 5(a) is also a pre-filter and that Td is 1/ωc. This can be replaced by a complex pre-filter to improve the dynamic performance. In that case, the FLL and the PLL can be expressed as a unified form. Their closed-loop transfer function without any pre-filters can be expressed as:

그림입니다.
원본 그림의 이름: CLP000013dc0016.bmp
원본 그림의 크기: 가로 1004pixel, 세로 196pixel      (20)

where ξ is the damping coefficient and ωn is the natural frequency. They can be expressed by the parameters of the FLL and the PLL.

그림입니다.
원본 그림의 이름: CLP000013dc0017.bmp
원본 그림의 크기: 가로 747pixel, 세로 331pixel        (21)

In order to realize system stability, ζ can be chosen as the empiric value 1/그림입니다.
원본 그림의 이름: CLP00000b4c3dd8.bmp
원본 그림의 크기: 가로 87pixel, 세로 67pixel, and ωn is 314rad. In addition, Kp1 and Ki1 can be calculated as 0.08 and 1.74. According to the Lienard-Chipard criterion, the characteristic equation of the FLL transfer function has positive coefficients. Thus, the system is stable.

A LPF can be applied in the FLL as a pre-filter. However, it cannot be applied in the PLL because the LPF would cause a phase delay. The input of the PLL is θ0. It changes periodically. If a LPF is applied, the output θ1 cannot track the input. On the other hand, the input of the FLL is f0. The LPF may slow down the speed of response. However, the output f1 can track the input.

Fig. 6 shows the input and output of a FLL and a PLL with different values of Td. When an ideal pre-filter is applied, Td is 0. When a LPF is applied, Td is 1/ωc. The grid frequency changes from 50Hz to 100Hz at 0.1s. In Fig. 6(a), an ideal pre-filter is applied to the FLL. In Fig. 6(b), a LPF is applied to the FLL. In Fig. 6(c), an ideal pre-filter is applied to the PLL. In Fig. 6(d), a LPF is applied to the PLL.


Fig. 6. Input and output of a FLL and a PLL: (a) FLL with an ideal pre-filter, (b) FLL with a LPF, (c) PLL with an ideal pre-filter, (d) PLL with a LPF.

그림입니다.
원본 그림의 이름: image81.emf
원본 그림의 크기: 가로 356pixel, 세로 200pixel

(a)

그림입니다.
원본 그림의 이름: image82.emf
원본 그림의 크기: 가로 355pixel, 세로 200pixel

(b)

그림입니다.
원본 그림의 이름: image83.emf
원본 그림의 크기: 가로 356pixel, 세로 201pixel

(c)

그림입니다.
원본 그림의 이름: image84.emf
원본 그림의 크기: 가로 355pixel, 세로 201pixel

(d)


According to Fig. 6(b) and Fig. 6(d), θ1 in the FLL is the integral result of f1. f1 is able to track f0. θ1 may have a phase difference with a grid angle of θ0. However, this is allowed. θ1 in the PLL is the output of the system. It cannot track θ0, which is the input of the system. According to Fig. 6(a), Fig. 6(b) and Fig. 6(c), the dynamic performance of a FLL with a LPF is worse than that of a FLL or a PLL with an ideal pre-filter. A pre-filter is necessary to ensure that the inverter works well in a non-ideal grid. However, it is hard to design a pre-filter with a short time delay. In an overall consideration, the FLL with a LPF is very simple and it can achieve a balance and a low THD of the grid current in a non-ideal grid.

Table II shows the frequency tracking times of a SRF-PLL and the proposed FLL both with and without a LPF. The dynamic response of the proposed control strategy may be worse than that of the traditional PLL. However, it adapts to a non-ideal grid and is simple.


TABLE II FREQUENCY TRACKING TIME

 

SRF-PLL

FLL without LPF

FLL with LPF

Tracking time/ms

3.27

3.31

14.65


When compared to the linear control mentioned above, nonlinear control can further improve the whole system performance. There are many nonlinear control strategies. The transient behavior of the observer can be quantitatively analyzed [29]. Thus, the design of the controller is not complex. However, a changing grid frequency results in new transient behavior of the observer. In order to use a linear controller, further analysis should be developed.



Ⅳ. EXPERIMENTAL RESULTS

An 18 kW three-phase grid-connected inverter based on a TMS320f2812 has been built. The parameters are designed through the theoretical analysis mentioned above. The DC-link voltage is 700V. The switching frequency is 5kHz. The grid frequency is 50Hz. The parameters are listed in Table III, and were designed in Sections II and III.


TABLE III EXPERIMENTAL PARAMETERS

L Filter

Kp1

Ki1

Kp2

Ki2

Kpf

Kif

5mH

0.08

1.74

0.15

20

0.12

2.37


The grid voltage is supplied by a programmable source. Fig. 7 shows experimental results when f1 is given directly instead of the output of a FLL. The waveforms in Fig. 7(a) are the grid voltage and current. The values of f1 and f0 are the same. In Fig. 7(b), f1 is 60Hz. It can be seen that without a FLL, f1 may be different from f0, which would reduce the PF of the inverter.


Fig. 7. Experimental results without a FLL: (a) Grid voltage and current when f1 is 50Hz, (b) Grid voltage and current when f1 is 60Hz.

그림입니다.
원본 그림의 이름: image85.emf
원본 그림의 크기: 가로 273pixel, 세로 231pixel

(a)

그림입니다.
원본 그림의 이름: image86.emf
원본 그림의 크기: 가로 273pixel, 세로 231pixel

(b)


Fig. 8 shows experimental results with a FLL in an unbalanced grid. The peak voltages of eb and ec are set as 311V. The peak voltage of ea is set as 250V. In Fig. 8(a), the waveforms are the grid voltage ea, eb, ec and the angle θ1. Here θ1 is a liner changed variable and it takes part in coordinate transformation. It is the integral of f1, which is the output of the FLL. Fig. 8(b) shows waveforms of ea and the grid current without the feed-forward of the grid voltage. The grid current changes sinusoidally. However, it is unbalanced. Fig. 8(c) shows waveforms of ea and the grid current with the feed-forward of the grid voltage. The three-phase grid current is balanced.


Fig. 8. Experimental results with a FLL in an unbalanced grid: (a) Waveforms of the grid voltage and θ1, (b) Waveforms of ea and the grid current without the feed-forward of the grid voltage, (c) Waveforms of ea and the grid current with the feed-forward of the grid voltage.

그림입니다.
원본 그림의 이름: image87.emf
원본 그림의 크기: 가로 272pixel, 세로 229pixel

(a)

그림입니다.
원본 그림의 이름: image88.emf
원본 그림의 크기: 가로 274pixel, 세로 230pixel

(b)

그림입니다.
원본 그림의 이름: image89.emf
원본 그림의 크기: 가로 274pixel, 세로 227pixel

(c)


Fig. 9 shows experimental results with the SRF-PLL in an unbalanced grid. In Fig. 9(a), the waveforms are the grid voltage ea, eb, ec and the angle θ1. Here θ1 is the output of the PLL. It does not change linearly. Fig. 9(b) shows waveforms of ea and the grid current with the feed-forward of the grid voltage. A comparison between Fig. 8(c) and Fig. 9(b) shows that with the SRF-PLL, the feed-forward method cannot completely avoid the distortion of the grid current in an unbalanced grid.


Fig. 9. Experimental results with the SRF-PLL in an unbalanced grid: (a) Waveforms of the grid voltage and θ1, (b) Waveforms of ea and the grid current with the feed-forward of the grid voltage.

그림입니다.
원본 그림의 이름: image90.emf
원본 그림의 크기: 가로 273pixel, 세로 230pixel

(a)

그림입니다.
원본 그림의 이름: image91.emf
원본 그림의 크기: 가로 273pixel, 세로 230pixel

(b)


Fig. 10 shows experimental results with a FLL when the grid contains harmonic. The peak voltages of ea, eb and ec are set as 311V. Fifth-order harmonics with a peak voltage of 15V are injected. In Fig. 10(a), the waveforms are the grid voltage ea, eb, ec and the angle θ1. Fig. 10(b) shows waveforms of ea and the grid current without the feed- forward of the grid voltage. Fig. 10(c) shows waveforms of ea and the grid current with the feed-forward of the grid voltage. The three-phase grid current changes sinusoidally. It can be seen that the feed-forward method can eliminate current distortion.


Fig. 10. Experimental results with a FLL when the grid contains harmonics: (a) Waveforms of the grid voltage and θ1, (b) Waveforms of ea and the grid current without the feed-forward of the grid voltage, (c) Waveforms of ea and the grid current with the feed-forward of the grid voltage.

그림입니다.
원본 그림의 이름: image92.emf
원본 그림의 크기: 가로 273pixel, 세로 230pixel

(a)

 

그림입니다.
원본 그림의 이름: image93.emf
원본 그림의 크기: 가로 273pixel, 세로 231pixel

(b)

 

그림입니다.
원본 그림의 이름: image94.emf
원본 그림의 크기: 가로 273pixel, 세로 233pixel

(c)


Table IV shows the THDs of the grid current with different PI regulator parameters of the FLL. Kp1 and Ki1 are the PI regulator parameters of the FLL. Kp2 and Ki2 are the PI regulator parameters of the current loop. The THD has low sensitivity to the control parameters, which shows that the system has high stability.


TABLE IV THDS WITH DIFFERENT PI REGULATOR PARAMETERS OF A FLL

Kp1

Ki1

Kp2

Ki2

THD

0.08

1.74

0.15

20

3.09%

0.05

2.74

0.15

20

3.07%

0.08

1.74

0.25

15

3.13%

0.05

2.74

0.25

15

3.11%


A change of the parameters affects the dynamic performance of the system. It is a typical problem of closed-loop systems, which has been analyzed in section II. When the grid frequency changes, the feedback and reference values of the reactive power are offset. The reactive power loop works and f1 tracks the grid frequency. However, the PI regulating effect is limited for a rapid periodic variation signal. If the grid has a high frequency oscillation, further research on an improved error regulator should be considered.

Table V shows the THDs of the grid current with the feed-forward method under different conditions. It can be seen that the proposed control strategy can realize a low THD of the grid current in a non-ideal grid.


TABLE V THDS OF THE GRID CURRENT WITH THE FEED-FORWARD METHOD UNDER DIFFERENT CONDITIONS

Phase

 

a

b

c

Unbalanced grid

FLL

3.11%

3.17%

3.18%

SRF-PLL

5.98%

6.25%

6.55%

Fifth-order harmonic injection

FLL

3.17%

3.24%

3.21%

SRF-PLL

7.68%

7.89%

8.43%



Ⅴ. CONCLUSION

This paper proposes a novel control strategy without a PLL for three-phase grid-connected inverters. The PLL in the traditional control strategy of inverters is replaced by a FLL. The principle of the control strategy is analyzed. A comparison of a FLL and a PLL is given. The proposed control strategy has the following characteristics.

(1) With the proposed control strategy, the inverter can realize a high PF and a low THD in a grid which is unbalanced or has harmonics.

(2) The complex pre-filters of existing PLLs or FLLs can be saved. Therefore, the control system can be simplified. In addition, the grid frequency can be detected. Therefore, the problems caused by an unfixed frequency which occur in existing PLL-less methods can be solved.

(3) Nonlinear control should be applied instead of linear control with the PI regulator in the next step to obtain a good performance in grids with a frequency oscillation.



ACKNOWLEDGMENT

The authors would like to acknowledge the support provided by the Special Foundation for doctoral degree (JZ2015HGBZ0456) and the National Natural Science Foundation (51607052).



REFERENCES

[1] K. Takagi and H. Fujita,A three-phase grid-connected inverter equipped with a shunt instantaneous reactive power compensator,” in Proc. ECCE '17, pp. 589-596, 2017.

[2] Y. He, H. S. Chung, C. N.-M. Ho, and W. Wu, “Direct current tracking using boundary control with second-order switching surface for three-phase three-wire grid-connected inverter,” IEEE Trans. Power Electron., Vol. 32, No. 7, pp. 5723-5740, Jul. 2017.

[3] M. Adel, R. Abdellatif, and B. Hocine, “ Two vector based direct power control of AC/DC grid connected converters using a constant switching frequency,” J. Power Electron., Vol. 17, No. 5, pp. 1363-1371, Sep. 2017.

[4] A. Shayestehfard, S. Mekhilef, and H. Mokhlis. “IZDPWM- based feedforward controller for grid-connected inverters under unbalanced and distorted conditions,” IEEE Trans. Ind. Electron., Vol. 64, No. 1, pp. 14-21, Jan. 2017.

[5] C. Zhu, Z. Zeng, and R. Zhao, “Comprehensive analysis and reduction of torque ripples in three-phase four-switch inverter-fed PMSM drives using space vector pulse-width modulation,” IEEE Trans. Power Electron., Vol. 32, No. 7, pp. 5411-5424, Jul. 2017.

[6] J. Dalei and K. B. Mohanty, “An approach to improve the performance of three-phase self-excited induction generator feeding an induction motor load using hilbert transform and coordinate rotation digital computer,” Electric Power Compon. Syst., Vol. 44, No. 14, pp. 1551-1563, Aug. 2016.

[7] R. Luhtala, T. Messo, T. Reinikka, J. Sihvo, T. Roinila and M. Vilkko. “Adaptive control of grid-connected inverters based on real-time measurements of grid impedance: DQ-domain approach” in Proc. ECCE '17, pp. 69-75, 2017.

[8] S. Golestan, M. Ramezani, J. M. Guerrero, and M. Monfared, “DQ-frame cascaded delayed signal cancellation-based PLL: analysis, design, and comparison with moving average filter-based PLL,” IEEE Trans. Power Electron., Vol. 30, No. 3, pp. 1618-1632, Aug. 2015.

[9] P. Kanjiya, V. Khadkikar, and M. S. E. Moursi, “Obtaining performance of type-3 phase-locked loop without compromising the benefits of type-2 control system,” IEEE Trans. Power Electron., Vol. 33, No. 2, pp. 1788-1796, Feb. 2018.

[10] S. Golestan, M. Monfared, F. D. Freijedo, and J. M. Guerrero, “Advantages and challenges of a type-3 PLL,” IEEE Trans. Power Electron., Vol. 28, No. 11, pp. 4985- 4997, Nov. 2013.

[11] K. S. Fuad, E. Hossain, and M. R. U. Chowdhury, “Grid- voltage synchronization algorithm for grid tied renewable energy sources during adverse grid fault condition,” in Proc. ICISET '16, pp. 1-5, 2016.

[12] P. Tan, H. He, and X. Gao, “A frequency-tracking method based on a SOGI-PLL for wireless power transfer systems to assure operation in the resonant state,” J. Power Electron., Vol. 16, No. 3, pp. 1056-1066, May 2016.

[13] P. Tan, H. He, and X. Gao, “Phase compensation, ZVS operation of wireless power transfer system based on SOGI-PLL,” in Proc. APEC '16, pp. 3185-3188, 2016.

[14] Q. Huang and K. Rajashekara, “An improved delayed signal cancellation PLL for fast grid synchronization under distorted and unbalanced grid condition,” IEEE Trans. Ind. Appl., Vol. 53, No. 5, pp. 4985-4997, Oct. 2017.

[15] J. Matas, M. Castilla, J. Miret, L. G. de Vicuna, and R. Guzman, “An adaptive prefiltering method to improve the speed/accuracy tradeoff of voltage sequence detection methods under adverse grid conditions,” IEEE Trans. Ind. Electron, Vol. 61, No. 5, pp. 2139-2151, Jan. 2014.

[16] Y. F. Wang and Y. W. Li, “Grid synchronization PLL based on cascaded delayed signal cancellation,” IEEE Trans. Power Electron., Vol. 26, No. 7, pp. 1987-1997, Jul. 2011.

[17] Z. Zeng, H. Yang, R. Zhao, and C. Song, “A novel control strategy for grid-connected inverters with LC filter based on passive hamiltonian theory,” Power System Technology Vol. 36, No. 4, pp. 207-212, Apr. 2012. (in Chinese)

[18] P. Rodriguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, “Advanced grid synchronization system for power converters under unbalanced and distorted operating conditions,” in Proc. IECON '16, pp. 5173-5178, 2016.

[19] C. Guzman, A. Cardenas, and K. Agbossou, “Control of voltage source inverter using FPGA implementation of ADALINE-FLL,” in Proc. IECON '12, pp. 3037-3042. Dec. 2012.

[20] L. Zhou, M. Yang, Q. Liu, and K. Guo, “New control strategy for three-phase grid-connected LCL inverters without a phase-locked loop,” J. Power Electron., Vol. 13, No. 3, p. 487, May 2013.

[21] X. Guo, W. Liu, X. Zhang, X. Sun, Z. Lu, and J. M. Guerrero, “Flexible control strategy for grid-connected inverter under unbalanced grid faults without PLL,” IEEE Trans. Power Electron., Vol. 30, No. 4, pp. 1773-1778, Apr. 2015.

[22] X. Li and R. S. Balog, “PLL-less robust active and reactive power controller for single phase grid-connected inverter with LCL filter,” in Proc. APEC'15, pp. 2154-2159, 2015.

[23] Q.-C. Zhong, P.-L. Nguyen, Z. Ma, and W. Sheng, “Self- synchronized synchronverters: inverters without a dedicated synchronization unit,” IEEE Trans. Power Electron., Vol. 29, No. 2, pp. 617-630, Jan. 2014.

[24] D. Kalyanraj, M. Vignesh, and S. S. Aravindan, “Performance analysis of different current control strategies for grid tied three phase voltage source inverter.” J. Contr. Instrum. Eng., Vol. 3, No. 1, pp. 19-27, Jan. 2017.

[25] D. Chen, J. Jiang, Y. Qiu, J. Zhang, and F. Huang, “Single- stage three-phase current-source photovoltaic grid-connected inverter high voltage transmission ratio,” IEEE Trans. Power Electron., Vol. 32, No. 10, pp. 7591-7601, Oct. 2017.

[26] J. Xu, S. Xie, and B. Zhang, “Current harmonics rejection and improvement of inverter-side current control for the LCL filters in grid-connected applications,” J. Power Electron., Vol. 17, No. 6, pp. 1672-1682, Nov. 2017.

[27] X. Guo and J. M. Guerrero, “General unified integral controller with zero steady-state error for single-phase grid- connected inverters.” IEEE Trans. Smart Grid, Vol. 7, No. 1, pp. 74-83, Jan. 2016.

[28] Z. Wang, S. Fan, Z. Zou, Y. Huang, and M. Cheng, “Control strategies of current-source inverters for distributed generation under unbalanced grid conditions,” in Proc. ECCE '12, pp. 4671-4675, 2012.

[29] C. R. Baier, M. Torres, J. A. Muñoz, J. M. Mauricio, J. Rohten, and M. Rivera, “Nonlinear control strategy for current source cascaded H-bridge inverters – An approach considering single-phase DQ components,” in Proc. ICIT’15, pp. 3079-3084, 2015.



그림입니다.
원본 그림의 이름: image95.jpeg
원본 그림의 크기: 가로 183pixel, 세로 253pixel

Zhenbin Fu was born in Anhui, China. He received his B.S. degree in Mechanical Engineering from the University of Science and Technology of China, Hefei, China, in 2007; and his M.S. degree in Instrument Engineering from Tsinghua University, Beijing, China, in 2010. He is presently working towards his Ph.D degree at the University of Science and Technology of China.


그림입니다.
원본 그림의 이름: image96.jpeg
원본 그림의 크기: 가로 199pixel, 세로 239pixel

Zhihua Feng was born in 1964. He received his B.S., M.S. and Ph.D degrees from the Universuty of Science and Technology of China (USTC), Hefei, China, in 1987, 1990 and 2005, respectively. He is presently working as a Professor in the Department of Precision Machinery and Precision Instrumentation, USTC. His current research interests include smart actuators and sensors, energy harvesting, power electronics, and robotics.


그림입니다.
원본 그림의 이름: image97.jpeg
원본 그림의 크기: 가로 195pixel, 세로 271pixel

Xi Chen was born in Jiangsu, China. He received his B.S. degree in Electrical Engineering from Nanjing Normal University, Nanjing, China, in 2008; and his M.S. degree in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2011. He is presently working in the Department of Substation Maintenance, State Grid Hefei Power Supply Company, Hefie, China.


그림입니다.
원본 그림의 이름: image98.jpeg
원본 그림의 크기: 가로 196pixel, 세로 239pixel

Xinxin Zheng was born in Anhui, China. She received her B.S. and Ph.D. degrees in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2009 and 2015, respectively. She is presently working in the Institute of Automotive Engineering Technology, Hefei University of Technology, Hefei, China.


그림입니다.
원본 그림의 이름: image99.jpeg
원본 그림의 크기: 가로 125pixel, 세로 182pixel

Jing Yin was born in 1986, in Anhui, China. She received her B.S. degree in Mechanical Engineering at the University of Science and Technology of China (USTC), Hefei, China, in 2011, where she is presently working towards her Ph.D. degree in Mechanical Engineering. Her current research interests include high-precision measurement technology, eddy current sensors, advanced fabrication and smart materials. She is currently working on developing temperature compensation for precision measurements.