https://doi.org/10.6113/JPE.2018.18.5.1523

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Fast Single-Phase All Digital Phase-Locked Loop for Grid Synchronization under Distorted Grid Conditions

Peiyong Zhang^†, Haixia Fang*, Yike Li*, and Chenhui Feng**

^†,*College of Electrical Engineering, Zhejiang University, Hangzhou, China

**College of Physics and Information Engineering, Fuzhou University, Fuzhou, China

Abstract

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

Key words: ADPLL, CORDIC, DDS, Distorted grid, Single-phase

Manuscript received Jul. 16, 2017; accepted Apr. 6, 2018

Recommended for publication by Associate Editor Young-Doo Yoon.

^†Corresponding Author: zhangpy@vlsi.zju.edu.cn Tel: +86-571- 8795-1679, Zhejiang University

*College of Electrical Engineering, Zhejiang University, China

**College of Physics and Information Eng., Fuzhou University, China

Ⅰ. INTRODUCTION

Grid synchronization is a crucial aspect in grid-tied power electronic applications, such as distributed generation (DG) units, uninterruptible power supplies (UPS), grid power converters, and so on. The key to this synchronization is how to quickly and accurately obtain information on the utility voltage, namely the phase, frequency and amplitude. Various methods have been produced to achiever this. Phase-locked loop (PLL) techniques have drawn a lot of attention owing to their simplicity, robustness and effectiveness [1]-[3].

A PLL, which is a nonlinear negative feedback control system, synchronizes its output in terms of frequency and phase with its input [4]. It is composed of three parts: a phase detector (PD), loop filter (LF) and voltage controlled oscillator (VCO). The PD generates a phase error between the input signal and the feedback signal. The LF filters the error and provides a control reference for the VCO. Then the VCO outputs the in-phase signal once the PLL is locked [5], [6].

Many different kinds of PLLs for grid synchronization have been proposed. Depending on the application, these PLLs can be divided into two major categories: single-phase PLLs and three-phase PLLs. In general, the design of single- phase PLLs is more complicated than that three-phase PLLs. This is due to the fact that single-phase PLLs lack multiple independent inputs to extract the phase error while three- phase PLLs can easily obtain the error by an abc→dqo transformation [7], [8]. The power- based PLL (pPLL) can better illustrate this fact. It has the simplest structure but suffers from obvious double-frequency oscillations [9]-[11]. Hence, synchronous rotating reference frame phase-locked loops (SRF-PLLs) as a solution for this drawback have drawn a lot of attention in recent years [12]. They have been developed from three-phase PLLs and they use an orthogonal signal generator (OSG)-based PD to detect the phase error. According to the OSG, various SRF-PLLs have been designed, such as the delay-based PLL and the differential-based PLL. The inverse-park transform-based PLL (Park-PLL) and the second-order generalized integrator-based PLL (SOGI-PLL) are also SRF-PLLs. Both of them show a relatively fast transient response and a high disturbance rejection capability [13].

However, the complex grid environment poses higher requirements to traditional single-phase PLLs. Firstly, the PLLs must be able to remove dc offset, which leads to phase-locked inaccuracies. Even if the system is well designed, a dc component may arise due to temporary system faults, measurement devices and conversion processes [14]- [16]. By adding an in-loop low-pass filter (LPF), a dc feedback loop and a dc error compensation algorithm have been proposed in [14], [15]. They are always undesirable due to their bad influence on the dynamic response. Secondly, the PLLs must track the power frequency and achieve frequency self-adaption or the frequency variations brings errors. Feeding back the estimated frequency to the PD is always used [17]. However, such a frequency feedback loop decreases the system bandwidth and makes tuning sensitive, which reduces the stability margins and dynamic response [17], [18]. Thirdly, the PLLs must have enough filtering capability for harmonics to improve robustness. A good phase-locked accuracy and a fast response speed are the pursuit of PLLs. However, there is always a tradeoff between steady-state accuracy and transient response. Adding a feedback loop, like frequency and dc feedback loops, means introducing an additional tradeoff and deteriorating the dynamic performance [19], [20]. In addition, the traditional implementation of PLLs using microprocessors or DSPs is subjected to sequential operation. The sample rate of PLLs is limited, which impedes the improvement of the dynamic and steady-state performances.

In this paper, a new single-phase all digital PLL (ADPLL) is proposed to ensure a fast dynamic response. It is designed for Field Programmable Gate Array (FPGA) implementation with a sampling frequency of 1MHz, which leads to potential improvements in the transient response and steady-state accuracy. The PD and VCO are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. Therefore, the detection of phase errors with a data width of 24 bits and a frequency control with a step size of 0.0596Hz can be acquired. Moreover, the ADPLL proposes a new method to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it is based on an open-loop method, which avoids the addition of an extra feedback loop. In this case, a new kind of parameter design method is used to obtain a large bandwidth and a fast response speed.

The rest of this paper is organized as follows. Section II introduces the basic structure of the ADPLL. Section III talks about the ADPLL implementation, including the discretization, configuration and parameter design. Section IV discusses a performance analysis of the ADPLL. In Section V experimental results are presented to validate the robustness and effectiveness of the ADPLL. Finally, some conclusions are given in the final section.

Ⅱ. STRUCTURE OF THE ADPLL

In this section, a brief overview of the ADPLL is presented. As shown in Fig. 1, the ADPLL includes five parts: OSG, PD, LF, VCO and OUT. Each of the components is described in detail in the following.

Fig. 1. Schematic diagram of the proposed ADPLL.

A. OSG

The OSG includes a cascaded frequency-adaptive SOGI (CFA SOGI) and a parallel frequency detector (PFD). The CFA SOGI is based on adjustable parameters and designed with sufficient removal capabilities in terms of the harmonics and the dc offset. The PFD is adopted to detect the input frequency and to provide a frequency reference for the CFA SOGI to realize frequency self-adaption.

1) CFA SOGI Module:

The standard SOGI structure as an OSG is shown in Fig. 2, and the close-loop transfer functions are given in (1), where ω₀ is the center frequency and k is the gain factor.

   (1)

Fig. 2. Structure of the SOGI.

Assuming that the input voltage is V_in=Acosθ_in= Acos(ω_int), under a frequency-locked condition (ω_in=ω₀), the outputs of the SOGI can be derived as (2). Since 4-k² must be more than 0, then k is less than 2 (k<2). In addition, v_α and v_β are momentary components of the SOGI. Therefore, in the steady state its outputs include an in-phase signal V_αs and an orthogonal signal V_βs.

          (2)

where:

 and

Fig. 3 and Fig. 4 are Bode diagrams and step response diagrams of the SOGI with different k values. In addition, ω₀ is fixed to 100π. From Fig. 3 and Fig. 4, the following characteristics can be observed.

Fig. 3. Bode diagrams of the SOGI. (a) G_αs(s). (b) G_βs(s).

(a)

(b)

Fig. 4. Step response diagrams of the SOGI. (a) G_αs(s). (b) G_βs(s).

(a)

(b)

a) G_αs works as a band-pass filter with a center frequency of ω₀ while G_βs is a low-pass filter with a corner frequency of ω₀. In addition, G_βs exhibits a better filtering feature than G_αs. However, it cannot provide zero dc gain. This means that the SOGI is sensitive to dc offset.

b) If ω_in≠ω₀, phase shift and amplitude attenuation occur. The outputs of the SOGI are impacted and inaccurately orthogonal. In the case of the CGI OSG in [16], when the input frequency is 46(54) Hz, the amplitudes are attenuated by -0.214(-0.118) dB and 0.516(-0.881) dB, while the phases are changed by 11.6° (-10.4°) and -78.4° (-100°). Hence, the center frequency of the OSG must be adjustable to guarantee the accuracy of the PLL.

c) The value of k can determine the bandwidth, response speed and filtering performance of the SOGI. A larger k makes a higher bandwidth, which offers a faster dynamic response with a bigger oscillation. It also means less immunity to the effects of harmonics in the grid voltage. On the other hand, a smaller k gives a narrower bandwidth and a better filtering capability to improve steady-state accuracy. However, it also results in a slower dynamic speed with a smaller overshoot. Therefore, the parameter k imposes a tradeoff between dynamic response and steady-state accuracy. A compromise must be made to obtain optimal performance.

In this paper, the modified SOGI structure shown in Fig. 5 is proposed. It is based on a cascaded SOGI structure. The first SOGI is used to remove dc offset, the second SOGI is used to improve attenuation capabilities of harmonics and the last SOGI works as an OSG. Moreover, they are all adaptive for the variation of the input frequency to guarantee phase- locking accuracy under frequency-varying conditions.

Fig. 5. Structure of the proposed CFA SOGI.

Note that the second SOGI uses G_βs instead of G_αs to obtain better attenuation capabilities in terms of harmonics. Meanwhile it introduces a 90° phase shift. Assuming an input grid voltage of V_in=Acosθ_in, the OSG outputs can be derived by:

         (3)

If the outputs are directly transmitted to PD, PD fails to work. Hence, a switch (W), like the one shown in Fig. 1, is needed and new assignments are given in (4). As a result, the proposed OSG achieves the same outputs as other OSGs.

   (4)

2) PFD Module:

As shown in Fig. 6, the PFD is based on a parallel frequency detecting technology. In addition, a SOGI, which is used to reject dc offset, harmonics and other interferences in the grid voltage, is required to ensure high-accuracy frequency detection. Note that the parameter ω₀ must be fixed, so that the fixed-parameter SOGI can still accurately transmit frequency information to the frequency detector and avoid a new feedback loop.

Fig. 6. Structure of the PFD.

B. PD

Unlike previous PDs, the proposed PD can extract the phase error of sine and cosine signals. It is based on a CORDIC and a selector switch (SW) as follows.

1) CORDIC Module:

In the conventional SRF-PLL, a park transformation (5) is always employed as a PD. The outputs V_q and V_d carry the phase error and amplitude information, respectively.

    (5)

In this paper, a CORDIC algorithm is used. It generates either a vector rotation or a vector translation. A vector translation rotates a vector (X, Y) to the x-axis and returns the angle θ. A vector rotation rotates a vector (X, Y) by the angle θ and yields a new vector (X^’, Y^’), as illustrated in (6).

    (6)

Thus, the CORDIC algorithm in the vector rotation mode essentially achieves the same result as a Park transformation. Moreover, it can be easily implemented on a digital platform by means of a simple shift-adder structure and it can obtain a good performance by the optimum use of computation resources.

2) SW Module:

In general, the OSG is directly connected to the PD. There is no problem when the input signal is a cosine signal. However, for a sine signal V_in=Asinθ_in, the PD fails to work and its outputs are derived as (7).

   (7)

Apparently, V_q no longer reflects the phase error. This means that the PLL fails to lock the phase of sinθ_in. In this paper, a SW is used to deal with this issue. As shown in Table I, it works as a selector switch to produce different outputs by judging the output value of the PD (X^’). X_JD is a boundary value to distinguish between sine and cosine input signals.

TABLE I PRINCIPLE OF THE SW

Judging condition	Judging result	Outputs
		Vq	Vd	Vout	Voutq
X’< XJD	Vin=Asinθin	Y’	-X’	Asinθout	Acosθout
X’> XJD	Vin=Acosθin	X’	Y’	Acosθout	Asinθout

C. LF

In this paper, a proportional-integral (PI) controller is chosen to implement the LF. The transfer function is shown in (8), where k_p and k_i are the proportional and integral parameters, respectively. Considering its direct influence on the PLL performance, a parameter optimization design is adopted and discussed in the following section.

         (8)

D. VCO

The VCO works as an integrator to generate the output phase angle. In this paper, it is realized by a DDS which has been widely used in practice due to its good frequency turning agility and high accuracy.

A DDS can produce a frequency-tunable and phase-tunable output signal according to a fixed-frequency clock. The relationship between the output frequency (f_clk) and the input frequency tuning word (FTW) is expressed as (9), where B_θ is the width of the DDS and Δf is the frequency resolution. The FTW is an unsigned decimal number with no units.

          (9)

A simplified diagram of the DDS is presented in Fig. 7(a). It consists of a phase accumulator (PA) and a phase-to- amplitude look-up table (LUT). The PA works as a phase wheel (PW), as shown in Fig. 7(b), and the LUT, basically a ROM, converts the digital phase into a digital amplitude. A cycle of the PW represents 360° and the points on the PW correspond to the content of the PA. At each system clock, the PW spins anticlockwise by an angle of the FTW points on its current value. It is exactly the output phase of the DDS at this moment. Thus, the relation between two consecutive output phases, namely θ_out(n) and θ_out(n+1), can be expressed as (10). Then the discrete transfer function of the DDS can be deduced as (11).

     (10)

   (11)

Fig. 7. Principle of the DDS: (a) DDS diagram; (b) phase wheel.

(a)

(b)

The DDS works as an integrator as well. Therefore, it achieves the same result as other VCOs and outputs an in-phase angle. Moreover, it can export an in-phase waveform and is suitable for hardware implementation.

Ⅲ. IMPLEMENTATION OF THE ADPLL

A. OSG

1) Discretization of the SOGI:

In this paper, the ADPLL is discretized by the zero-order hold (ZOH) method. Its transfer function ø(s) is (1-e^-Ts)/s, where T_s is a sampling time. Therefore, the discrete results of the SOGI are:

   (12)

By replacing k with and bringing it to a canonical form, the discretization of the SOGI can be derived as follows:

     (13)

where:

2) Parameter Design of the SOGI:

Based on the analysis in section II, an optimal compromise between the dynamic speed, overshoot and harmonic rejection is crucial to determining the k value. As a result, the parameter k is selected as to achieve a good comprehensive performance of the SOGI. Moreover, the values of k in the four SOGI blocks are all set in this optimal tradeoff value. The parameter ω₀ in the PFD is a constant and is equal to 100π. However, in the CAF SOGI it is adjustable and the initial value is set to 100π as well.

3) Parameter Design of the PFD:

The PFD is based on a zero-crossing detecting technique and the counter clock frequency is set at 1MHz. The measurement precision is up to 0.0001Hz for the power frequency signals. Thus, the input frequency can be exactly measured by detecting every zero-crossing of V_αr, and the center frequency of the CFA SOGI can be adjusted twice a cycle. Considering the settling time of the SOGI, usually more than half a cycle, the adjusting time is enough.

B. PD

1) Configuration of the CORDIC:

The CORDIC block works as a comparator and the discrete transfer function is displayed in (14), where k_PD is the gain of the PD and is equal to the input amplitude.

   (14)

In this paper, the CORDIC is configured to operate in the vector rotation mode and it is implemented with a parallel architectural to reduce latency. It features phase error detection with a data width of 24 bits. The gain k_PD is equal to 1.

2) Parameter Design of the SW:

As shown in (7), the output X^’ is equal to -A in the steady state, while the normal value is a relatively big value (≈0). Therefore, the boundary value X_JD can be set at -0.5A. It is equal to -0.5 in this paper.

C. VCO

In this paper, the DDS is equipped with a 24-bit phase accumulator and a 1MHz internal clock. The central frequency tuning word (FTW₀) is set at 839. Therefore, its gain and frequency resolution are equal to 0.3745 and 0.0596Hz, respectively.

D. LF

1) Discretization of the Pi:

The PI is discretized by the ZOH method and the result is:

   (15)

2) Optimization Design of the Pi:

In the digital circuits, loop delays are unavoidable and usually a side effect to pipelining, filtering or inner-loop mechanisms. Each delay increases the system order, limits the stability region and deteriorates the transient performance. Hence, a system analysis with consideration of the delays is necessary. As designed, there is no feedback between the OSG and the PLL loop. Therefore, their designs can be separate. Fig. 8 shows the discrete-time model of the ADPLL loop. The delays from the CORDIC and DDS are described as z^-D1 and z^-D2, respectively. In fact, D₁ is equal to 2 and D₂ is equal to 3. In addition, D_PD(z), D_PI(z) and D_VCO(z) are all known. Then the discrete close-loop transfer function of the ADPLL loop can be deduced as (16).

   (16)

Fig. 8. Discrete-time model of the ADPLL loop.

Since k_VCO and T_s are known, based on (16), a root-locus diagrams of the ADPLL loop with variations of k_p and k_i can be obtained by MATLAB as Fig. 9(a)-(b).

Fig. 9. Root-locus diagrams of the ADPLL loop: (a) k_i=10.2012×10⁶, and k_p varies from 22937.6 to 2293760, (b) k_p=229376, and k_i alters from 10.2012×10⁵ to 10.2012×10¹⁰.

(a)

(b)

Note that the ADPLL is stable on a large scale. In order to achieve a fast response speed, choosing good k_p and k_i values in the unit circle is crucial. As a result, the parameters of the PI are selected as k_p=229376 and k_i=10.2012×10⁶, which directly results in a high system bandwidth while still guaranteeing system stability.

Ⅳ. PERFORMANCE ANALYSIS OF THE ADPLL

A. Dynamic Analysis

As analyzed above, the ADPLL loop has a high system bandwidth via an optimize parameter design. In this case, according to (16), a step response diagram of the ADPLL loop can be plotted as Fig. 10. Note that the ADPLL loop has a fast response speed. A 5% settling time for the step response is about 17us. In addition, the overshoot is also very small. This means that the dynamic performance of the ADPLL is mainly determined by the OSG block. The proposed OSG is a sixth-order integrator and the close-loop transfer functions are as follows:

    (17)

Fig. 10. Step response diagram of the ADPLL loop.

Unlike the frequency-locked assumption in other papers, the center frequency ω₀ of the OSG can always lock the grid frequency ω_in. Therefore, V_α and V_β can be derived as:

   (18)

v_α and v_β are momentary components of the OSG, which are functions of A, k, ω₀ and t. Then applying the CORDIC algorithm (5) to (18) yields the V_d and V_q signals as (19), where v_d and v_q are also momentary components.

    (19)

In the steady state, V_q converges to zero. This means the ADPLL successfully locks the phase of the grid voltage. Thus, the dynamic response of V_q is the phase-locked dynamic of the ADPLL. In addition, V_d yields the grid voltage amplitude, whose dynamic reflects the dynamic of V_out. Considering the complexity of the mathematical expression for V_d and V_q, their step response diagrams are obtained by Simulink as Fig. 11, and the corresponding response of V_out is also given in Fig. 11. Note that the steady-state value of V_q, V_d and V_out are all zero. For the step signal, according to (17) and (6), V_d and V_q both equal zero in the steady state. Therefore, V_out also converges to zero. Finally, the PLL tends to a steady state. The 5% settling time of the ADPLL for the unit step signal is about 30ms. In addition, the maximum overshoot is about 0.8 p.u.. The whole process is relatively smooth without a big mutation. Thus, the ADPLL shows a good transient performance.

Fig. 11. Step response diagrams of V_d, V_q and V_out.

B. Robust Analysis

The proposed OSG generates an orthogonal signal for the PD and works as a pre-filter to eliminate harmonics, dc offset and other interferences. Thus, according to (17), Bode diagrams of the OSG can be draw by MATLAB as Fig. 12.

Fig. 12. Bode diagrams of the proposed OSG.

The plots show that the proposed OSG exhibits a good filtering feature. The dc offset has been completely removed. The 3th, 5th and 7th harmonics for G_α and G_β are also decayed with slopes of -38.9dB and -29.3dB, -60.9dB and -46.9dB, and -75.6dB and -58.6dB, respectively. Its rejection capabilities of dc offset and harmonics are improved when compared with the SOGI.

Simulation results also demonstrate the robustness of the ADPLL. When the input voltage (Acosθ_in) has 0.05p.u third- order, 0.05p.u fifth-order and 0.04p.u seventh-order harmonic components (8.12% Total Harmonic Distortion/ THD) and a 40% dc offset, the ADPLL still achieves good signal-tracking. A harmonic analysis of the ADPLL output V_out via a Fast Fourier Transform (FFT) shows that its THD has been greatly reduced and that only 0.06% harmonics remain. The detected maximum phase error is about 0.184°. This satisfies the Total Vector Error (TVE) 1% standard (a maximum phase error below 0.57°) [21]. Therefore, the ADPLL is robust to harmonics and dc offset.

Ⅴ. EXPERIMENTAL RESULTS

The ADPLL is designed and coded using Verilog and implemented on a Nexys4 DDR™ FPGA Board from Xilinx. As mentioned above, the sampling frequency is fixed to 1MHz. The total FPGA resources used on this implementation include Slice Registers 2320, Slice LUTs 7856, Occupied Slices 2496, RAMB36E1 1, RAMB18E1 1, DSP48E1s 136 and BUFG 3. Fig. 13 shows experimental results under the actual grid voltage, which has distortion and the THD is 1.7%. It is sampled by hall sensor and transferred to the FPGA via A/D converters.

Fig. 13. Experimental results of the ADPLL under grid voltage: (a) V_in, V_out, X_PI and A_m signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

A FFT analysis demonstrates that the output wave V_out is a power signal and that the harmonic components are markedly attenuated. The detected phase error θ_e (in this case, use the PD output V_q as θ_e) converges to zero. The amplitude A_m and frequency f_out are also zero errors. They all demonstrate the effectiveness and practicability of the ADPLL under the actual grid voltage.

In order to fully evaluate the performance of the ADPLL, experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, must be carried out. Considering the difficulties of implementing these distortions on grid voltage, using a FPGA to emulate the distortional grid voltage has great meanings. In this case, the input phase angle θ_in can be obtained so that the phase error can be exactly determined via a subtraction (θ_in-θ_out). The power frequency voltage V₅₀ can also be acquired. Therefore, the following experiments are all based on the emulated grid voltage, which is generated by the FPGA and directly fed to the ADPLL. The input signal V_in, output signal V_out, PI output signal X_PI, detected frequency f_out, detected phase error θ_e and detected magnitude A_m are all monitored by an oscilloscope through two 16-bit D/A converters. Fig. 14 shows the experimental set-up.

Fig. 14. Photo of the experimental set-up.

A. Dynamic Experiments

1) Voltage Sag: Fig. 15 shows experimental results in response to a 40% voltage sag in the grid voltage. Although there is a deviation of 0.1Hz in the detected frequency and an overshoot of 8.6° in the detected phase error, the ADPLL attains a new steady state in 18ms without any amplitude overshoot.

Fig. 15. Experimental results of the ADPLL for voltage sag: (a) V_in, V_out, X_PI and A_m signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

2) Phase Jump: Fig. 16 shows experimental results in response to a 90° phase jump in the grid voltage. Due to this disturbance, there is a frequency overshoot of 7Hz, an amplitude overshoot of 0.22 per unit (p.u) and a phase error overshoot of 20.1°. Note that the 5% settling time under this condition is roughly 39ms.

Fig. 16. Experimental results of the ADPLL for a phase jump: (a) V_in, V_out, X_PI and θ_in signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

3) Frequency Step: Fig. 17 shows the experimental results in response to a frequency step from 50Hz to 55Hz. Note that the detected frequency smoothly converges to its new steady-state value in 27ms. The transient overshoots for the detected phase error and amplitude are 15.1° and 0.15p.u, respectively. In fact, the ADPLL is able to achieve a wider frequency variation from 42Hz to 62Hz, which satisfies international grid-tied standards [3].

Fig. 17. Experimental results of the ADPLL for a frequency step: (a) V_in, V_out, X_PI and f_out signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

4) Comparison: In this paper, the Delay-PLL, Deri-PLL, Park-PLL, SOGI-PLL, DOEC-PLL, CCF-PLL and TPFA- PLL are selected. Considering that these established PLLs have been researched in other studies and are not the focus of this paper, the corresponding experimental data is directly quoted from paper [6]. The transient performances of these PLLs against various distorted grid conditions are presented in Table II.

TABLE II DYNAMIC PERFORMANCE COMPARISON OF PLLS

	Settling time(5%) /Frequency overshoot/Peak phase error
	Voltage Sag	Phase Jump	Frequency Step
ADPLL	18ms/0.1Hz/8.6°	39ms/7.0Hz/20.1°	27ms/0.0Hz/15.1°
Delay-PLL	22ms/2.9Hz/3.3°	40ms/17.0Hz/16.2°	70ms/2.2Hz/16.0°
Deri-PLL	0.0ms/0.0Hz/0.0°	40ms/17.0Hz/16.0°	70ms/2.0Hz/12.5°
Park-PLL	60ms/2.5Hz/6.7°	81ms/18.9Hz/37.0°	72ms/2.5Hz/17.0°
SOGI-PLL	55ms/2.9Hz/6.0°	70ms/22.0Hz/25.0°	53ms/2.1Hz/15.5°
DOEC-PLL	16ms/0.7Hz/2.0°	82ms/18.9Hz/40.5°	72ms/2.5Hz/17.0°
CCF-PLL	30ms/10Hz/5.5°	104ms/16.6Hz/17.8°	75ms/8.1Hz/21.0°
TPFA-PLL	15ms/1.5Hz/3.5°	105ms/17.1Hz/28.8°	90ms/2.6Hz/25.0°

Under a voltage sag condition, all of the PLLs except the Park-PLL, SOGI-PLL and CCF-PLL show a relative response speed. The Park-PLL, SOGI-PLL and CCF-PLL use a frequency feedback loop to realize frequency self-adaption, which simultaneously worsens the dynamics. Therefore, in the other two cases, they also show a slow dynamic. The DOEC-PLL also employs a Park-based OSG. However, it has a dc compensation loop to remove dc offset, which is beneficial to the amplitude tracking. Thus, the response speed of the DOEC-PLL for a voltage sag is better than the Park-PLL. Meanwhile, in the other two cases, they are almost same. The Delay-PLL, Deri-PLL and TPFA-PLL all avoid the frequency feedback loop. The Delay-PLL and Deri-PLL are based on a fixed T/4 delay algorithm and a derivator, respectively. Both of the algorithms are simple with no extra feedback loop and no filter. Therefore, their responses for all of the cases are relatively fast. The TPFA-PLL is based on Park’s and inverse Park’s transformations. In addition, two extra MAFs are needed to filter unwanted frequency components. Thus, it obtains a filtering ability for harmonics and other interferences. However, do to this, its response speed for frequency step and phase jump is slow while for voltage sag it remains fast due to its insensitivity to amplitude. When compared to these PLLs, the ADPLL almost always shows the best dynamic performance. It shows a relatively fast response, less frequency overshoot and smooth dynamics. Under the frequency step condition, the response time is greatly shortened with zero frequency overshoot and a small phase overshoot.

B. Robust Experiments

1) Dc Offset: Fig. 18 evaluates the dc rejection capability of the ADPLL. A sudden dc offset of 40% is injected into the grid voltage at 30ms. Although transient errors in the detected phase error (12.96°), frequency (1Hz) and amplitude (0.3p.u) occur, the ADPLL attains a new steady state in 28ms with zero steady-state errors. That is to say, the ADPLL has a complete elimination capability in terms of dc offset.

Fig. 18. Experimental results of the ADPLL for dc offset: (a) V_in, V₅₀, V_out and X_PI signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

2) Harmonics Distortion: Fig. 19 evaluates the harmonic filtering capability of the ADPLL in the presence of 0.05p.u third-order, 0.05p.u fifth-order and 0.04p.u seventh-order harmonic components in the grid voltage (THD=8.12%). Note that the FFT analysis demonstrates that the 3th, 5th and 7th harmonics in the output signal are greatly reduced and that only a few harmonics are left. However, it still results in a small oscillation in the detected phase error and amplitude. The maximum phase error and amplitude error are below 0.35° and 0.014p.u, respectively. This still satisfies the TVE 1% standard [21]. Thus, the ADPLL is robust to harmonics and dc offset.

Fig. 19. Experimental results of the ADPLL for harmonics distortion: (a) V_in, V₅₀, V_out, X_PI and V_outFFT signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

3) Combined Disturbances: Fig. 20 verifies the applicability of the ADPLL to sine signal. In this test case, a sine signal (Asinθ_in) along with harmonics and a dc offset is considered. Note that in the steady state, the output signal is well coincident to the input sine signal. In addition, the detected phase, frequency and amplitude errors all converge to zero. This means that the ADPLL can lock the sine-signal phase well. At 30ms, a 0.4p.u dc offset and 0.05p.u third-order and 0.05p.u fifth-order harmonics are injected into the grid voltage. After 40ms, the ADPLL reaches its new steady state with a peak-peak phase error of 0.32° and a peak-peak amplitude error of 0.002p.u, which also satisfies the TVE 1% standard [21].

Fig. 20. Experimental results of the ADPLL for combined disturbances: (a) V_in, V₅₀, V_out, X_PI and V_outFFT signals, (b) θ_e, f_out and A_m signals.

(a)

(b)

4) Comparison: The robust performances of the PLLs under different abnormalities are presented in Table III.

TABLE III ROBUST PERFORMANCE COMPARISON OF PLLS

	Peak-peak frequency error/ Peak-peak phase error
	DC offset	Harmonics Distortion	Combined Disturbances
ADPLL	0Hz/0°/0p.u	0Hz/0.35°/0.005p	0Hz/0.32°/0.002p.u
Delay-PLL	1.6Hz/1.7°/-	3.8Hz/0.8°/-	-
Deri-PLL	1.5Hz/1.5°/-	8.7Hz/2.2°/-	-
Park-PLL	1.5Hz/1.8°/-	1.1Hz/0.4°/-	-
SOGI-PLL	1.7Hz/1.9°/-	1.2Hz/0.4°/-	-
DOEC-PLL	0.0Hz/0.0°/-	0.9Hz/0.3°/-	-
CCF-PLL	3.2Hz/3.8°/-	1.5Hz/0.6°/-	-
TPFA-PLL	1.2Hz/1.2°/-	0.0Hz/0.0°/-	-

When a dc offset occurs in grid voltage, all of the PLLs except the ADPLL and DOEC-PLL suffer from steady-state errors for lake of dc rejection ability. On the other hand, the ADPLL and DOEC-PLL use a CFA SOGI structure and a dc compensation algorithm to remove the dc offset, respectively. Both of them show a good dc rejection performance with zero steady-state errors. They also show a similar harmonic filtering performance. However, the ADPLL has a better dynamic response since it does not have an additional feedback loop. Under the harmonics distortion scenario, all of the PLLs except for the Delay-PLL, Deri-PLL and CCF-PLL meet the TVE 1% standard [21]. The Delay-PLL and Deri-PLL are based on a simple OSG with no filtering capability. The CCF-PLL uses a complex-coefficient filter as an OSG. However, its filtering capability for 8.12% harmonics is still not enough. Therefore, their filtering capabilities must be enhanced. Among these PLLs, the TPFA-PLL shows the best harmonic rejection capability, followed by the DOEC-PLL and ADPLL, then the Park-PLL and SOGI-PLL. However, the TPFA-PLL is sensitive to dc offset. Thus, the ADPLL shows the best robust performance in the presence of harmonics and dc offset. Moreover, the ADPLL can extract amplitude information of the utility voltage and achieve an accurate phase tracking of sine and cosine signals. By comparison, the ADPLL shows the best comprehensive properties.

Ⅵ. CONCLUSION

In this paper, a single-phase ADPLL based on a FPGA has been presented to ensure a fast dynamic response. In order to obtain high steady-state accuracy under dc offset, harmonics and frequency-varying conditions, a new OSG is applied. It contains no extra feedback loop, which avoids the undesired tradeoff, improves the dynamic speed and enhances stability. A parameter optimization design with consideration of loop delays is also employed to obtain a good transient performance and to guarantee system stability. Theoretical analysis and experimental investigations on the performance of the ADPLL are also carried out. The obtained results demonstrate that the ADPLL, in addition to its sufficient rejection capabilities of harmonics and dc offset, has a fast dynamic response (less than 39ms) and a good robustness (below 0.35°). In particular, under a frequency step of +5th, it shows a smooth dynamic performance without frequency deviation and less phase error overshoot. In addition, the settling time (27ms) has shorten more than twice that of other established PLLs.

On the other hand, this design belongs to all digital PLLs. It can be easily embedded in other systems to realize rich functionality and implementation as low-cost chips. Looking at the trends of the grid synchronization techniques, the digitalizing and integrating of the PLL technique is conducive to the promotion of grid-tied technology and the development of the power electronics industry. Therefore, the proposed ADPLL is a competitive solution in engineering applications.

ACKNOWLEDGMENT

The project is supported by the National Science Foundation of China (61474098 and 61674129).

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Peiyong Zhang was born in Anqing, China, in 1977. He received his Ph.D. degree from Zhejiang University, Hangzhou, China, in 2004. In the same year, he joined the Institute of VLSI Design, Zhejiang University. Since 2004, he has been working on VLSI designs for manufacturability.

Haixia Fang was born in Zhejiang, China, in 1990. She received her B.S. degree in Electronic and Information Engineering from Zhejiang University, Hangzhou, China, in 2013. She is presently working towards her M.S. degree in the Institute of VLSI Design, Zhejiang University. Her current research interests include phase lock loops and high speed SerDes.

Yike Li was born in Sichuan, China, in 1996. He received his B.S. degree in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2018. He is presently working towards his M.S. degree in the Institute of VLSI Design, Zhejiang University. His current research interests include low-power high-speed transceiver modules in integrated circuits.

Chenhui Feng was born in Pingtan, China, in 1990. He received his B.S. and Ph.D. degrees from Zhejiang University, Hangzhou, China, in 2011 and 2016, respectively. He joined the College of Physics and Information Engineering, Fuzhou University, Fuzhou, China, in 2016. His current research interest include on-chip parameter extraction.