사각형입니다.

https://doi.org/10.6113/JPE.2018.18.5.1595

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Hierarchical Control Scheme for Three-Port Multidirectional DC-DC Converters in Bipolar DC Microgrids


Taha Ahmadi*, Mohsen Hamzeh**, and Esmaeel Rokrok


†,*Department of Electrical and Electronics Engineering, Lorestan University, Lorestan, Iran

**School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran



Abstract

In this paper, a hierarchical control strategy is introduced to control a new three-port multidirectional DC-DC converter for integrating an energy storage system (ESS) to a bipolar DC microgrid (BPDCMG). The proposed converter provides a voltage-balancing function for the BPDCMG and adjusts the states of charge (SoC) of the ESS. Previous studies tend to balance the voltage of the BPDCMG buses with active sources or by transferring power from one bus to another. Furthermore, the batteries available in BPDCMGs were charged equally by both buses. However, this power sharing method does not guarantee efficient operation of the whole system. In order to achieve a higher efficiency and lower energy losses, a triple-layer hierarchical control strategy, including a primary droop controller, a secondary voltage restoration controller and a tertiary optimization controller are proposed. Thanks to the multi-functional operation of the proposed converter, its conversion stages are reduced. Furthermore, the efficiency and weight of the system are both improved. Therefore, this converter has a significant capability to be used in portable BPDCMGs such as electric DC ships. The converter modes are analyzed and small-signal models of the converter are extracted. Comprehensive simulation studies are carried out and a BPDCMG laboratory setup is implemented in order to validate the effectiveness of the proposed converter and its hierarchical control strategy. Simulation and experimental results show that using the proposed converter mitigates voltage imbalances. As a result, the system efficiency is improved by using the hierarchical optimal power flow control.


Key words: Bipolar-type DC microgrid, Burst-mode control, Efficiency optimization, Hierarchical control, Multidirectional converters, Three-port converter (TPC), Voltage balancer


Manuscript received Feb. 24, 2018; accepted May 19, 2018

Recommended for publication by Associate Editor Fuxin Liu.

Corresponding Author: esmaeel.rokrok@gmail.com Tel: +98-66-33120005, Lorestan University

*Dept. of Electrical and Electronics Eng., Lorestan University, Iran

**School of Electrical & Comp. Eng., College of Eng., Univ. of Tehran, Iran



Ⅰ. INTRODUCTION

There has been an increased focus in research on DC microgrids, since they are seen as a useful technology to prepare an efficient interface between renewable energy sources, DC loads and ESSs [1]. Furthermore, a DC microgrid has fewer power electronic conversion stages when compared to an AC microgrid [2]. Therefore, they have increased reliability and stability [3, 4]. DC microgrids are categorized into two types [5]: unipolar-type and bipolar-type [6]. Unipolar DC microgrids have one voltage level in a two-wire DC distribution network. On the other hand, BPDCMGs have two voltage levels in a three-wire DC distribution network (positive, neutral and negative). BPDCMGs are suggested to achieve higher efficiency, better power transmission capability and improved reliability [6].

In addition to the advantages of BPDCMGs, they also present some technical challenges. In fact, when the loads are connected to the upper and lower terminals of a BPDCMG, they may have different powers. Therefore, the voltage of the terminals may drift from the rated value resulting in a voltage imbalance [7]. To quantify this voltage imbalance, the line voltage unbalances rate equation (LVUR) is utilized [2].

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그림입니다.
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원본 그림의 크기: 가로 110pixel, 세로 64pixel and 그림입니다.
원본 그림의 이름: CLP000017c00004.bmp
원본 그림의 크기: 가로 113pixel, 세로 68pixel are the positive and negative buses voltages. In [8], various interlink converters (ICs) have been proposed. These circuits tend to balance the voltage at only one end of the BPDCMG. The main disadvantages of these structures are as follows. 1) A reduction of system reliability due to supplying loads using a single converter. 2) In case of the island mode, when the IC is disconnected from the AC grid, the voltage balancer control system should be turned into the island mode, which causes a significant voltage transient [9]. 3) In a BPDCMG with a long feeder length, this method cannot make the neutral line current reach zero. To compensate these issues, a new structure was proposed in [7]. In this structure, each of the distributed generator (DG) units provides a voltage-balancing function. In addition, the interlinking converter is connected to the BPDCMG. Due to an increasing number of converters, the system efficiency can be decreased. However, this topology improves the voltage balancing. In [2], an interleaved DC-DC converter is introduced to mitigate the unbalanced voltage. The advantage of this method is that there is no need for an active source as a compensator. In this regard, since batteries play an important role in BPDCMGs, it is possible to achieve a new structure for the battery converter in order to mitigate unbalanced voltage in addition to the charging and discharging of batteries. Therefore, the new converter has the following benefits. 1) Enhancing the BPDCMG loadability due to its ability to transfer terminal loads to another terminal. 2) Reducing the number of converters by integrating a voltage balancing converter and a battery converter. 3) Reducing the current of the neutral line and its associated power losses, while IC converters cannot eliminate the neutral line current for a BPDCMG with a long feeder length, since they attempt to balance the voltage at only one end of the BPDCMG [2]. 4) Balancing the possibility of voltage in the island condition of the BPDCMG by disconnecting the interlink converter.

A family of non-isolated DC-DC three-port converters (TPCs) for integrating renewable-energy sources (RESs) and an energy storage system into a DC bus is proposed in [10]. In [11], a multi-port converter, which integrates the energies of a PV panel, fuel cell and a battery, is introduced for supplying local loads. In [12], a three-port DC-DC boost converter is introduced. The presented converter interfaces two unidirectional input power ports and a bidirectional port for a battery. This converter can supply loads, and charge or discharge a battery by the sources connected to ports individually or simultaneously. Since multiple voltages are required for some applications, several studies have been done on different types of single-input multiple-output converters [13]. In [14], a new three-port DC-DC converter, based on the flyback converter, is introduced to integrate PV and battery systems to feed the loads connected to the converter. The flyback converter has many features, such as a high-output voltage range, isolation of the port voltages and a cost effective structure [15]. As can be seen, although a lot of investigations have been done on TPCs, these topologies are mostly designed to integrate multiple energy sources in certain polarities for consuming loads in other polarities. In addition, they cannot transfer power from all three polarities to the other one. Therefore, solutions for integrating a battery and a BPDCMG are still limited.

Within this context, this paper focuses on the voltage balancing of BPDCMGs and proposes a new isolated three-port multidirectional converter integrating a battery system with a BPDCMG. This converter has the capability of balancing positive and negative terminal voltages, in addition to charging and discharging a battery.

Due to the ability of the proposed three-port multidirectional converter to transfer current between two terminals, it is possible to supply positive or negative loads by positive and negative RESs. Furthermore, in battery charging conditions, the proposed three-port multidirectional converter has the ability to share the battery charging current between positive and negative RESs. Therefore, the proposed three-port multidirectional converter can be considered as a parallel-input-parallel-output converter. One challenging issue is the current sharing control among the paralleled outputs of RESs converters. Common current distribution methods consist of master-slave control [16], average current control [17], droop control, etc. Master-slave control, average current control and others methods require the transmission of current signals with high speed communication lines, which are not required in droop control [1]. In [7] and [6], droop methods have been introduced for current sharing in microgrids. Droop control is a decentralized strategy that does not need communication links and has many benefits such as higher reliability, flexibility, simplicity and inexpensiveness [18]. Although droop control methods make autonomous current sharing easier, they does not guarantee optimum system operation [19]. Optimum system operation can be achieved by considering the efficiency [20]-[22], repair and maintenance costs [23], fuel cost [24]-[26], etc. In this paper, optimization is based on the interconnect converters efficiency curves of RESs to the BPDCMG. In particular, it has been found that converter efficiency under light load conditions is relatively low [27]. In [28], a coordinative control strategy for enhancing the efficiency of paralleling source converters under light load conditions is proposed. In [27], a new tertiary control level including an optimization method for achieving efficient operation is proposed for paralleled DC–DC converters. Similarly, this paper proposes a hierarchical control method for adjusting the operation points of RESs converters. In addition, the proposed three-port multidirectional converter optimizes the sharing proportion among converters, and achieves a higher system efficiency and better battery power management.



Ⅱ. DESCRIPTION OF THE PROPOSED THREE-PORT MULTIDIRECTIONAL CONVERTER

The structure of an isolated BPDCMG is shown in Fig. 1(a). In the BPDCMG, loads can be connected between the positive and negative terminals, the positive and neutral terminals, and the negative and neutral terminals. Since the last two connections types may cause voltage imbalances between the positive and negative terminals, it is necessary to utilize a voltage balancing strategy. Therefore, the proposed three-port multidirectional converter is integrated into the BPDCMG to balance the voltages of the positive and negative terminals. In the considered the BPDCMG, it is assumed that the RESs are connected by their respective converters, and that the characteristics of these converters are different. Therefore, each of them has an independent control system. The proposed three-port multidirectional converter is shown in Fig. 1(b). As can be seen in this figure, in the primary side of the transformer,그림입니다.
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원본 그림의 크기: 가로 104pixel, 세로 66pixel, 그림입니다.
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원본 그림의 크기: 가로 83pixel, 세로 69pixel and 그림입니다.
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원본 그림의 크기: 가로 64pixel, 세로 68pixel denote the output voltage filter capacitors, 그림입니다.
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원본 그림의 크기: 가로 91pixel, 세로 73pixel and 그림입니다.
원본 그림의 이름: CLP000017c0000f.bmp
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원본 그림의 크기: 가로 116pixel, 세로 76pixel and 그림입니다.
원본 그림의 이름: CLP000017c00011.bmp
원본 그림의 크기: 가로 120pixel, 세로 71pixel show the terminals voltages, and 그림입니다.
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원본 그림의 크기: 가로 178pixel, 세로 72pixel and 그림입니다.
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원본 그림의 크기: 가로 83pixel, 세로 50pixel denote for the primary, secondary and tertiary turns number. The proposed converter is analyzed under the island operating mode of the BPDCMG. In this operating mode, the interplay of the battery and the RESs takes on a considerable role. The proposed three-port multidirectional converter usually operates under constant-voltage mode control, which causes additional power loss, such as switching loss and conduction loss. To increase system efficiency and reliability, the proposed three-port multidirectional converter operates under the proposed two dimension (2D) burst mode or in the skip mode control method. The burst control mode operates using the cycle-skipping method to reduce the switching loss in low power switching converters and to increase the operational efficiency. During cycle skipping, each of the skips of the switching can be started at the minimum-allowed voltage value and stopped at the maximum-allowed-voltage value [29]. Fig. 1(c) shows the four operation modes of the proposed three-port multidirectional converter for operating in the BPDCMG. To simplify the analysis of the proposed three-port multidirectional converter, it is assumed that the indexes ‘I’ and ‘J’ are defined as: 그림입니다.
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원본 그림의 크기: 가로 344pixel, 세로 65pixel.


Fig. 1. The structure of an isolated BPDCMG: (a) Typical isolated BPDCMG equipped with the proposed converter, (b) Proposed three-port multidirectional converter utilized for interfacing a battery to the buses of the BPDCMG, (c) Operation modes of the proposed converter.

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(a)

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(b)

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(c)


A. Mode 1: Natural Balance Mode

Based on the idea of the burst mode, a new 2D burst mode control scheme is proposed for this converter. As shown in Fig. 1(c), when VRL,I and V RL,J are inherently preserved between Vmin-allowed and Vmax-allowed, the proposed converter does not operate and the battery is isolated from the BPDCMG during this time. In this mode, the RESs are responsible for their own DC bus voltages.


B. Mode 2: Battery Charging Mode

When 그림입니다.
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원본 그림의 크기: 가로 743pixel, 세로 92pixel and 그림입니다.
원본 그림의 이름: CLP000010b80001.bmp
원본 그림의 크기: 가로 726pixel, 세로 72pixel, the RESs generation potential is more than the load demands in each of the two terminals. In this mode, if the battery does not reach to its maximum SoC level, the redundant power of one or both of the terminals may be utilized to charge the battery. Since this case occurs under light load conditions, in order to provide the possibility to achieve maximum system efficiency, the proposed converter should be able to transfer power between the two terminals in addition to charging the battery simultaneously and with a different power sharing. In this case, since the RESs are responsible to regulate the DC bus voltages, the proposed converter operates under voltage control and can be modeled as a voltage source. Fig. 2(a) shows an equivalent circuit under this operational mode.


Fig. 2. Proposed three-port multidirectional converter in mode 2 assuming I=1 and 그림입니다.
원본 그림의 이름: CLP000010b80003.bmp
원본 그림의 크기: 가로 155pixel, 세로 57pixel: (a) Equivalent circuit, (b) Switching pattern (assuming the battery demand has more current than RL,J demand), (c) State I, (d) State II, (e) State III, (f) State IV.

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(a)

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(b)

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(c)

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(d)

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(e)

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(f)


There is no possibility of simultaneous transmission of power from the positive to negative terminals or from the negative to positive terminals. In other words, in the case of power transmission from the positive terminal to the negative terminal, in order to share the load power of RL2, the RES2 power does not sent back the power to the positive terminal. This condition is also available for power transmission from the negative terminal to the positive terminal. Therefore, (2) and (3) are obtained for the two aforementioned conditions.

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원본 그림의 크기: 가로 744pixel, 세로 89pixel   (2)

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In general, the currents are given by the following equations:

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Since the battery is charged by RES1 and RESJ through the proposed converter, and the RL,J voltage is directly regulated by RESJ and RESI through the proposed converter. Therefore, the proposed converter should regulate the voltages V5 and V6 on the battery side and the voltage V(I+2) on the terminal J. The voltage error is defined as (6).

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원본 그림의 크기: 가로 959pixel, 세로 78pixel   (6)

According to the switching times of SI2, SI3, SJ2, SJ3 and Sp1, as shown in Fig. 2(b), the converter has the following four distinctive states. In this figure, it is assumed that 그림입니다.
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원본 그림의 크기: 가로 238pixel, 세로 63pixel.

State I (Fig. 2(c)): SI2, SI3, SJ2 and SJ3 are turned ON. Therefore, Lm absorbs energy from VI +VJ. The coefficient K1 is directly related to eV(J+4).

State II (Fig. 2(d)): SI2 and SI3 stay ON. Therefore, Lm absorbs energy from VI. The coefficient K2 is directly related to the maximum amount of eV(I+4) and eV(I+2). In Fig. 2(b), it is assumed that 그림입니다.
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원본 그림의 크기: 가로 342pixel, 세로 66pixel, since SI2 is turned OFF earlier than SP1.

State III (Fig. 2(e)): SP1 and SI2 stay ON and Lm sends the absorbed energy to the battery and RL,J through DP2, Sp1, SI2, DI1, DI3 and the freewheeling diode Dm. In this state, the coefficient K3 is related to the minimum amount of eV(I+4) and eV(I+2). In Fig. 2(b) it is assumed that 그림입니다.
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State IV (Fig. 2(f)): since the battery demands more current than RL,J, SI2 is kept OFF and Sp1 is kept ON. Alternatively, if RL,J absorbs more current than the battery, SP1 is kept OFF and SI2 is kept ON.


C. Mode 3: Buses Power Transferring Mode

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원본 그림의 크기: 가로 518pixel, 세로 92pixel and 그림입니다.
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원본 그림의 크기: 가로 749pixel, 세로 96pixel, RESI is responsible for regulating the DC terminals voltages and RESJ operates under the MPPT condition. Therefore, the converter transfers power from the terminal ‘I’ to the terminal ‘J’ under the voltage mode control. This is done to regulate the voltage of terminal ‘J’. The operation of this mode is defined as follows:

State I: SI2 and SI3 are turned ON. Therefore, the Lm current through the transformer increases linearly.

State II: When SI3 is turned OFF, the transformer magnetizing inductor current discharges on the load RLJ.


D. Mode 4: Battery Discharging Mode

When 그림입니다.
원본 그림의 이름: CLP000017c0002a.bmp
원본 그림의 크기: 가로 523pixel, 세로 91pixel and 그림입니다.
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원본 그림의 크기: 가로 393pixel, 세로 81pixel그림입니다.
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원본 그림의 크기: 가로 710pixel, 세로 84pixel, then the voltage value is in an acceptable range and the battery only regulates the RLJ voltage. The operation of this mode defined as follows:

State I: SP2 is ON. Therefore Lm absorbs energy form Vbat. During this state, the load currents are supplied by C1 and C2.

State II: S11 and S21 are ON and the absorbed energy is sent to the upper and lower loads.

State III: In this state the converter acts in the balancing function. If 그림입니다.
원본 그림의 이름: CLP00001a640003.bmp
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원본 그림의 크기: 가로 344pixel, 세로 56pixel is kept ON.



Ⅲ. CONTROL SYSTEM OF THE PROPOSED THREE-PORT MULTIDIRECTIONAL CONVERTER

Fig. 3(a) shows the voltage and current control loops of the upper and lower terminals. To adjust the transient response and to meet small steady-state error, the duty cycle to the output voltage small-signal transfer function is acquired using the average state-space method. These equations are written for power transmission from the battery to RL1. Therefore, the state-space equations for the two states of mode 3 (assuming그림입니다.
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원본 그림의 크기: 가로 721pixel, 세로 83pixel) are derived and averaged over one switching cycle. The state variables are the voltages of C1 (VRL1), and the inductor Lm current (iLm). The input vector is the source voltage that in this mode is the battery voltage (Vbat).


Fig. 3. Control system of the proposed three-port multidirectional converter: (a) Primary control scheme of the proposed three-port multidirectional converter, (b) Bode diagram of the plant transfer functions with and without compensation.

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(a)

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(b)


In the proposed converter, turns number of the transformer in each winding is equal. Therefore, the transfer function of the perturbed output voltage (그림입니다.
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원본 그림의 크기: 가로 120pixel, 세로 70pixel) versus the perturbed inductance current그림입니다.
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원본 그림의 크기: 가로 147pixel, 세로 80pixel and the perturbed inductance current versus the perturbed duty cycle (그림입니다.
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원본 그림의 크기: 가로 117pixel, 세로 79pixel), 그림입니다.
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원본 그림의 크기: 가로 714pixel, 세로 154pixel   (7)

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원본 그림의 크기: 가로 779pixel, 세로 150pixel          (8)


TABLE I SYSTEM PARAMETER VALUES

Parameter

Value

Inductor Lm

2.5 mH

Capacitor C1 and C2

200 μF

Duty cycle D

0.5

Load Rload

200 Ω

Transformer winding turns NP=Ns1=Ns2

1

Battery

2000 Ah, 400 V

Reference voltage (Vref)

400 V

Maximum voltage (Vmax)

408 V

Minimum voltage (Vmin)

392 V

Maximum-allowed voltage (Vmax-allowed)

404 V

Minimum-allowed voltage (Vmin-allowed)

396 V

Inductor current upper limit (iMAX)

10 A

Duty cycle upper limit (DMAX)

0.8


The transfer function of the voltage control system (Gcv(s)) and that of the current control system (Gcc(s)), shown in Fig. 3(a), are represented by (9) and (10).

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In order to avoid kicks in the control signal due to setpoint changes from the voltage control and the battery charge control strategy, an anti-windup transfer has been used. Using the model introduced in [30] and [31], the anti-windup transfer is achieved by adding (Iref,i – I’ref,i) to the integral coefficient term of Gcv(s). In this case, I’ref,i is the output value of the voltage control block and the index i represent the bus number.

With the parameters mentioned above, a Bode diagram of the open-loop and closed-loop control system is shown in Fig. 3(b). By analyzing the amplitude-frequency characteristic and phase-frequency response curves in the Bode diagram, it can be concluded that the designed controller provides a good stability margin for the system.



Ⅳ. HIERARCHICAL CONTROL ARCHITECTURE FOR LIGHT LOAD CONDITIONS

In order to improve the overall system efficiency under light load conditions, a hierarchical control strategy with virtual resistance optimization for efficiency enhancement and battery power management has been proposed. The structure of the hierarchical control is shown in Fig. 4. The primary control or droop control appears as an upper loop, over the voltage control loop. Voltage deviation is restored in the secondary control. Finally, tertiary control is normally responsible for power flow control. Furthermore, optimization techniques can be used in this level following up on the operation points of the converters and improving the operation of microgrids [27]. Droop controlled DC–DC converters act as a voltage source in series with a virtual resistance. The droop controller is located on top of the voltage control loop to connect several unites in parallel to share power between them. Therefore, the droop controller produces a proper reference for the voltage loop as (11).


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Fig. 4. Hierarchical control applied to the proposed converter.


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원본 그림의 크기: 가로 581pixel, 세로 91pixel is the terminal reference voltage. Furthermore, 그림입니다.
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원본 그림의 이름: CLP000010880006.bmp
원본 그림의 크기: 가로 483pixel, 세로 68pixel are the output current of the RESs and the VR values. The main disadvantage of droop control is its poor voltage regulation. According to (11), the voltage deviation in the primary control is intrinsic and depends on the output current. Therefore, secondary control has been proposed in order to solve this issue. The terminal bus voltage is obtained and compared with the reference voltage, 그림입니다.
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Then the new reference voltage can be obtained as (13).

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In the top layer, system data such as limits of the flow currents in the lines and converters, and limits of the generation power and voltage of the terminals and battery are received by the tertiary level. In this layer, the operation mode of the system is determined. Therefore, under light load conditions, the optimization algorithm finds the optimal load power sharing ratio. Virtual output resistances are the decision variables in this algorithm. Furthermore, a first-order Butterworth low-pass filter (LPF) is recommended for use in the tertiary control level and the BPDCMG to smooth the changing of VRs. In addition, a first-order Butterworth low-pass filter (LPF) is recommended for use in the tertiary control level and the BPDCMG to smooth the changing of VRs.



Ⅴ. OPTIMIZATION PROBLEM FORMULATION AND ANALYSIS

In a BPDCMG with many source units, the total efficiencies usually correspond to the conversion efficiency, which mostly consists of the switching losses of the semiconductor components. Since these losses are a function of the output current, the converter efficiency changes with the output current. IN a BPDCMG, different types of power sources with different DC-DC converters can be used to integrate the RESs to the BPDCMG. Therefore, the related converter efficiency curves are considered different [32].

In this regard, different efficiency curves, in order to demonstrate the performance of the proposed hierarchical control method, have been considered for the RES1 and RES2 converters. For example, a boost converter is considered as the RES1 converter [33]. In addition, the RES2 converter is assumed to be a one-switch forward converter [34]. A typical efficiency curve for a boost converter and a one-switch forward converter are introduced in [35] and [36]. Since the efficiency curve varies with respect to the input voltage and power of the converter, these efficiency curves are obtained theoretically at a voltage of 400V, taking into account the actual model of the switches and adding the parasitic series resistors of the inductors and capacitors. Similarly, theoretical efficiency curves of the representative operation modes of the proposed converter are shown in Fig. 5.


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Fig. 5. Efficiency vs. load current diagram of RESs converters and the proposed converter.


The proposed converter has many switches. However, since some switches always remain in ON state during the switching time, the conduction loss is small and the proposed converter can still achieve a high conversion rate. The highest efficiency is attained between 30% and 60% of the maximum output current. Therefore, by using this figure, the optimization algorithm obtains an appropriate ratio to share the load demands and the battery charging current in the BPDCMG. A two-term exponential model in MATLAB Curve Fitting Tool is utilized to change the data into function as (14)-(17).

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Where, 그림입니다.
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원본 그림의 크기: 가로 480pixel, 세로 71pixel, and 그림입니다.
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원본 그림의 크기: 가로 186pixel, 세로 57pixel are the efficiencies of the RES1 and RES2 converters and the proposed converter (in the DC terminal to DC terminal and it the battery to DC terminal power transferring modes). 그림입니다.
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Considering the equivalent circuit shown in Fig. 2(b), the power conversion losses of the RES converter and the proposed converter in mode 2 are calculated as follows:

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As can be seen from some typical efficiency curves of the RESs converters and the proposed three-port multidirectional converter in Fig. 5, under light load conditions, the efficiency of the converters is low, and if the converters share loads and battery charging currents equally, the system efficiency is the average efficiency of them all. With the help of the proposed three-port multidirectional converter, power can be transferred between two buses.

Furthermore, the battery charging current can be supplied by the RESs in such a way that the system efficiency is maximized. Therefore, as shown in Fig. 2(a), two series converters and a parallel converter operate to provide the current of each load. In addition, two series converters and two parallel converters operate to charge the battery. The general approach to increasing system efficiency is to differentiate the sharing proportion in mode 2 instead of equal sharing of the load current. The sharing proportion gains k1, k2 and kb for the loads (RL1 and RL2) and for charging the battery are defined as (22)-(24).

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These sharing proportions are used to evaluate the system power loss change, as shown in Fig. 6. Fig. 6(a) shows the system power losses with the kb changes at different battery charging current levels. Moreover, Fig. 6(b) shows the power losses while feeding various IRL2 by different values for the sharing proportion of the load current. As shown in this figure, under light load conditions, the power loss can be reduced by supplying the loads and battery charging currents in the non-equal sharing current. In addition, under different operating conditions, the optimum point also changes. This means that under different operating conditions, the optimal operating point of the system is different. Therefore, it is possible to determine this point using an optimal algorithm.


Fig. 6. Effect of various sharing ratios on the power loss for charging a battery and in mode 2: (a) Power loss for charging a battery for ibat=0.5~4A, i1=1.5A and i2=1.5A, (b) Power loss for feeding R2 for iRL2=0.15~0.85A and iRL1=1A.

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According to the above-mentioned analysis, the optimization problem can be defined as follows:

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Where IMAX and Ires, MAX are the maximum conversion current limits for each of the converters and the maximum current limit for each of the RESs. Considering the stability issues, the sharing ratio between any two possible sides (K1, K2 and Kb) i s limited between 1/20 and 20.

To optimize the model formulated above, an optimization algorithm should be selected. The selection of the algorithm is done according to an objective function analysis. For this purpose, global and local optimization methods are available. The fastest optimization algorithms only look for an optimal local point called the local optimization, such as steepest descent and Newton algorithms. For this reason, local optimization does not provide global optimal solutions. Therefore, to find a global optimum, global optimization algorithms such as a Genetic Algorithm (GA) are used. Therefore, this article used a GA to solve the optimization problem. The crossover rate is set to 0.8. In order to calculate in the minimum time given the acceptable quality of the final solution, Npop is set to 200.



Ⅵ. SIMULATION RESULTS

In order to verify the performance of the proposed converter and the hierarchical controller, a number of computer simulation studies are carried out in Matlab-Simulink. The parameters of the proposed converter are listed in Table 2.


TABLE II MAIN PARAMETERS OF THE EXPERIMENTAL SETUP

Parameter

Value

NP=Ns1=Ns2

15

Transformer wire size

AWG 18

Transformer core size

EE 55

Reference voltage (Vref)

24V

Maximum voltage (Vmax)

26V

Minimum voltage (Vmin)

21V

Maximum-allowed voltage (Vmax-allowed)

25V

Minimum-allowed voltage (Vmin-allowed)

23V

Battery

12V-100AH

Battery fully charged voltage

13.06 V

Switching Frequency

10kHz

Inductor Lm

0.288 µH

Capacitor C1 and C2

220 μF

Duty cycle upper limit (DMAX)

0.8

Inductor current upper limit (iMAX)

2.5A


It is assumed that, RES1 and RES2 are capable of producing a maximum power of 2kW. The cut-off frequency of the first-order Butterworth LPF implemented between the secondary and primary control is set to 400 Hz. Simulation waveforms of the voltages (V1, V2 and Vbat), the inductor current (iL) and the converter modes under different load currents are shown in Fig. 7. As analyzed previously, these simulations were carried out in four different operational modes.


Fig. 7. Simulation results: (a) Modes, (b) Transformer inductor current, (c) Voltage of the battery, (d) Output voltage of the negative and positive terminals, (e) Load currents under various load currents, (f) 그림입니다.
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(f)


A. 0~0.02: NBM Mode

When RL1 = 80Ω and RL2 = 80Ω, the voltages V1 and V2 tend to stay naturally balanced without any control, and eventually they stay equal. Since V1 and V2 stay between Vmin-allowed and Vmax-allowed, the balancer operates in this mode. In this mode, the inductor current is constantly zero.


B. 0.02~0.04: Low Load Condition

During 0~0.02, RL1 = 400Ω, RL2 = 200Ω and the battery does not reach its maximum SoC level. In this case, V1 and V2 stay between Vmax and Vmax-allowed. Therefore, the converter operates in mode 2. The proposed hierarchical control method is considered in this mode. According to the converters efficiency curves, the tertiary control gives an overall efficiency improvement in accordance with the objective function analysis done in section ‎IV. Assume receiving 4A for charging the battery, as shown in Fig. 7(a). Then RES1 sends 1.19A to support R2 and 2.1A to charge the battery. Moreover, RES2 sends 0.81A to support RL2 and 1.9A to charge the battery. Using the proposed control strategy, the power loss value is 389.36 W. Meanwhile, with an equal share proportion in charging the battery and independently supplying the loads, the power loss value will be 413.66 W.


C. 0.04~0.06: Power Transferring Between Buses

When the reduction of RL2 continues to 57Ω, (R1 stays at 400Ω), the redundant power-generated potential of RES1 is enough to supply the RL1 and RL2 load demands. Under this condition, the proposed converter changes to mode 3. For this reason and due to increased compensation, the upper bus only considers compensating the voltage of the negative bus. Then V2 begins to increase to the allowed voltage lower limit Vmin-allowed. After that, the operation mode changes to mode 1 until V2 reaches Vmin again.


D. 0.04~0.06: Battery Discharging Mode

With a greater reduction in RL1 (RL1=50Ω, RL2=57Ω), both of the bus voltages stay between Vmin and Vmin-allowed. Therefore, the battery discharges on both buses to increase the voltages V1 and V2. Finally, these voltages come back to the allowed values during droop control. Then V1 and V2 begin to i ncrease to the allowed voltage lower limit Vmin-allowed, and like the previous conditions, the operational mode changes to mode 1.

In order to test the performance and response of the hierarchical control method in mode 2, as shown in Fig. 8, a load profile of RL2 is given to the system. The value of iR2 varied from 0.8 A to 2.6 A. In this figure it is assumed that the battery charging current is 4A. In Figs. 8(a), (b) and (c) ir1=0.3A, 0.6A and 0.9A, respectively. During the test phase, it can be observed that the converter control strategy is optimized by the tertiary control and that the system efficiency is enhanced when compared with non-optimized results.


Fig. 8. Effect of increasing IRL2 and IRL1 on changing the sharing proportions. It is assumed that Ibat=4A and: (a) IRL1=0.3A; (b) IRL1=0.6A; (c) IRL1=0.9A.

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(C)


In order to test the performance of the optimization algorithm, the effect of increasing the battery charging current is shown in Fig. 9. In this figure, IRL1=1A. In Fig. 9(a), (b) and (c), the battery charging current is assumed to be 2A, 3A and 4A, respectively. It can be seen that in all of the load conditions, the GA tries to minimize the objective function value (power loss). It can be seen that the strategy of using converters under different load levels and battery charging powers, is carried out to achieve the highest system efficiency. Since the RES1 converter has the highest efficiency, it is mostly employed in light and medium loads levels.


Fig. 9. Effect of increasing IRL2 and Ibat on changing the sharing proportions. It is assumed that IRL1=1A and: (a) Ibat=2A, (b) Ibat=3A, (c) Ibat=4A.

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(c)



Ⅶ. EXPERIMENTAL RESULTS

In order to verify the hierarchical control strategy in the proposed converter, a low voltage and power (24V-50W) experimental system of the proposed converter, shown in Fig. 11, is designed and implemented. The experimental testbench includes two 24V DC input voltage sources with a maximum current of 2A, the proposed three-port multidirectional converter, two cascade VRLA 12V batteries and loads. The converter parameters are listed in Table II.

To determine the converter efficiency curve, the duty cycle is adjusted to meet different load current levels, and the input voltages are kept the same during the measurements. This curve is shown in Fig. 10(a). The MATLAB Curve Fitting Tool is used to transform data into functions as follows:

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Fig. 10. Experimental waveforms: (a) Conversion efficiencies of the DC bus to battery and the DC bus to DC bus modes, (b) S12, S13, S22 and S23 signals, battery charging current and RL1 voltage in mode 2, (c) Voltages of RL1 and RL2, output current of the positive voltage source and current of RL2 in mode 3, (d) Voltages of RL1 and RL2, current of RL2 and battery charging current in mode 4 with RL1 = 11.75Ω, RL2 = 7.2Ω, (e) Mode 4 with RL1=RL2=8.2Ω.

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(c)

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(d)

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(e)


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Fig. 11. Photograph of the proposed converter prototype.


Under the condition of RL1 = RL2 = 47Ω, the voltage sources power generations are more than the load demands in both buses. Therefore, the proposed converter operates in mode 2 and the battery can be charged with positive and/or negative buses. The proposed hierarchical control method is used in this mode. The tertiary control gives an overall efficiency improvement in accordance with the objective function. Assume receiving 2A for charging the battery. Then RES1 sends 1.67A to support RL2 and to charge the battery. Moreover, RES2 sends 1.35A to support RL2 and to charge the battery. The voltages of RL1, the output current of RES1 and RES2 and the battery charging current are shown in Fig. 10(b).

When RL2=7.2Ω and RL1 stays at 47Ω, the power- generation potential of the positive voltage source is more than the R1 load demand. Under this condition, the proposed converter operates in mode 3. The upper bus only considers compensating the voltage of the negative bus. Fig. 10(c) shows the RL1 and RL2 voltages, the output current of the positive voltage source and the current of R2 before and after compensation. In this condition, LVUR is reduced from 54.3% (before compensation) to 13.4% (after compensation).

With a decrease in RL1 (RL1 = 11.75Ω, RL2 = 7.2Ω), the voltage sources generations are no longer enough to supply the loads. Therefore, the proposed converter operates in mode 4 and the battery can participate to compensate the lower bus voltage. In this mode, the battery compensates the lower bus voltage. The voltage of RL1 and RL2, the current of the battery and the current of RL2 before and after compensation are shown in Fig. 10(d).

Under the condition that RL1 and RL2 are 8.2Ω, there is not enough power generated by the voltage sources to supply the available loads. In this case, the battery compensates the positive and negative bus voltages through the proposed converter. The voltage of RL1 and RL2, the current of the battery and the current of RL2 before and after compensation are shown in Fig. 10(e).



Ⅷ. CONCLUSION

In this paper, a bipolar multidirectional converter and a hierarchical control scheme were proposed for bipolar-type DC microgrids. The advantages of this new converter are as follows. 1) Enhancing the BPDCMG loadability due to the ability to transfer the terminal loads to another terminal. 2) Reducing the number of converters by integrating a voltage balancing converter and a battery converter. 3) Reducing the current of the neutral line and its associated power losses. 4) Possibility of balancing the voltage in the island condition of a BPDCMG by disconnecting the interlink converter. The structure of the proposed converter enhanced the system efficiency under light load conditions thanks to the proposed hierarchical control method. Under the proposed hierarchical control scheme, the proposed converter balanced the voltages of a BPDCMG with maximum system efficiency. Finally, simulation and experimental results had verified that the proposed converter had a suitable capability to balance buses voltages with unbalanced loads. Furthermore, the converter had a smooth transition without voltage or current stresses by changing the loads.



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Taha Ahmadi was born in Tehran, Iran, 1987. He received his B.S. degree in Electrical Engineering at the Shahrood University of Technology, Shahrud, Iran, in 2010; and his M.S. degree in Electrical Engineering at Mazandaran University, Babolsar, Iran, in 2012. He is presently working towards his Ph.D. degree in Electrical Engineering at Lorestan University, Khoramabad, Iran. His current research interests include distribution generation, microgrid control, and the application of power electronics in power distribution systems.


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Mohsen Hamzeh received his B.S. and M.S. degrees in Electrical Engineering from the University of Tehran, Tehran, Iran, in 2006 and 2008, respectively; and his Ph.D. degree in Electrical Engineering from the Sharif University of Technology, Tehran, Iran, in 2012. He has been a Senior Research Engineer with the SGP Company, Tehran, Iran, since 2010. He joined the Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran, in 2013, where he is presently working as an Assistant Professor. His current research interests include renewable energy, microgrid control and the application of power electronics in power distribution systems.


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Esmaeel Rokrok was born in Khoramabad, Iran, 1972. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the Isfahan University of Technology, Isfahan, Iran, in 1985, 1997 and 2010, respectively. He is presently working as an Assistant Professor in the Department of Electrical Engineering, Lorestan University, Khoramabad, Iran. His current research interests include power system control and dynamics, dispersed generation, microgrids, power electronic and robust control.