사각형입니다.

https://doi.org/10.6113/JPE.2018.18.6.1627

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Rapid Dynamic Response Flyback AC-DC Converter Design


Changyuan Chang, Menglin Wu*, Luyang He*, and Dadi Zhao*


†,*School of Microelectronics, Southeast University, Nanjing, China



Abstract

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC 1μm 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.


Key words: Constant voltage, PFM mode, Rapid dynamic response


Manuscript received May 7, 2018; accepted Jul. 17, 2018

Recommended for publication by Associate Editor Sang-Won Yoon.

Corresponding Author: ccyycc@seu.edu.cn Tel: +86-1-002-5267, Southeast University

*School of Microelectronics, Southeast University, China



Ⅰ. INTRODUCTION

In recent years, portable electronic products have been springing up, and the demand of high performance AC-DC converters has become huge. The output voltage of conventional secondary-side regulation (SSR) flyback converters is detected directly and transferred to the controller by an optical coupler and a precise voltage source [1], [2]. It is easy for SSR converters to obtain a rapid dynamic response. However, the complex structure of SSR converters and the sensitivity of optical couplers to temperature are the drawbacks [3]-[6]. Indeed, the primary- side regulation (PSR) flyback converter is popular due to the fact that its structure is simple and it does not need an optical coupler or a precise voltage source [7], which reduces both the cost and volume. In addition, the PSR structure has good system reliability and anti-interference [8]-[12].

In 2010, USB battery charging specification 1.2 put forward stringent requirements on the output performance of the switching power supplies for USB charging, which imposed strict specifications on the output voltage variations caused by load jumping. Therefore, scholars and experts from various countries have initiated research aimed at improving the dynamic response capability of switching power supplies.

A rapid dynamic response flyback AC-DC converter based on digital assistant technology is proposed in this paper. The detailed operation principle and design of compensation modules are illustrated in Section II. Simulation results will be given in Section III. Experimental results based on a prototype will be given in Section IV. Section V will make some conclusions of the proposed design.



Ⅱ. DESIGN OF THE CONTROL IC


A. System Review

The system diagram of the PSR AC-DC flyback converter with the proposed control chip is shown in Fig. 1, which consists of a bridge rectifier BD, EMI filter, RCD clamp circuit, freewheel diode D0, capacitors C0 and Cf3, inductor Lf3, transformer, power triode Q1, primary current sensing resistor RCS, pull-up resistor R1, pull-down resistor R2, filter capacitor CC, and control IC [13], [14]. In this control chip, the FB pin is to detect information on the output voltage through the auxiliary winding, the CS pin is to detect the primary side current, the VC pin, which is connected to an external capacitor, is to convert the digital compensation current to an analog current, and the BASE pin is to drive the power triode.


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Fig. 1. System diagram of the proposed PSR constant voltage AC-DC converter.


A block diagram of the control IC presented in Fig. 2 is mainly comprised of a sampling module, which contains a S/H and a logic module, OSC (oscillator) module, PFM generator, EA (error amplifier), digital CV (constant voltage) module, digital compensation module, CS peak controller, Base driver, internal supply, and protection module (UVLO, OVP).


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Fig. 2. Block diagram of the proposed CV control IC.


Key operating waveforms of the PSR flyback converter are depicted in Fig. 3. During the conduction time, the primary side inductor current Ip ramps up linearly and the electromagnetic energy is stored in the primary inductor. Once the peak value of Ip reaches the threshold, Q1 is turned off. The energy is released through the secondary inductor, which starts to demagnetize. The secondary side inductor current Is decreases from its peak current to zero. TD is the completion time of demagnetization. The auxiliary winding of the transformer is used to sense the output voltage Vo and demagnetization time. Then the information is fed back to the control IC. VFB is the voltage across the auxiliary winding.


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Fig. 3. Typical operating waveforms of PSR flyback AC-DC converter.


B. Principle of Dynamic Response Compensation

The PSR structure adopts a cycle by cycle sampling method. The output voltage is sampled at some point in the demagnetization time in one switching period, and the result is provided to the controller through the auxiliary winding. According to the sampling result, the controller adjusts the switching frequency to keep the output voltage stable. However, if the load jumps just after the sampling point, the controller cannot respond to this change before the next sampling point because the variation of output voltage has not been fed back into the controller, which results in a fluctuation of the output voltage. If the load jumps from light to heavy, the output voltage drops drastically since the switching period is too large under a light load and the sampling interval is too long. It takes a long time until the controller senses the variation of the output voltage again. However, if the load jumps from heavy to light, due to a high sampling frequency, the controller can make a rapid response, which avoids the large overshoot of the output voltage.

Therefore, the undershoot voltage and undershoot time are determined by the switching frequency under a light load when the load jumps from light to heavy. The higher the switching frequency under a light load, the stronger the dynamic response capability becomes.

In order to acquire a higher response speed, the switching pulse width should be adjusted dynamically on the basis of the PFM mode, which makes the frequency regulation more flexible.

From above, the switching pulse width is related to the primary peak current Ipk. For the CV converter operating in the PFM mode, the primary peak current Ipk can be expressed as:

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Where Vin is the rectified line voltage, Lp is the primary inductor, and Ton is the turn-on time of the power diode Q1. Then the input power Pin can be expressed as:

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Where, Ts is the switch period. The substitution of Eq. (1) into Eq. (2) leads to:

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The converter output power Pout is:

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Where RL is the load resistor.

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According to the relationship among the input power Pin, output power Po and efficiency η which is shown in Eq. (5), Vo can be defined as follows by combining Eq. (2) and Eq. (3):

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By substituting Eq. (1) into Eq. (6), the output voltage can be redefined as:

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Where the primary peak voltage Vpk is set to a constant value Vth_cs, and Fs is the switch frequency.

From Eq. (7), when the system is operating in the CV mode, if the primary peak voltage Vpk decreases, the switching frequency FS increases, and the dynamic response capability is enhanced. Thus, a dynamic response compensation method, which can adjust Vpk based on the load state, is proposed. A schematic diagram of this is shown in Fig. 4.


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Fig. 4. Schematic diagram of dynamic response compensation.


The compensation current ICS_comp is generated by the compensation module based on the switching frequency FS. ICS_comp is linear to the switching period TS. The ratio coefficient of ICS_comp and TS is set to α, and the compensation current is:

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In Eq. (8), IC,max is the maximum compensation current. ICS_comp is injected into the positive port of the comparator CMP and then flows out of the CS pin. The product of the primary peak current Ipk and the primary sensing resistor RCS is the primary peak voltage Vpk. After compensation, Vpk can be derived as:

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It can be seen in Eq. (9) that when the system is operating under a heavy load, FS is relatively high and the compensation current ICS_comp is small, which makes the primary peak voltage Vpk high. On the other hand, when the circuit is under a light load, FS drops to a low level, and the large compensation current ICS_comp causes Vpk to be relatively low. Therefore, the switching pulse width can be adjusted based on the load state after the dynamic response compensation. Since VCS_th-IC,max·Rcomp is the minimum value of the primary peak voltage, Eq. (9) can be simplified as:

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In Eq. (10), Vpk,min is the minimum primary peak voltage, and β is equal to the product of α and Rcomp. Substituting Eq. (10) into Eq. (7), the output voltage formula is expressed as:

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By comparing Eq. (11) with Eq. (7), it is easy to see that the regulation of Vo based on the switching frequency FS is more sensitive. The dynamic response capability after compensation is stronger.

From another point of view, when the system is working in the CV mode, compensation current is generated depending on the load state. If the load is light, the compensation current is large. Vpk is forced to drop to a low level, causing the switching pulse width to become very small. As a result, the switching frequency must be improved to maintain the output voltage constant.


C. Design of the Dynamic Response Compensation Module

The digital assistant dynamic response compensation module consists of a data storage unit, encoder, current source array, RC filter and V/I converter. Based on the binary counting number Trise of the switching period TS, which is from the digital exponential waveform generator, the compensation current is produced and injected to the CS pin. A schematic diagram of compensation module can be seen in Fig. 5.


Fig. 5. Schematic diagrams of the dynamic response compensation module. (a) Digital compensation current generator; (b) Analog compensation current generator.

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(a)

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(b)


In the digital exponential waveform generator, when the power triode Q1 is turned on, the binary counting number Trise is reset and increases from zero. Trise is then converted into real time Ts in the data storage. However, it has not been stored until the rising edge of Vsw comes (Trise is transmitted to the data storage in real time but has not been stored). Once the exponential waveform voltage reaches the EA output voltage, the Q1 control signal Vsw jumps to a high level and Q1 is turned on again. The rising edge of Vsw informs the data storage to store Trise. At this time, Trise is equal to the switching period TS. The binary switching period TS is encoded and the most relevant channels in the current source array are turned on, which generates the digital compensation current Icomp_D. The lighter the load, the more channels are turned on.

Since the digital compensation current is discrete, has large glitches and is unsuitable for injection into the CS pin, it is necessary to obtain an analog compensation current. Icomp_D is converted to the analog capacitor voltage VC by RC filtering, as shown as Fig. 5(a). Then VC is transmuted into the analog compensation current Icomp_A, as shown as Fig. 5(b). Through the current mirror, Icomp_A is converted into the dynamic response compensation current ICS_comp.



Ⅲ. SIMULATION RESULTS

From the principle of the compensation circuit, it can be known that the compensation current is linear to the system load. In this section, the circuit is simulated under different loads. The corresponding data results are shown in Table II.


TABLE I USB BATTERY CHARGING SPECIFICATION 1.2

Parameter

Symbol

Value

Max output voltage

Vo,max

6V

Min output voltage

Vo,min

4.1V

Max undershoot time

TUDST

10ms


TABLE II SWITCHING FREQUENCY AND COMPENSATION CURRENT DATA

Io (A)

Ts(μs)

Fs(kHz)

CS Compensation current(μs)

1.1870

22.1356

45.1761

2.660622

1.0860

23.5817

42.4058

6.286886

0.9625

24.9978

40.0035

9.74302

0.8460

26.8883

37.1909

14.39283


Key waveforms of the system load jumping from a light (load resistance is 280Ω) to a heavy (load resistance is 4.2Ω) are shown in Fig. 6. Without dynamic response compensation, the undershoot of the output voltage is 1.53V and the undershoot time is 2.45ms. However, the undershoot of Vo is just 0.843V and the undershoot time is only 1.62ms when the dynamic response compensation is adopted.


Fig. 6. Key simulation waveforms of a load jump from a light to a heavy load: (a) Simulation without dynamic response compensation; (b) Simulation with dynamic response compensation.

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(a)

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(b)



Ⅳ. EXPERIMENTAL RESULTS


A. Layout Design of the Control IC

The proposed AC-DC controller is implemented in NEC 1μm 5V/40V HVCMOS and the area is 974.8×510.5μm2. The layout of this controller is shown in Fig. 7. The key modules and pins are marked in the photograph.


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Fig. 7. Layout of proposed control IC.


B. Test Results of the Proposed Control Chip

A prototype of the test board is shown in Fig. 8, and its size is about 4.8cm×3.6cm. The key components and parameters of the circuit are listed in Table III.


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Fig. 8. Photograph of the fabricated PCB.


TABLE III KEY COMPONENTS AND PARAMETERS

Components

Symbol

Value or Specification

Bridge rectifier

BD

1N4007

EMI filter inductor

Lf1, Lf2

1mH, 4.7μH

EMI filter capacitor

Cf1, Cf2

4.7μF

Primary-side inductor

Lp

1.4mH

Transformer core

T

EE13

Power switch

Q1

NPN 13003

Transformer turn’s ratio

NP/NS/NAUX

126/11/32

Pull-up resistor

R1

27KΩ

Pull-down resistor

R2

3.6KΩ

Auxiliary-side Freewheel diode

D1

FR107

Primary current sense resistor

RCS

Output filter inductor

Lf3

4.7μH

Output filter capacitor

Cf3

680μF

Output capacitor

Co

470μF

Secondary-side Freewheel diode

Do

SR3100


In order to verify the response capability, the load current jumps from 0A to 1.2A. The corresponding waveforms are shown in Fig. 9. The undershoot voltage VUDST is about 893.75mV. As a result, the output voltage can be maintained above 4.1V. The undershoot time is 7.4ms. Therefore, the test results of the load jump all meet the requirement of USB Specification 1.2.


Fig. 9. Tested waveforms of the output current jumping from 0 to 1.2A. (a) Measured waveforms of several switching periods. (b) Measured waveforms of one switching period.

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(a)

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(b)


The efficiency in the CV mode is tested and depicted in Fig. 10. Obviously, the efficiency under a low input voltage is lower than that under a high input voltage. The maximum efficiency of the CV output can reach about 83.3%.


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Fig. 10. Measured efficiency versus Vo under an 85Vac, 60Hz- input and a 265Vac, 50Hz-input.


A comparison between the proposed work with other similar technologies is shown in Table IV. The dynamic response capability of the method proposed in this paper and iW1760 satisfy the demand of USB Specification 1.2. However, the method proposed in [15] does not. The undershoot time of [15] is too large at almost 22ms. The method in [15] and this work adopt analog technology. However, iW1760 adopts digital technology. The circuit structure of iW1760 is too complex and the cost is much higher than that of the proposed work, which indicates that the proposed rapid dynamic response converter has good prospects.


TABLE IV COMPARISON BETWEEN DIFFERENT METHODS

 

This work

[15]

iW1760

Topology

Flyback

Flyback

Flyback

Controller type

Analog

Analog

Digital

Output voltage

5V

5V

5V

Max output current

1.2A

1A

2V

Standby power consumption

40mW

N/A

50mW

Max efficiency

83.3%

N/A

85%

undershoot voltage VUDST(0-1.2A)

893.75mV

680mV

N/A

undershoot time(0-1.2A)

7.4ms

22.09ms

6ms

Meeting USB Specification 1.2

Yes

No

Yes



Ⅴ. CONCLUSIONS

A rapid dynamic response AC-DC CV converter based on digital assistant technology is designed in this paper. The system adopts a flyback structure, omitting the optical coupler and a precise voltage source. It also reduces both the size and cost. A digital compensation module is proposed to dynamically adjust the switching pulse width for the sake of good dynamic response capability. The control IC is implemented based on a NEC 1μm 5V/40V HVCMOS process, and a 5V/1.2A prototype has been built to verify the proposed control method. The minimum output voltage can be kept above 4.16V and the undershoot time is only 7.4ms when the load jumps from idle to a heavy load, which meets application requirements.



REFERENCES

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[2] H. F. Liu and L. K. Chang, “Flexible and low cost design for a flyback AC/DC converter with harmonic current correction,” IEEE Trans. Power Electron., Vol. 20, No. 1, pp. 17-24, Jan. 2005. 

[3] C. J. Chang and C. L. Chen, “An isolated output-feedback scheme with minimized standby power for SMPS,” IEEE Trans. Power Electron., Vol. 28, No. 11, pp. 5140-5146, Nov. 2013.

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[5] J. M. Zhang, H. Zeng, and T. Jiang, “A primary-side control scheme for high-power-factor LED driver with TRIAC dimming capability,” IEEE Trans. Power Electron., Vol. 27, No. 11, pp. 4619-4629, Nov. 2012.

[6] X. G. Xie, J. Wang, C. Zhao, Q. Lu, and S. Liu, “A novel output current estimation and regulation circuit for primary side controlled high power factor singled-stage flyback LED driver,” IEEE Trans. Power Electron, Vol. 27, No. 11, pp. 4602-4612, Nov. 2012.

[7] Y. T. Lin, T.-J. Liang, and K.-H. Chen, “IC design of primary-side control for flyback converter,” Future Energy Electronics Conference, Vol. 92, pp. 449-453, 2013.

[8] C. S. Moo, Y.-J. Chen, and W.-C. Yang, “An efficient driver for dimmable LED Lighting,” IEEE Trans. Power Electron, Vol. 27, No. 11, pp. 4613-4618, Nov. 2012.

[9] H. Choi, “Flyback converter protection scheme with a selective shutdown delay time,” IEEE Industrial Electronics, IECON 2006, Conference on IEEE, pp. 2192-2196, Nov. 2006.

[10] S. Jung and G.-H. Cho, “Transformer coupled recycle snubber for high-efficiency offline isolated LED driver with on-chip primary-side power regulation,” IEEE Trans. Ind. Electron., Vol. 61, No. 12, pp.6710-6719, Dec. 2014.

[11] C. Adragna, “Primary-controlled high-PF flyback converters deliver constant dc output current,” in Proc. Eur. Conf. Power Electron, pp. 1-10, Sep. 2011.

[12] Y. C. Li and C. L. Chen, “A novel primary-side regulation scheme for single-stage high-power-factor AC–DC LED driving circuit,” IEEE Trans. Ind. Electron, Vol. 60, No.  11, pp. 4978-4986, Nov. 2013.

[13] Y. B. Zhou, F. B. Yu, and S. B. Tang, “Control method and controller,” C.N. Patent No. CN 103427655 B, 2013.

[14] S. B. Zhang, Y. J. Bai, and Z. L. Hu, “Control method and control circuit for improving load dynamic response and switching power supply,” C.N. Patent No. CN 104300793 A, 2015.

[15] Y. Li and J. Zheng, “A low-cost adaptive multi-mode digital control solution maximizing AC/DC power supply efficiency,” in Proc. IEEE 25th Annu. Appl. Power Electron. Conf. Expo., pp. 349-354, 2011.



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Changyuan Chang received his M.S. and Ph.D. degrees in Electronic Engineering from Southeast University, Nanjing, China, in 1990 and 2000, respectively. He is presently working as an Associate Professor in the School of Integrated Circuits of Southeast University. His current research interests include analog-controlled and digitally- controlled ICs designs for power-management.


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Menglin Wu received his B.S. degree from Jiangsu University of Electrical Engineering, Zhenjiang, China, in 2016. He is presently working towards his M.S. degree in IC Engineering at Southeast University, Nanjing, China. His current research interests include switch-mode power supplies and ac-dc converters.


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Luyang He was born in Henan, China, in 1995. He received his B.S. degree from Xidian University, Xi’an, China, in 2017. He is presently working towards his M.S. degree in IC Design at Southeast University, Nanjing, China. His current research interests include analog integrated circuits, power electronics and AC-DC converters.


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Dadi Zhao was born in Jiangsu, China, in 1995. He received his B.S. degree from Nantong University, Nanjing, China, in 2016. He is presently working towards his M.S. degree in IC Engineering at Southeast University, Nanjing, China. His current research interests include analog integrated circuits, power electronics and CV/CC AC-DC converters