https://doi.org/10.6113/JPE.2018.18.6.1642

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Flyback AC-DC Converter with Low THD Based on Primary-Side Control

Changyuan Chang^†, Luyang He^*, Zixuan Cao^*, and Dadi Zhao*

^†,*School of Microelectronics, Southeast University, Nanjing, China

Abstract

A single-stage flyback LED AC-DC converter based on primary-side control under constant current mode is proposed in this study. The proposed converter features low total harmonic distortion (THD) and high power factor (PF). It also consists of a zero-crossing distortion compensation circuit and a variable duty ratio control compensation circuit to deal with the line current distortions caused by fixed duty ratio control. The system model and layout are built in Simplis and Cadence, respectively. The feasibility and performance of the proposed circuit is verified by designing and fabricating an IC controller in the HHNEC 0.35 μm 5 V/40 V HVCMOS process. Experimental results show that the PF can reach a level in the range of 0.985–0.9965. Moreover, the average THD of the entire system is approximately 10%, with the minimum being 6.305%, as the input line voltage changes from 85 VAC to 265 VAC.

Key words: AC–DC, Fixed duty ratio control distortion, Flyback converter, Low THD, Zero-crossing distortion

Manuscript received Jan. 23, 2018; accepted Sep. 6, 2018

Recommended for publication by Associate Editor Il-Oun Lee.

^†Corresponding Author: ccyycc@seu.edu.cn Tel: +86- 25-83791835-8206, Southeast University

^*School of Microelectronics, Southeast University, China

Ⅰ. INTRODUCTION

LED lighting has attracted much attention in green development applications [1]-[3]. As key components, different architectures and techniques of LED drive circuits have been studied, and flyback power factor correction (PFC) converters are the most widely used because of their strong anti-interference ability, flexible conversion, low cost, and simple structure [4]-[7]. Existing studies have shown that single-stage flyback PFC converters involve various control strategies [8], [9]. The common control modes used are peak current mode control, average current mode control, and single-cycle mode control.

The harmonics generated by power electronic devices for switching power supply can cause serious pollution to power grids. These harmonics increase power grid losses and cause interferences to communication lines, radar equipment, and other surrounding communication systems. In addition, harmonics exert adverse effects on power electronic devices, such as switching power supplies. Harmonics decrease the power factors (PFs) of circuits and influence the utilization rate of electric energy. In addition, harmonics cause the circuit to generate large spike currents, which seriously damage filter capacitors on the DC side. Meanwhile, an input side electromagnetic interference (EMI) filter should be large due to high peak current pulses [10].

To improve the efficiency, increase the reliability, and minimize the harmonic pollution of power grids, considerable studies have analyzed line current distortions and the reduction of the distortion effect on circuit performance by increasing system complexity [11]-[13]. In 2010, Shi Huang, Tang, Dan, Chen, and others developed two methods to compensate for those distortions [14]. The first method replaces the traditional zero-current detector with zero-voltage switching to obtain an accurate demagnetization time. The second method reverses the voltage on an input capacitor and multiplies it by a certain factor to correct the turn-on time. With this method, the distortion caused by the reverse current can be compensated for. The study used a direct truncation approach instead of making the circuit work properly in a zero-crossing distortion region. In 2012, Li Yani, Yang Yintang, and others proposed a periodically self-starting timing circuit, in which a shunt resistor was added between the oscillator and the auxiliary winding to reduce zero-crossing distortions and prevent the system from reaching a zero state [15]. However, an extra circuit is required and thus increases system complexity. At the same time, the shunt resistor is inaccurate because it is easily affected by external factors, such as temperature and noise. In 2013, Jen-Chieh Tsai, Chi-Lin Chen, and others presented a new approach to decrease input current distortions [16]. This approach adds an original sawtooth wave to make the signal follow the input voltage amplitude, and the comparison result of the sawtooth wave and the output voltage is used to control the switching transistor. In addition, the study proposed a non-negative voltage and zero current detection circuit that uses an up-and-down clamping method to improve switch sensitivity. In 2015, Xiaoru Xu and Huiqiang Chen developed a frequency-limiting circuit to avoid EMIs and to reduce input current distortions [17]. An adaptive blanking time control circuit was also presented to deal with zero-crossing distortions. Although the distortion problem in light loads and small input line voltages is resolved, the heavy load and large input line voltage problems were not analyzed. The PF can reach 0.96 when the input voltage is 220 VAC, which is unsuitable.

Section 2 presents two kinds of distortion that frequently occur in traditional single-stage flyback AC–DC converters based on primary side control. Section 3 analyzes the simulation result of the Simplis model of compensated circuits. Section 4 describes the chip layout and test results, and Section 5 provides the content summary.

Ⅱ. ANALYSIS AND CONSTRUCTION OF TWO KINDS OF COMPENSATION CIRCUIT

The structure of the proposed circuit is shown in Fig. 1. The ideal waveforms of the input line voltage V_in, inductance current I_p, freewheeling diode current I_D, switch gate voltage V_gs, output current I_out, and output voltage V_out are shown in Fig. 2.

Fig. 1. Structure of the proposed circuit.

Fig. 2. Ideal waveforms of the system.

The ideal relation among V_in, input average current I_av, inductance peak current I_pk, duty cycle D, and turn-on time T_on is illustrated as follows:

          (1)

However, the practical fact can be complicated. Next, the influence of nonideal factors on the PF and total harmonic distortion (THD) of the system is analyzed, and the corresponding compensation circuits are established.

A. Analysis of Zero-Crossing Distortion and Construction of Compensation Circuit

Zero-crossing distortion is mainly caused by two conditions. First, due to the presence of residual charges, the input capacitance C_in cannot be normally charged when the input line voltage is small (near the zero-crossing area). Meanwhile, the diodes in the bridge rectifier are reverse biased, and the circuit cannot normally work. Second, the output energy delivered is reduced due to the resonance among inductance L, parasitic capacitance C_ds of the switch transistor, and input capacitor C_in, which causes zero-crossing distortion. This kind of distortion worsens when the input line voltage is small or the system is in light load. Thus, T_on should be increased under small input voltage, and the discharging time of C_in and charging time of the inductor should be extended. The distorted input current and the ideal sinusoidal waveform are shown in Fig. 3.

Fig. 3. Distorted waveform caused by zero-crossing distortion.

The zero-crossing distortion compensation circuit is shown in Fig. 4. The output of comparator COMP controls switch transistor MN7, consequently affecting the working state of switch MP4. EN1 is an enable signal. The circuit operates normally when EN1 is low. COMP outputs a high voltage and turns switches MN7 and MN4 on when the COMPENSATION signal is lower than that of the reference voltage. Thus, the COMPENSATION signal is compensated for by the system. The output is low, and switches MN7 and MN4 are sequentially turned off when the voltage of the COMPENSATION signal reaches the value of the positive terminal of COMP. The values of resistances R5 and R6 influence the compensated input current waveform.

Fig. 4. Schematic of zero-crossing distortion compensation circuit.

In addition, a temperature-independent reference voltage V₊ is generated by triode Q2, load resistance R4, and transistors MP1, MP2, and MN5. This reference voltage is used as the positive input of COMP. V₊ can be expressed as follows:

   (2)

where V_EB is the voltage drop between the emitter and the base of triode Q2 and I₁ is the current flowing through transistor MP1, resistor R4, and triode Q2 collector.

Output voltage V_COMPENSATION is used as the feedback to access the negative input of COMP.

     (3)

When the reference voltage as the control signal of COMP is less than that of V₊, V_COMPENSATION is compensated to the following value:

          (4)

where R5 and R6 are the resistance values of R5 and R6, respectively. Thus, the effect of the zero-crossing compensation module on the entire system is influenced by V₊ and K_R.

The above discussion is based on an ideal case. In actual circuits, Equation (4) can be rewritten by considering parasitic capacitance C_P of resistance R6 and by ignoring the slightly important parasitic capacitance of resistance R5 and switch MP4 due to the existence of the parasitic capacitance of resistance.

        (5)

The relationship between current i_R flowing through resistor R6 and current i_C through parasitic capacitance C_P is shown as follows:

    (6)

         (7)

Equations (6) and (7) are substituted with the following equations:

    (8)

   (9)

          (10)

           (11)

Therefore, the output of the entire compensation circuit satisfies the following equation:

          (12)

where

           (13)

Compensated output V_{Compensation_OUT} is used as reference V_REF in Equation (12) to control the input current and thereby achieve a high PF and low THD.

B. Analysis of Input Current Distortion Caused by Fixed Duty Cycle Control and Construction of Compensation Circuit

The average value of the input current can be expressed as (1). The PF of the system is improved when I_pk×D is proportional to V_in, which indicates that T_on×D is constant and I_av is proportional to V_in. The average current expression is shown in (1). However, because T_on is fixed, T_off is extended with the increase of V_in, and the duty cycle D decreases. Therefore, I_av is not directly proportional to V_in, and the PF cannot reach 1. The fixed on time-controlled active PFC circuit can only ensure that peak current I_pk is proportional to V_in; it cannot guarantee that I_av is proportional to V_in. Thus, the fixed on time control is unable to achieve a high PF and low THD.

For the boundary model system, the following formula is expressed as

        (14)

where N_ps is the former side turn ratio and T_sw is the switching cycle. Equation (14) can be obtained by (15).

       (15)

By combining (1) and (15), we can obtain (16) as follows:

   (16)

As shown in (16), I_av deviates from the voltage waveform with the changes of V_in, resulting in the increase of the THD and decrease of the PF. Solving this problem requires the use of other methods apart from the control of T_on. Therefore, a new variable duty ratio compensation circuit is proposed. Its schematic is shown in Fig. 5.

Fig. 5. Schematic of the adaptive duty cycle control compensation circuit.

As shown in Fig. 5, voltage V_comp, which is used to control T_on, is converted into current I_comp through amplifier AMP, resistor R1, and transistor Mn1.

     (17)

Then, current I_comp is converted into the charging current of C1 through a current mirror with a ratio of 1: N (the ratio of W/L of transistors Mp1 and Mp2 is 1: N), and the output signal Timer can be expressed as follows:

         (18)

Then, the corresponding frequency of Timer can be written as f_timer = 1/Timer ∝ V_comp. The circuit operates as follows: the increase of the line voltage or the decrease of the output voltage results in the rise of V_CS and the output voltage of feedback circuit. Then, reference voltage V_ref and the output voltage of the feedback circuit are sent to the positive and negative points of the error amplifier, respectively. Consequently, output voltage V_comp of the error amplifier decreases, and the voltage Timer increases, thereby increasing opening time T_on. This condition indicates that the negative effect caused by the increase of input voltage V_in and decrease of duty ratio D can be offset or reduced. In sum, the modulation of system frequency is achieved by controlling voltage V_comp.

Ⅲ. SIMULATION AND TEST VERIFICATION

A. Modeling, Simulation, and Analysis of Zero-Crossing Distortion Compensation Circuit

As shown in Fig. 6, the Simplis model is built on the basis of the construction in Fig. 4. The reference circuit that generates the voltage of the positive point of comparator COMP is replaced with resistors R9 and R4. The COMP in Fig. 4 represents comparator U2 in Fig. 6. To simulate the function of the compensation circuit, we set the default value of EN1 to low. In this case, MN6 and MN8 can be omitted, and transistors MN7 and MP4 are replaced with switches S2 and S5, respectively.

Fig. 6. Simplis model of zero-crossing compensation circuit.

As shown in Equation (12), the different values of coefficients K_R and K_T affect the output voltage of the compensation circuit. In other words, they determine the impact of the compensation circuit on the system. The comparison of the different values of K_R and K_τ of the input current waveforms is shown in Fig. 7. At this time, input voltage V_in is 220 VAC, and reference voltage V_REF is 0.2 VDC. As shown in Fig. 7, the input current can follow the change of the input voltage without any distortion in a half period when K_R = 1/4 and K_τ = 3/4. Compared with several data sets, the input current is remarkably improved when K_R = 1/4 and K_τ = 3/4.

Fig. 7. Input current waveforms in different values of K_R and K_τ.

As shown in Fig. 8, the Simplis model is built on the basis of the construction in Fig. 5. The current mirror consisting of transistors MP1 and MP2 in Fig. 5 is replaced with current- controlled current source G1, and resistor R3 in Fig. 5 is represented by the impedance of transistor MP2. U3 is a buffer. Timer turns from high to low when the voltage across the capacitor is charged to a value greater than or equal to Vref. Then, switch S1 is closed, capacitor C1 is discharged, and Timer changes to a high level again to prepare for the next flip.

Fig. 8. Simplis model for adaptive duty cycle control compensation circuit.

The simulation waveforms are presented in Fig. 9. The duty cycle of Timer is 50%, and the voltage slope of the negative side of comparator U2 is 1 V/100 µs when V_comp equates to 1 V. The duty cycle of Timer becomes approximately 25%, and the slope is 2 V/100 µs when V_comp is changed to 2 V. In conclusion, the value of Timer can be adjusted by detecting the value of V_comp, and Timer changes in the opposite direction of V_comp. Therefore, the desired control can be achieved when this compensation circuit is added to the system.

Fig. 9. Simulation waveforms of adaptive duty cycle control compensation circuit. (a) Waveforms for V_comp = 1 V. (b) Waveforms for V_comp = 2 V.

(a)

(b)

Several parameters of the proposed flyback AC–DC converter are listed in Table I. The simulation results in Simplis are shown in Fig. 10, where (a) is the simulation result of the uncompensated system and (b) is the result of the compensated system. Vin is the waveform of the 220 VAC input line voltage, and IF is the input current waveform.

TABLE I PARAMETERS OF FLYBACK AC–DC CONVERTER

Key	Value
Input voltage Vin	85~265Vac
Output current Io	450mA
Transformer turn’s ratio	48:16:6
Output capacitor	441.1μF/50V
Rectifier	MB6S
Primary inductance	890uH
Power transistor	AP03N70
Transformer frame	EE6

Fig. 10. Simulation results before and after compensation: (a) Simulation result of the uncompensated system; (b) Simulation result of the compensated system.

(a)

(b)

As shown in Fig. 10, the input line current has serious distortions, and those distortions are reduced to a great extent after the addition of compensation circuits in the system. The THD of Fig. 10(a) measured by Simplis is approximately 25%. The PF can be calculated on the basis of the relationship between the THD and the PF in Equation (19). Suppose that cosψ₁ is 1. The PF of Fig. 10(a) can then be obtained as 0.97. By using the same method, the THD and PF of Fig. 10(b) can be calculated as 5.2% and 0.9986, respectively. The results indicate that the THD and PF are improved by the compensation circuit.

        (19)

Ⅳ. EXPERIMENTAL RESULTS

The IC is implemented in the HHNEC 0.5 μm 5 V/40 V HVCMOS process. A micro-graph of the fabricated chip is shown in Fig. 11. The operating AC voltage of the PCB is 85–265 VAC, and the output power is 3–20 W. As shown in Fig. 12, the basic modules of the circuit, such as output capacitance and resistance, transformer, power transistor, control chip, rectifying bridge, and EMI module, are labeled.

Fig. 11. Micro-graph of the fabricated chip.

Fig. 12. System test board.

Fig. 13 illustrates the waveforms of 220 VAC/60 Hz input voltage and current. The test result shows that the current follows the input voltage well.

Fig. 13. Waveforms of input current and voltage.

The voltage waveform of V_comp is shown in Fig. 14. The test result shows that V_comp remains approximately constant under the steady operation of the circuit. Although several ripples are superimposed on V_comp, its value basically remains at 130.5 mV.

Fig. 14. Waveform of voltage V_comp.

In Fig. 15, the green and yellow lines are the waveforms of switch gate voltage V_gate and voltage V_cs on sampling resistor R_cs respectively. The system is in good operation state.

Fig. 15. Waveforms of V_gate and V_cs.

The PF line chart of different systems at several input line voltages is shown in Fig. 16. The zero-crossing distortion and adaptive duty cycle control compensation circuits effectively improve the PF. Specifically, the PF increases from 0.973 (maximum before compensation) to 0.9965. The THD line chart of different systems at several input line voltages is shown in Fig. 17. The zero-crossing distortion and adaptive duty cycle control compensation circuits effectively reduce the harmonic component of the system. Specifically, the THD is reduced from 23.72% (before compensation) to 6.305%.

Fig. 16. PFs of different systems at several input voltages.

Fig. 17. THDs of different systems at several input voltages.

Obviously, the system performance is improved by using the proposed design. On the basis of the test results of the chip at different voltages and formula of efficiency in (20), the following equation is derived:

   (20)

The performance parameters of the proposed flyback AC–DC converter are shown in Table III. The comparison of the performances of the proposed converter and other products is shown in Table IV.

TABLE II EFFICIENCY TABLE

Input voltage Vin/Vac	Input power Pin/W	Output voltage Vo/Vdc	Output current Io/mA	Output power Po/W	Efficiency η
90	24.1	45.25	449	20.3274	85.931%
120	23.48	45.35	449	20.3621	86.721%
180	23.21	45.37	450.6	20.4437	88.082%
220	23.43	45.38	451.1	20.4709	87.371%
264	23.76	45.37	451.5	20.4846	86.214%

TABLE III PERFORMANCE PARAMETERS OF FLYBACK AC–DC CONVERTER

Key	Value
Input voltage Vac	85~265Vac
Output current Io	450mA
Power factor	0.9965~0.987
THD	6.305%~10.05%
Efficiency	86%~88%
Output current ripple	62.5mA
Switch frequency	60kHz~140kHz

TABLE IV COMPARISON OF THE PROPOSED CONVERTER AND OTHER PRODUCTS

	This paper	FL7732	SY5802	BP3318
Input voltage	85~265Vac	90~265Vac	90~265Vac	85~265Vac
Output power	3~20W	9W	10.8W	100W
Max switch frequency	100kHz	120kHz	120kHz	100kHz
Conversion efficiency	>86%	>85%	87%	84.8%
Power factor	0.985	>0.9	>0.9	>0.92
THD	<11.5%	<25%	<20%	<18%
Linear regulation rate	±2%	±3.5%	±3%	±4.1%
Load regulation rate	±2%	±2.5%	±3%	±2.2%

Ⅴ. CONCLUSION

The proposed flyback AC–DC converter uses zero- crossing distortion and adaptive duty cycle control compensation circuits to compensate for two kinds of line current distortions caused by zero-crossing distortions and fixed duty ratio control. With the proposed converter, the input line current waveform is close to the sinusoidal waveform. A model is built, and a new AC–DC converter circuit is simulated in Cadence to verify the effect of the two proposed circuits. The simulation results show that the compensation circuits are valuable in improving system performance. The test results indicate that the average THD of the entire system is approximately 10%, with the minimum being 6.305%. The PF is above 0.965, with the maximum being 0.9965.

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Changyuan Chang received his M.S. and Ph.D. degrees in Electronic Engineering from Southeast University, Nanjing, China, in 1990 and 2000, respectively. He is currently serving as an Associate Professor in the School of Integrated Circuit in Southeast University. His main research interests include the design of analog-controlled and digitally controlled ICs for power management.

Luyang He was born in 1995 in Henan, China. He received his B.S. degree from XiDian University, Xi’an, China, in 2017. He is presently working toward his M.S. degree in IC Design at Southeast University, Nanjing, China. His current research interests include analog integrated circuits, power electronics, and AC–DC converters.

Zixuan Cao received her B.S. degree from Xi’an University of Posts and Telecommunications, Xi’an, China, in 2015. She is presently working toward her M.S. degree in IC Engineering at Southeast University, Nanjing, China. Her current research interests include switch-mode power and AC–DC converters.

Dadi Zhao was born in Jiangsu, China, in 1995. He received his B.S. degree from Nantong University, Nantong, China, in 2016. He is presently working toward his M.S. degree in IC Engineering at Southeast University, Nanjing, China. His current research interests include analog integrated circuits, power electronics, and CV/CC AC–DC converters.