https://doi.org/10.6113/JPE.2018.18.6.1729

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Comparative Study of Minimum Ripple Switching Loss PWM Hybrid Sequences for Two-level VSI Drives

G. Vivek^†, Jayanta Biswas^**, Meenu D. Nair^***, and Mukti Barai^*

^†,*Department of Electrical Engineering, National Institute of Technology, Calicut, Kerala, India

^**Freelance Researcher, Calicut, Kerala, India

^***Department of Electrical Engineering, Karpagam College of Engineering, Tamil Nadu, India

Abstract

Voltage source inverters (VSIs) are widely used to drive induction motors in industry applications. The quality of output waveforms depends on the switching sequences used in pulse width modulation (PWM). In this work, all existing optimal space vector pulse width modulation (SVPWM) switching strategies are studied. The performance of existing SVPWM switching strategies is optimized to realize a tradeoff between quality of output waveforms and switching losses. This study generalizes the existing optimal switching sequences for total harmonic distortions (THDs) and switching losses for different modulation indexes and reference angles with a parameter called quality factor. This factor provides a common platform in which the THDs and switching losses of different SVPWM techniques can be compared. The optimal spatial distribution of each sequence is derived on the basis of the quality factor to minimize harmonic current distortions and switching losses in a sector; the result is the minimum ripple loss SVPWM (MRSLPWM). By employing the sequences from optimized switching maps, the proposed method can simultaneously reduce THDs and switching losses. Two hybrid SVPWM techniques are proposed to reduce line current distortions and switching losses in motor drives. The proposed hybrid SVPWM strategies are MRSLPWM 30 and MRSLPWM 90. With a low-cost PIC microcontroller (PIC18F452), the proposed hybrid SVPWM techniques and the quality of output waveforms are experimentally validated on a 2 kVA VSI based on a three-phase two-level insulated gate bipolar transistor.

Key words: Harmonic distortion, Minimum ripple switching loss PWM (MRSLPWM), Quality factor, Voltage source inverter (VSI)

Manuscript received Oct. 14, 2017; accepted Aug. 29, 2018

Recommended for publication by Associate Editor Young-Doo Yoon.

^†Corresponding Author: gvivek1988@gmail.com Tel: +91-9495280334, National Institute of Technology

*Dept. of Electrical Engineering, National Institute of Technology, India

**Freelance Researcher, India

***Dept. of Electrical Eng., Karpagam College of Engineering, India

Ⅰ. INTRODUCTION

Power electronic converters are widely used to convert electrical energy from one level to another through the ON/OFF property of semiconductor switches. Voltage source inverters (VSIs) convert fixed DC voltages to controllable AC voltages. A block diagram of a VSI-fed induction motor drive is shown in Fig. 1. VSIs approximate output voltages through the high-frequency switching of pulse width modulation (PWM) techniques. The harmonics at the output of a VSI and the switching loss in a VSI are strongly influenced by the PWM technique used [1]-[5]. Extensive research on PWM techniques has been conducted [2]-[14] to address a variety of drawbacks associated with modulation techniques. Carrier- based PWM and space vector PWM (SVPWM) are the two most recognized methods among all available PWM techniques. Carrier-based PWM techniques provide waveform quality and operate at a high switching frequency. SVPWM is considered to be a superior technique for PWM implementation because it has advantages over carrier-based PWM, e.g., good utilization of DC bus voltages, reduced switching frequencies, low current ripple, and enhanced waveform quality [15]. SVPWM is employed to generate synchronized PWM waveforms with three-phase, half-wave, and quarter-wave symmetries required for high-power drives. The principle of the SVPWM technique is based on the switching combinations of the inverter used. Eight switching combinations corresponding to eight stationary voltage vectors in space are available for a three-phase two-level inverter.

Fig. 1. Block diagram of a VSI-fed induction motor drive.

Two zero-voltage and six active space vectors are available. The flexibility in the placement of the zero-voltage space vector results in either continuous SVPWM or discontinuous SVPWM. The former is known as the continuous SVPWM (CSVPWM) strategy, and the latter is known as the discontinuous or bus clamping SVPWM (BCSVPWM) strategy. CSVPWM renders additional switching losses at high modulation index regions due to low-quality output waveforms. The application of a single zero-voltage space vector generates BCSVPWM [16]-[18]. Relative to continuous techniques such as the CSVPWM strategy, discontinuous techniques such as the BCSVPWM strategy achieve superior performance at high modulation indexes and reduce the switching losses at all modulation indexes. The optimal continuous PWM reported in [19] minimizes RMS current ripples in each half-carrier cycle and results in the lowest line current distortion among CSVPWM schemes. The concept of active state time division in clamping sequences further leads to advanced BCSVPWM strategies.

Hybrid SVPWM methods employing different combinations of sequences, including the combination of existing sequences, were presented in [21]-[23]. These hybrid SVPWM methods reduce line current distortions at various ranges of modulation indexes. Hybrid SVPWM methods designed to reduce harmonic distortions and switching losses were presented in [20]. Hybrid SVPWM techniques are classified into three categories according to the performance indexes. The first and second categories are developed for minimum current ripples and reduced switching losses, respectively. Meanwhile, the third category is developed to reduce current ripples and switching losses in motor drives and is compared with CSVPWM techniques, as mentioned in [21]. The hybrid SVPWM techniques under the third category are called hybrid SVPWM types I, II, III, and IV.

The preceding discussion indicates that two-level SVPWM is a broad topic that has received much attention in the literature over the years. The existing literature provides deep insights into the relationship between current total harmonic distortions (THDs) and flux ripples for various SVPWM switching sequences. The SVPWM strategy with a minimum- loss modulating function first appeared in a theoretical paper [22] devoted to the comparative analysis of PWM techniques for three-phase VSIs. Switching loss indicator (SLI) was introduced as a comparative measure of these losses. The SLI is calculated as the sum of the squared values of the output current at the switching instances of the inverter. A similar approach to the comparative evaluation of switching losses was proposed in [23]. In [23], the harmonic copper losses in an induction machine were analyzed, and the optimum PWM pattern for the minimization of harmonic losses was presented. The PWM technique discussed in the paper optimizes the RMS value of the harmonic current. An optimization of the PWM based on selective harmonic elimination for motor drives was discussed in [23]. Ahmet Hava analyzed the harmonic distortions of continuous and discontinuous PWM using the harmonic distortion function in [24]. The experimental verification was performed by measuring the weighted THD of the line voltage waveform. The switching loss calculation was theoretically verified from the waveform by using the switching loss function (SLF). The SLF is thought to be adequate for at least a general qualitative comparison of various PWM strategies. A similar approach to the comparative evaluation of switching losses was used in [25]. The detailed quantitative study of the comparable inverter losses under discontinuous and continuous PWM was presented in [26]. A. Trzynadlowski described a minimum switching loss SVPWM technique [26]. A quadratic coefficient-based expression called the quality factor was introduced to study the combined effects of switching losses and THDs. The quality factor is inversely related to THDs and switching losses. G. Narayanan et al. [13]-[17] developed various continuous and discontinuous SVPWM sequences and several SVPWM strategies on the basis of such sequences. The harmonic contents for various sequences in an induction motor were numerically compared by studying stator flux ripples. The RMS value of a stator flux ripple provides the harmonic content for the corresponding sequence. Analytical expressions were developed in the study to evaluate the performance of each sequence. Switching loss analysis is conducted by measuring energy losses in subcycles. The switching sequences are then optimized on the basis of either RMS flux ripples or switching losses. Therefore, these optimized sequences mainly focus on either harmonic distortions or switching losses. The best-performing THD reduction sequence may not provide the best- performing switching loss sequence. This technique cannot reduce RMS flux ripples and switching losses simultaneously. If switching loss reduction is the main focus, then switching sequences are optimized on the basis of switching losses for different power factor angles, and suitable sequences are selected to reduce flux ripples. These optimization techniques do not yield actual optimized sequences for harmonic distortions and switching losses. The preceding discussion shows that the chosen optimum sequences based on either switching losses or THD constraints clearly lead to a tradeoff between the quality of the output current and the amount of switching losses incurred in a converter.

Switching sequences are naturally diverse with respect to the number of switches in different SVPWM techniques. The performance of different continuous and discontinuous SVPWM techniques is mainly determined by the THD factor of the no-load current (I_THD) and switching losses. The harmonic distortion in a current is determined by the switching frequency and the employed PWM technique. Moreover, the harmonic distortion in motor phase currents must be low to achieve a satisfactory operation of motor drives. Inverter switching losses are unavoidable due to the finite number of on and off events of the semiconductor switches employed in VSIs. The best reduction in switching losses is 50% when a phase is clamped around the peak of the phase current, as reported in [21]. Switching frequencies in almost all inverter topologies are increased to reduce filtering requirements. A rise in switching frequency increases switching losses, thus reducing system efficiency and reliability.

The main objective of the present work is to develop a simple method for synthesizing an optimum hybrid SVPWM technique with minimum THDs and switching losses for a given maximum value of pulse number in a two-level inverter. Optimum switching sequences are considered on the basis of a joint optimization parameter referred to as the quality factor [26]. The optimized switching sequences obtained in [26] reduce the harmonic distortions for a given pulse number. In existing hybrid SVPWM techniques under no-load conditions of induction motor drives, the switching losses are under a specified limit because the pulse number is fixed and the switching sequence has discontinuity. The harmonic distortion in a current is determined by the switching sequence employed in the hybrid SVPWM technique. This study demonstrates that a considerable improvement of the hybrid SVPWM technique is feasible and results in high-quality output currents and greatly reduced switching losses in inverters. Considering all the available SVPWM strategies for performance improvement, this study aims to expand the link between harmonic distortion factor and switching loss factor under a linear modulation range without the distortion of waveform quality. Section II of this paper analyzes the background of the work. Section III explains the proposed hybrid SVPWM techniques. Section IV presents the experimental results. Section V provides the conclusions.

Ⅱ. BACKGROUND OF THE WORK

In the SVPWM technique, the reference voltage is provided by a revolving reference vector sampled once in every subcycle. The reference vector is realized by the nearest

         (1a)

         (1b)

where is the reference vector and is the sampling period. and are the dwell times of active vectors and , respectively. is the total dwell time of zero vectors and .

The dwell times , , and are respectively defined as

      (2a)

         (2b)

         (2c)

The modulation index (m_i) is defined by the ratio of the reference voltage and input DC voltage . m_i is further modified as the reference vector ( ) normalized with respect to . The preceding equation can be written as

      (3a)

         (3b)

A. Analysis of Flux Ripple

In the space vector PWM approach, the applied voltage is equal to the reference voltage only in an average sense over the given sampling interval and not in an instantaneous fashion. The difference between applied voltage () and reference voltage () is defined as the error voltage (). The instantaneous error voltages in the α–β plane are illustrated in Fig. 3(a) for a reference voltage () at sector I. The mathematical formulation of instantaneous error voltages can be defined by the following expressions:

      (4)

Fig. 2. Representation of: (a) Error voltages; (b) Flux ripples corresponding to V_ref in sector I.

(a)

(b)

Fig. 3. Vector and d-q diagram representation of a flux ripple: (a) Representation of a flux ripple corresponding to V_ref in sector I; (b) Stator flux ripple vector over a subcycle for sequence 0127.

(a)

(b)

where and are the error voltage vectors corresponding to active vectors and , respectively. The error voltage corresponds to zero-voltage vector or . The instantaneous error voltage causes a ripple in flux linkage in the machine. The relation between flux ripples and error voltages is described by the following expression:

        (5)

The different components of a flux ripple can be resolved along the d- and q-axes, which are the reference axes of a synchronously revolving reference frame, as shown in Fig. 3(b). For a reference voltage in sector I, the corresponding flux ripple components along the d- and q-axes are described as follows:

     (6a)

          (6b)

          (6c)

The magnitude of the resultant flux ripple along the d- and q-axes is given by the following expressions:

           (7a)

       (7b)

The magnitude of each term is expressed by the following equations.

    (8a)

          (8b)

      (9a)

          (9b)

   (10)

where , , , and are the error voltage components in the d- and q-axes. From all the preceding analytical expressions, the instantaneous RMS flux ripple of a switching sequence can be evaluated on the basis of the modulation index and location of the reference vector. Therefore, the instantaneous RMS flux ripple of a switching sequence can be generalized by the following expression:

           (11)

where , , and are the resultant instantaneous RMS flux ripple, q-axis, and d-axis components of the instantaneous RMS flux ripple of a switching sequence, respectively. The trajectories of the voltage vectors for different possible switching sequences and the corresponding flux ripple components along the d- and q-axes are illustrated in Fig. 4 for a reference voltage () in sector I. The application of any active voltage vector clearly results in variations of the d- and q-axis components, whereas the application of a zero-voltage vector leads only to variations of the q-axis component of the flux ripple. The analytical expressions (10–16) of the resultant RMS flux ripple in terms of the d- and q-axis components (obtained from Fig. 4) for all the switching sequences in sector I are given below.

       (12)

     (13)

     (14)

         (15)

   (16)

    (17)

   (18)

Fig. 4. Representation of flux ripple corresponding to: (a) ; (b) ; (c) ; (d) ; (e) ; (f) ; (g) .

Trajectory	q axis ripple	d axis ripple
	(a)
	(b)
	(c)
	(d)
	(e)
	(f)
	(g)

The preceding analytical expressions are simplified and obtained in terms of sampling time (T_s) and as a polynomial expression of the reference voltage.

   (19)

The coefficient values of , , and are listed in Table I. The resultant RMS flux ripple is evaluated for modulation indexes of 0.55 and 0.865, as shown in Figs. 5(a) and 5(b), respectively. The reference angle is varied from 0° to 60°. The conventional sequence is satisfactory at a low modulation index with an angle between 15° to 45°. The resultant RMS flux ripple for double switching sequences and is also shown in Fig. 5. performs well in the first part of the sector from 0° to 15°, whereas performs well in the second part of the sector from 45° to 60°. Similarly, if the observation is conducted at the high modulation index region of 0.865, then and perform well at angles of 50°–30° and 30°–55°, respectively. performs well in the first part of the sector from 0° to 50°, whereas performs well in the second part of the sector from 55° to 60°. The sequence has a low ripple value at the low modulation index of 0.55. Meanwhile, has a low modulation index ranging from 0.55 to 0.68. The graphs of the RMS ripple characteristics provide an idea of the spatial distribution of the switching sequence that performs well in a sector. The resultant RMS flux ripple that is normalized with respect to the fundamental flux (ψ₁) provides the THD measure of a switching sequence. The THD of a switching sequence can be evaluated as follows:

       (20)

TABLE I COEFFICIENTS B0, B1, AND B2 OF RMS FLUX RIPPLE FOR DIFFERENT SEQUENCES

Switching sequence	B0	B1	B2

Fig. 5. Ripple variation of switching sequences in sector I with reference vector angle α with magnitudes: (a) m_i = 0.55; (b) m_i = 0.865.

(a)

(b)

The fundamental flux (ψ₁) is expressed by

      (21)

where is the fundamental frequency of the supply voltage. The fundamental frequency of the reference voltage is obtained from the following equation in terms of the modulation index (m_i) corresponding to a six-step operation [12]:

         (22)

   (23)

The THD variation of the sequences with modulation index variation is shown in Fig. 6.

Fig. 6. THD variation of switching sequences with variation of modulation index from 0.55 to 0.865.

B. Switching Loss Analysis of a Sequence

The performance evaluation of various switching sequences in terms of switching loss is discussed in this section. Consider the R phase. The switching energy loss per subcycle in the R phase is proportional to the DC bus voltage, device switching times, and R-phase current. Only the fundamental component of the R-phase current (iR) is considered because the contribution of the ripple current to this energy loss is insignificant. The switching energy loss is also proportional to the number of switches (n_R) of the R phase in the given subcycle, which depends on the switching sequence used [25]. For simplicity, the product of i_R and n_R can be regarded as a measure of the energy lost due to switching in a phase. Table II shows the number of switches of different sequences for various phases. The average switching loss of a sequence per phase over a fundamental cycle is given by the switching loss of the inverter, which is measured on the basis of the following expression:

   (24)

   (25)

TABLE II NUMBER OF SWITCHES FOR VARIOUS PHASES FOR DIFFERENT SEQUENCES

Sl. No	Sequence	Phase R switching (nR)	Phase Y switching (nY)	Phase B switching (nB)
1	0127-7210	1	1	1
2	012-210	1	1	0
3	721-127	0	1	1
4	1012-2101	2	1	0
4	0121-1210	1	2	0
4	7212-2127	0	2	1
5	2721-1272	0	1	2

where x represents R, Y, and B phases.

     (26)

The normalization of the total switching loss of a sequence is performed with respect to the continuous PWM strategy and is defined as SLF.

       (27)

           (28)

Various switching sequences are compared on the basis of the SLF, which is a function of the power factor. The variation of the switching loss at 90° and 30° lag in a sector is shown in Fig. 7. and have low switching losses from 0° to 30° and 30° to 90°, respectively, in the first half of the sector. The double switching sequences incur more switching losses than the single switching sequences do. At a power factor angle of 39°, has a low switching loss over the entire reference angle of 0° to 60°. The reference angle variation is studied from −90° to 90°, as shown in Fig. 8. has a low switching loss from −90° to −65° (lag), and has a minimum switching loss from −85° to 0° (lag). and have low switching losses from 0° to 85° (lead) and from 85° to 90° (lead), respectively. The switching losses show peak values for double switching sequences at various power factor ranges of the lag and lead. The normalized switching loss is computed from a power factor angle of −90° to 90°. Evidently, double switching sequence has a low switching loss at the power factor angle ranging from −90° to −30°. The switching sequences , , and show a satisfactory operating performance in the corresponding power factor ranges of −30° to 0°, 0° to 30°, and 30° to 90°, respectively. The SLF characteristics provide well-performing sequences with minimal switching losses in a sector.

Fig. 7. Variation of switching loss of switching sequences in sector I with reference vector angle α with magnitudes: (a) 90° lag; (b) 30° lag.

(a)

(b)

Fig. 8. Variation of switching loss of switching sequences with the power factor angle ranging from −90° to 90°.

C. Joint Optimization

The quality of a PWM is determined by the tradeoff between THDs and incurred switching losses. The impact of switching frequencies varies with different hybrid SVPWM strategies due to the different sequences used. Quality factor is used as a measure of performance index [26] to overcome this difficulty. Quality factor is obtained as a quadratic relation that is inversely related to THDs and switching losses.

        (29)

A combination of sequences that consider the 𝑄𝑢𝑎𝑙𝑖𝑡𝑦 𝐹𝑎𝑐𝑡𝑜𝑟 parameter can further improve switching losses and THDs, as explored in the following section. The classification of the switching sequences [27] requires an elaborate study of existing hybrid sequences, which are categorized by providing importance to harmonic distortion values only. In this work, the switching sequences are classified according to their quality factor values, and the number of switches is restricted to only one phase at any given time. Hence, the switching events and switching losses are reduced relative to those in previous hybrid techniques [21]. The number of switches per subcycle is analyzed with the harmonic distortion of the output voltage under different modulation indexes. The switching states and sequences are selected in a simple manner after considering both constraints of PWM under the linear region of operation. The 𝑄𝑢𝑎𝑙𝑖𝑡𝑦 𝐹𝑎𝑐𝑡𝑜𝑟 of the SVPWM switching sequence depends on modulation index (m_i), power factor angle (φ), and reference angle location (α). The maximum value of the quality factor determines the optimum switching sequences for a specific modulation index, reference angle, and power factor for two-level inverters. Therefore, an efficient minimum ripple switching loss SVPWM (MRSLPWM) algorithm is developed on the basis of the optimized switching sequences that can optimize THDs and switching losses. The proposed MRSLPWM method addresses THD and switching loss issues without any complex computations. The switching sequences are analytically mapped in the optimized zones in the sector. The 𝑄𝑢𝑎𝑙𝑖𝑡𝑦 𝐹𝑎𝑐𝑡𝑜𝑟 values are computed for all the seven switching sequences of sector I in two-level inverters for different modulation indexes and power factor angles (φ). The values of the quality factor for power factor angles φ = 30° and 90° with modulation indexes 0.55, 0.65, 0.75, and 0.865 are plotted in Figs. 9(a)–(d) and Figs. 10(a)–(d). The switching sequences and evidently produce the best quality factor value for m_i = 0.55 for power factor angle φ = 90° in the first half (0° < α < 30°) and second half (30° < α < 60°) of sector I, respectively, as shown in Fig. 9(a). The and sequences are satisfactory in the range of (20° < α < 30°) to (30° < α < 40°) at a modulation value of 0.75. Similarly, switching sequences and , along with , , and , perform better than the other sequences do in the modulation index region m_i = 0.865, as shown in Fig. 9(d). Figs. 10(a)–(d) present the quality factor at power factor angle φ = 30°. The switching sequences , , and outperform other sequences in the entire modulation index region. Furthermore, Fig. 10(a) shows that and are better than the other sequences over a wide range of α for m_i = 0.55. Sequences and perform well in the power factor angle φ = 30° with m_i = 0.865. Thus, the various sequences exhibit good complementarity in reducing switching losses and THDs over different ranges of power factor. Following the same procedure, the high-quality switching sequences for sector I switching states are obtained.

Fig. 9. Quality factor variation of switching sequences in sector I with reference vector angle α with magnitudes: (a) m_i = 0.5; (b) m_i = 0.65; (c) m_i = 0.75; (d) m_i = 0.865 for power factor angle (φ) = 90°.

(a)

(b)

(c)

(d)

Fig. 10. Quality factor variation of switching sequences in sector I with reference vector angle α with magnitudes: (a) m_i = 0.5; (b) m_i = 0.65; (c) m_i = 0.75; (d) m_i = 0.865 for power factor angle (φ) = 30°.

(a)

(b)

(c)

(d)

The high-quality switching sequences for sector I are listed in Tables III and IV according to their optimum operating range of modulation index and reference angle range, respectively. The considerable improvement of the existing SVPWM technique is feasible, a high-quality output current is maintained, and switching losses in the inverter are markedly reduced. The improvement in quality factor indicates the improvement in the efficiency of the inverter operation in comparison with previous hybrid methods. The various optimal sequences and existing hybrid sequences are analyzed on the basis of the polynomial equations of THDs in terms of modulation indexes and switching losses and the number of switches and power factor. The optimized sequences for the existing hybrid sequences are listed in Tables V to VIII. The analytical evaluation of THDs for the proposed hybrid SVPWM and existing hybrid sequences are listed in Tables IX to XII.

TABLE III OPTIMIZED SWITCHING TABLE FOR MRSLPWM 90°

Sequence/ mi	0.55	0.65	0.75	0.865
Reference  Angle  Location (α )
	26°- 34°
		26°- 30°	18°- 30°	9.3°- 15.5°
		30°- 33°	30°- 42°	44°- 50.2°
				15.5°- 30°
				30 °- 44°
	0°- 26°	0°- 26°	0°- 18°	0°- 9.3°
	34°- 60°	33°- 60°	42°- 60°	50.2°- 60°

TABLE IV OPTIMIZED SWITCHING TABLE FOR MRSLPWM 30°

Sequence/ mi	0.55	0.65	0.75	0.865
Reference  Angle  Location  (α )
	0°- 60°	0°- 60°	0°- 26°  44°- 60°	0°- 12°
			26°- 44°	18°- 60°
				12 °- 18°

TABLE V SWITCHING TABLE FOR TYPE-I SEQUENCE

Sequence/ mi	0.55	0.65	0.75	0.865
Reference  Angle  Location  (α )
	0°- 60°	0°- 60°	0°- 13°  47°- 60°	0°- 5°  55°- 60°
			13°- 47°	5°- 55°

TABLE VI SWITCHING TABLE FOR TYPE-II SEQUENCE

Sequence/ mi	0.55	0.65	0.75	0.865
Reference  Angle  Location  (α )
	0°- 44°	0°- 28°	0°- 13°	0°- 5°
			13°- 45°	5°- 54°
	44°- 60°	28°- 60°	45°- 60°	54°- 60°

TABLE VII SWITCHING TABLE FOR TYPE-III SEQUENCE

Sequence/ mi	0.55	0.65	0.75	0.865
Reference  Angle  Location  (α )
	0°- 60°	0°- 16°  51°- 60°	0°- 6°  54°- 60°	0°- 3°  57°- 60°
		16°- 51°	6°- 20°  36°- 54°	3°- 8°  52°- 57°
			20°- 36°	8°- 52°

TABLE VIII SWITCHING TABLE FOR TYPE-IV SEQUENCE

Sequence/ mi	0.55	0.65	0.75	0.865
Reference  Angle  Location  (α )
	0°- 28°	0°- 16°	0°- 6°	0°- 3°
	28°- 42°	16°- 48°	6°- 20°  36°- 54°	3°- 8°  52°- 56°
			20°- 36°	8°- 52°
	42°- 60°	48°- 60°	54°- 60°	56°- 60°

TABLE IX THD EXPRESSION FOR PROPOSED AND EXISTING SVPWM METHODS AT N = 7

Sequence(mi =0.55)	THD
MRSLPWM 30
MRSLPWM 90
Type I
Type II
Type III
Type IV

TABLE X THD EXPRESSION FOR PROPOSED AND EXISTING SVPWM METHODS AT N = 7

Sequence(mi =0.65)	THD
MRSLPWM 30
MRSLPWM 90
Type I
Type II
Type III
Type IV

TABLE XI THD EXPRESSION FOR PROPOSED AND EXISTING SVPWM METHODS AT N = 7

Sequence(mi =0.75)	THD
MRSLPWM 30
MRSLPWM 90
Type I
Type II
Type III
Type IV

TABLE XII THD EXPRESSION FOR PROPOSED AND EXISTING SVPWM METHODS AT N = 7

Sequence(mi =0.865)	THD
MRSLPWM 30
MRSLPWM 90
Type I
Type II
Type III
Type IV

TABLE XIII SEQUENCES FOR LOADED CONDITIONS

Sample Number	Modulation Index	Placement Angle	Samples
7	0.55	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°
7	0.65	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°
7	0.75	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°
7	0.865	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°

TABLE XIV SEQUENCES FOR NO-LOAD CONDITIONS

Sample Number	Modulation Index	Placement Angle	Samples
7	0.55	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°
7	0.65	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°
7	0.75	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°
7	0.865	4.3°, 12.9°, 21.4°, 30°, 38.6°, 47.1°, 55.7°

Ⅲ. PROPOSED HYBRID SVPWM

The sampling time (T_s) is varied in different SVPWM techniques in [26], [27]. In the proposed SVPWM approach, the fundamental frequency is fixed at 50 Hz, and no adjustment is made for different switching sequences. The variation of the quality factor with respect to the reference angle is used to determine the optimum switching sequences for two-level inverters. This parameter is also used to analyze THD and switching loss performance for a particular strategy with a given maximum value of pulse number corresponding to two-level inverters. The samples are generally placed equidistantly in two-level inverter configurations. The existing approaches of hybrid SVPWM clearly do not follow single switching transitions in the sector while switching from one zone to another under no-load conditions. This phenomenon leads to double switching transition between neighboring samples with existing approaches. Some of the existing approaches [18]–[21] that provide single switching transitions do not select the optimum sequences for THDs and switching losses. The proposed algorithm takes a design approach and explores a global map for all optimum sequences. The methodology enforces one switching transition while crossing the sector boundaries, maintains symmetry properties, and achieves a minimum THD for a given pulse number. The design of the hybrid SVPWM technique involves two steps, namely, (1) selection of a set of switching sequences and (2) determination of boundaries of various subsectors [14]. Both design steps influence harmonic distortions and inverter switching losses. The hybrid SVPWM technique divides each sector into spatial regions termed as subsectors and employs different sequences in the various subsectors. The selection of optimum switching sequences is dependent on φ, α, and m_i.

The main focus in this study is to design hybrid PWM techniques that lead to (1) reduced inverter switching losses and (2) reduced THDs in line current, with CSVPWM as a benchmark. The study of THDs and switching losses in Section II shows that sequences , ,,and are good choices at φ = 90° lagging power factor. Similarly, optimum sequences are found for different lagging power factors from Figs. 9 (a–d) and 10(a–d). All these sequences can be appropriately deployed to achieve reduced THDs and switching losses over some range of lagging power factor. Therefore, existing SVPWM sequences are evaluated on the basis of the quality factors for different power factor regions. In this work, optimized hybrid sequences, namely, MRSLPWM 90 for no-load machine condition and MRSLPWM 30 for loaded machine conditions, are developed.

The analytical evaluation of quality factor characteristics for the proposed hybrid MRSLPWM 90 and MRSLPWM 30 SVPWM techniques in relation to existing hybrid SVPWM techniques is shown in Figs. 11(a)–(b). MRSLPWM 90 and 30 SVPWM sequences evidently provide high a Quality Factor relative to existing hybrid SVPWM sequences. The proposed hybrid SVPWM techniques are suitable for lagging power factors φ = 30° and 90°. The analytically evaluated switching sequences with high a Quality Factor are listed in Tables III to VIII on the basis of the modulation index and reference angle location. Tables III to VIII are presented using area in sector I of the hexagon space vector diagram. The plot is established for various optimized switching sequences on the basis of the modulation index and angle value in the hexagonal plane for sector I using scattering plots. The zone or area of superior performance for a given switching sequence is illustrated with a spatial zone distribution within a sector in Figs. 12–14. The areas of optimized switching sequences for hybrid SVPWM Types I, II, III, and IV are shown in Figs. 14 (a)–(d).

Fig. 11. Analytical evaluation of quality factor variations with modulation index: (a) MRSLPWM 90; (b) MRSLPWM 30.

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Fig. 12. Spatial regions for MRSLPWM 30.

Fig. 13. Spatial regions for MRSLPWM 90.

Fig. 14. Spatial region for: (a) Hybrid SVPWM Type I sequence; (b) Hybrid SVPWM Type II sequence; (c) Hybrid SVPWM Type III sequence; (d) Hybrid SVPWM Type IV sequence.

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Ⅳ. SIMULATION AND EXPERIMENTAL RESULTS

In this work, the effectiveness of the proposed minimum loss SVPWM and the performance of the control method for induction motor drives are investigated via computer simulations using MATLAB. PWM for inverters is fully modeled and controlled using a hybrid SVPWM technique. The design parameter of the inverter is 400 V DC, and the switching frequency ranges from 850 Hz to1250 Hz.

The simulation waveforms of three-phase pole voltages with line voltage, pole voltage with phase current waveform, and FFT spectrum for MRSLPWM 90 and MRSLPWM 30 are shown in Figs. 15(a)–(c) and 16(a)–(c), respectively. The analytical evaluation of quality factor is at par with the simulation results, and the superiority of the proposed method is validated from the simulation. An open loop v/f control is implemented in a single PIC microcontroller (PIC18F452) with a compiler optimized architecture. The open-loop architecture considers the fixed value of the modulation index, and bus voltage is varied through an autotransformer to obtain a variable output voltage. This condition is a two-stage process. In the first stage, code is optimized in Linux, and the output is optimized for an 8-bit PIC microcontroller. The samples can be placed at exactly 30° because the timing and pulse generation are maintained in a centralized and synchronized manner.

Fig. 15. Simulation results: (a) Pole voltage and line voltage waveforms; (b) Pole voltage waveform along with current waveform; (c) FFT spectrum at m_i = 0.65 for MRSLPWM 90.

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Fig. 16. Simulation results: (a) Pole voltage and line voltage waveforms; (b) Pole voltage waveform along with current waveform; (c) FFT spectrum at m_i = 0.65 for MRSLPWM 30.

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An IGBT-based 2 kVA two-level VSI is designed and developed. The proposed work is experimentally verified with a three-phase induction motor. The parameters of the induction motor under testing are as follows: 2.2 kW, 415 V, 4 A, 50 Hz, (cos(φ = 0.82), and 1420 rpm. The line voltage, pole voltage, line current, and FFT spectrum of the line voltage for the existing SVPWM (hybrid SVPWM Types I–IV) strategies obtained from the experimental setup are shown in Figs. 17–24.

Fig. 17. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type I SVPWM technique for power factor angle (φ) = 90° with mi = 0.65.

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Fig. 18. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type II SVPWM technique for power factor angle (φ) = 90° with mi = 0.65.

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Fig. 19. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type III SVPWM technique for power factor angle (φ) = 90° with mi = 0.65.

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Fig. 20. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type IV SVPWM technique for power factor angle (φ) = 90° with mi = 0.65.

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Fig. 21. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type I SVPWM technique for power factor angle (φ) = 30° with mi = 0.65.

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Fig. 22. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type II SVPWM technique for power factor angle (φ) = 30° with mi = 0.65.

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Fig. 23. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type III SVPWM technique for power factor angle (φ) = 30 with mi = 0.65.

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Fig. 24. Hardware results: (a) Pole voltage and line current waveform; (b) Line voltage waveforms and FFT spectrum of Type IV SVPWM technique for power factor angle (φ) = 30° with m_i = 0.65.

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Figs. 25–26 show the line voltage, pole voltage, line current, and FFT spectrum of the line voltage for the proposed MRSLPWM 90 and MRSLPWM 30.

Fig. 25. Hardware results: (a) Line voltage waveform along with FFT spectrum; (b) Pole voltage waveform along with current waveform; (c) Three-phase pole voltage waveform at (φ) = 90° with m_i = 0.65.

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Fig. 26. Hardware results: (a) Line voltage waveform along with FFT spectrum; (b) Pole voltage waveform along with current waveform; (c) Three-phase pole voltage waveform (φ) = 30° with m_i = 0.65.

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The performance of different SVPWM strategies depends on specific switching sequences, clamping type, pulse number, or number of switching and modulation index values. The normalized value of harmonic content in line voltage waveform, V_wthd, is defined as

           (30)

where V₁ and V_n are the RMS values of the fundamental and nth harmonic voltage of the line voltage waveform, respectively. The weighted voltage THD is approximately proportional to the current THD and independent of motor parameters. The performance based on weighted voltage THD is calculated for the modulation index range (m_i) 0.5 to 0.865. The weighted THD curves for MRSLPWM 90 and MRSLPWM 30 are shown in Fig. 27. The SLF curves for MRSLPWM 90 and MRSLPWM 30 are shown in Fig. 28. SLF is determined in terms of the number of switching transitions of the pole voltage on the current waveform. The 𝑄𝑢𝑎𝑙𝑖𝑡𝑦 𝐹𝑎𝑐𝑡𝑜𝑟 for each SVPWM strategy is computed from the experimental results, and the outcomes are presented in Fig. 29.

Fig. 27. Performance comparison of weighted THD for: (a) MRSLPWM 90; (b) MRSLPWM 30.

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Fig. 28. Comparison of switching losses of: (a) MRSLPWM 90; (b) MRSLPWM 30.

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Fig. 29. Quality factor comparison of: (a) MRSLPWM 90; (b) MRSLPWM 30.

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The proposed hybrid SVPWM techniques are compared with existing techniques. Four representative modulation index values, namely, 0.55 ,0.65, 0.75, and 0.865, are considered over the linear modulation range for various SVPWM strategies. Different strategies produce different pulse numbers for a particular modulation index. Linear interpolation is used to plot data for the missing pulse number to generate performance curves. The THD obtained from the experimental results is analyzed, and V_wthd characteristics under no-load and loaded conditions are plotted. The proposed hybrid SVPWM techniques clearly produce minimal THDs in the linear modulation index region of 0.75 and provide moderate performance above 0.75. The optimized hybrid techniques result in moderate THDs in comparison with the existing hybrid strategies at a modulation value of 0.75. The proposed method performs well above m_i of 0.75 at a power factor of 30°.

The SLF for the proposed hybrid SVPWM for φ = 30° and φ = 90° is lower than those for existing hybrid SVPWM sequences. Fig. 28 demonstrates that the switching loss performance for the proposed hybrid SVPWM for φ = 90° and φ = 30° is greater than that for existing strategies and CSVPWM in the corresponding power factor range. The performance summary of the proposed hybrid SVPWM techniques in comparison with existing hybrid SVPWM techniques is computed using the following expression for various parameters listed in Tables XV to XVIII:

   (31)

TABLE XV PERFORMANCE SUMMARY FOR SAMPLE NUMBER = 7 AT MODULATION INDEX (MI = 0.55)

Technique	THD		Switching loss		Quality factor
	No load	load	No load	load	No load	load
Hybrid PWM Type I	100%	100%	100%	100%	100%	100%
Hybrid PWM Type II	81%	93.9%	92%	108.14%	132.8%	98.4%
Hybrid PWM Type III	102.17%	69%	91%	85.19%	106.8%	168.3%
Hybrid PWM Type IV	126%	81%	90.37%	85%	87.7%	143%
MRSLPWM 90	82%		82.96%		145%
MRSLPWM 30		84%		55.56%		207%

TABLE XVI PERFORMANCE SUMMARY FOR SAMPLE NUMBER = 7 AT MODULATION INDEX (M_I = 0.65)

Technique	THD		Switching loss		Quality factor
	No load	load	No load	Load	No load	load
Hybrid PWM Type I	100%	100%	100%	100%	100%	100%
Hybrid PWM Type II	84%	91%	92%	101.82%	109%	101.8%
Hybrid PWM Type III	127%	91%	87.8%	70.25%	89%	156.25%
Hybrid PWM Type IV	117%	81%	84%	94.9%	101%	128.3%
MRSLPWM 90	76%		70%		185%
MRSLPWM 30		74%		56%		196%

TABLE XVII PERFORMANCE SUMMARY FOR SAMPLE NUMBER = 7 AT MODULATION INDEX (MI = 0.75)

Technique	THD		Switching loss		Quality factor
	No load	load	No load	load	No load	load
Hybrid PWM Type I	135.7	99	110.7	92.98	130	107.6
Hybrid PWM Type II	100	100	100	100	100	100
Hybrid PWM Type III	102.14	97	121.4	81.4	121.1	123.6
Hybrid PWM Type IV	101.4	94	125	98.9	78	107
MRSLPWM 90	107.1		78.5		150
MRSLPWM 30		92.9		59.65		180.5

TABLE XVIII PERFORMANCE SUMMARY FOR SAMPLE NUMBER = 7 AT MODULATION INDEX (MI = 0.865)

Technique	THD		Switching loss		Quality factor
	No load	load	No load	load	No load	load
Hybrid PWM Type I	94	88	117	81.69	89	139
Hybrid PWM Type II	55	79	117.8	87	164	142
Hybrid PWM Type III	68	76	124	91.5	152	137.7
Hybrid PWM Type IV	52	84	125	88	117	200
MRSLPWM 90	50		110.7		190.7
MRSLPWM 30		64		73		213

At lagging power factor φ = 30° and at a modulation index of 0.65, the percentage reduction of switching losses in the proposed hybrid SVPWM is 44%. The average percentage reduction values of the weighted THDs for the proposed hybrid SVPWM in comparison with CSVPWM are 34% and 36% at lagging power factor φ = 30° and 90°, respectively. The corresponding percentage reduction values of the weighted THDs for the best existing hybrid techniques in comparison with CSVPWM are 16% and 19% at φ = 30° and φ = 90°, respectively. The average percentage reduction values of the switching losses for the proposed hybrid SVPWM in comparison with CSVPWM are 44% and 30% at lagging power factor φ = 30° and 16% at φ = 90°. The corresponding percentage reduction values of switching losses by the best existing hybrid techniques in comparison with CSVPWM are 29.9% and 16% at φ = 30° and φ = 90°, respectively. This considerable reduction further improves the quality factor performance by 30% and 80% under MRSLPWM 30 and MRSLPWM 90 conditions, respectively. Therefore, the proposed hybrid SVPWM techniques for 30° and 90° perform better than existing advanced SVPWM techniques do in certain power factor regions.

The quality factor metric is used to assess the quality of the output current and the efficiency of the inverter operation. This parameter also measures the quality of various PWM strategies. The MRSLPWM 𝑄𝑢𝑎𝑙𝑖𝑡𝑦 𝐹𝑎𝑐𝑡𝑜𝑟 outperforms that of the best hybrid SVPWM strategies under no-load and loaded conditions of induction motor drives by 76% and 40%, respectively.

Ⅴ. CONCLUSION

A new version of a space vector hybrid PWM technique called MRSLPWM is developed on the basis of the quality factor metric. The MRSLPWM strategy differs from existing hybrid SVPWM methods in terms of the employed state sequence within a switching interval, which improves the quality of output waveforms and inverter efficiency. MRSLPWM is compared with known hybrid SVPWM techniques for performance analysis. The proposed PWM pattern is tested with an induction motor drive. An effective reduction in THDs and switching losses is obtained from the experimental analysis. An excellent tradeoff between THDs and switching losses is achieved, thereby making the MRSLPWM strategy distinctly superior to existing hybrid SVPWM techniques.

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G. Vivek received his B.Tech degree in Electrical and Electronics Engineering from the University of Calicut, Kerala, India, in 2009; and his Master of Engineering Degree in Power Electronics and Drives from Anna University, Tamil nadu, India, in 2011. He is currently working toward his Ph.D. degree from the Department of Electrical Engineering National Institute of Technology, Calicut, India. His research interests are pulse width modulation control in multilevel inverters and pulse width modulation techniques for drives.

Jayanta Biswas received his B.E. degree in Computer Science from Bengal Engineering College, Shibpur, Howrah, India, in 1993; and his M.E. and Ph.D. degrees in System Science and Automation from the Indian Institute of Science, Bengaluru, India, in 1995 and 2006, respectively. From January 1995 to 1998, he was with NCR, Columbia, SC. From January 1999 to November 2002, he was with Alcatel Internetworking, Calabasas, CA. He served as the Project Manager of the Alcatel Internetworking ATM (core and edge) switch software development effort from May 2000 to November 2002 and led the 10 Gigabit software development effort. He worked at CEM Solutions, Bangalore, where he led embedded product development and research activities as the Technical Director. He served as an Assistant Professor at the International Institute of Information Technology (IIIT), Bangalore, under the Embedded Systems and VLSI group. His current research interests include digital controller architecture for power management application ICs and modulation techniques for multi-level power electronics converters.

Meenu D. Nair received her B.Tech. degree in Electrical and Electronics Engineering from the Govt. Rajiv Gandhi Institute of Technology, Kottayam, India, in 2009; her M.Tech. degree in Power Electronics from SASTRA University, Tanjavur, India, in 2011; and her Ph.D. degree from the Department of Electrical Engineering at the National Institute of Technology, Calicut, India, in 2018. She is currently working as an Assistant Professor at Karpagam College of Engineering, Tamil Nadu India. Her research interests are multilevel inverters and pulse width modulation techniques for drives.

Mukti Barai received her B.E. degree in Electrical Engineering from Bengal Engineering College, Shibpur, Howrah, India, in 1992, and M. Tech. and Ph.D. degrees in Machine Drives and Power Electronics from the Indian Institute of Technology, Kharagpur, India, in 1994 and 2009, respectively. From 1994 to 2000, she was a Senior Engineer (Design and Development) in the Electronics Division, Bharat Heavy Electricals Limited, Bangalore, India. She was a Principal Software Development Engineer at Alcatel Internetworking, Inc. from 2002 to 2002. From 2003 to 2004, she was at ST Microelectronics Research Laboratory in Indian Institute of Science (IISc), Bangalore. She is currently working as Associate Professor at the National Institute of Technology (NIT), Calicut. Her research interests include modulation techniques for multi-level power electronics converter and digital controller architecture for power management application ICs.