https://doi.org/10.6113/JPE.2018.18.6.1791

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Deadbeat and Hierarchical Predictive Control with Space-Vector Modulation for Three-Phase Five-Level Nested Neutral Point Piloted Converters

Junjie Li^†, Xiangyu Chang^**, Dirui Yang^*, Yunlong Liu^***, and Jianguo Jiang^*

^†,*Key Laboratory of Control of Power Transmission and Conversion, Ministry of Education, Shanghai Jiao Tong University, Shanghai, China

^**School of Russian and Eurasian Studies, Shanghai International Studies University, Shanghai, China

^***School of Mechanical Electronic and Information Engineering, China University of Mining and Technology, Beijing, China

Abstract

To achieve a fast dynamic response and to solve the multi-objective control problems of the output currents, capacitor voltages and system constraints, this paper proposes a deadbeat and hierarchical predictive control with space-vector modulation (DB-HPC-SVM) for five-level nested neutral point piloted (NNPP) converters. First, deadbeat control (DBC) is adopted to track the reference currents by calculating the deadbeat reference voltage vector (DB-RVV). After that, all of the candidate switching sequences that synthesize the DB-RVV are obtained by using the fast SVM principle. Furthermore, according to the redundancies of the switch combination and switching sequence, a hierarchical model predictive control (MPC) is presented to select the optimal switch combination (OSC) and optimal switching sequence (OSS). The proposed DB-HPC-SVM maintains the advantages of DBC and SVM, such as fast dynamic response, zero steady-state error and fixed switching frequency, and combines the characteristics of MPC, such as multi-objective control and simple inclusion of constraints. Finally, comparative simulation and experimental results of a five-level NNPP converter verify the correctness of the proposed DB-HPC-SVM.

Key words: Capacitor voltage balancing control, Deadbeat control, Five-level, model predictive control, Nested neutral point piloted, Space-vector modulation, Stacked multicell converter

Manuscript received May 13, 2018; accepted Aug. 29, 2018

Recommended for publication by Associate Editor Kai Sun.

^†Corresponding Author: lijunjie@sjtu.edu.cn Tel: +86-18817227992, Shanghai Jiao Tong University

*Key Laboratory of Control of Power Transmission and Conversion, Ministry of Education, Shanghai JiaoTong University, China

**School of Russian and Eurasian Studies, Shanghai International Studies University, China

***School of Mechanical Electronic & Information Engineering, China University of Mining and Technology, China

Ⅰ. INTRODUCTION

Multilevel converters have been widely applied to the grid integration of renewable energy sources, motor drives and other fields [1]-[3]. Stacked multicell converters (SMCs) are presented in [4]-[10], which stack several flying capacitor (FC) converters together. When compared to FC converters, SMCs require less energy storage in the capacitors and have lower switching losses. In [9] and [10], a five-level SMC is described as a five-level nested neutral point piloted (NNPP) converter that is nested by the two modular structures of the phase-leg of a three-level neutral point piloted (NPP) converter.

In order to balance the capacitor voltages for the SMC, some capacitor voltage balancing methods based on pulse width modulation (PWM) are presented in [8]-[10]. In [9], a space vector pulse width modulation (SVPWM) for five-level NNPP converters is proposed to achieve the decoupling control strategies of capacitor voltages and reduce the common-mode voltage. The conventional proportional-integral (PI) controllers with PWM schemes are one of the most common solutions to control power converters. However, the performance of PI controller is closely related to the controller parameters, bandwidth and stability of the controller. Moreover, the dynamic response is slow, especially for cascade PI control. In order to address the problems of the conventional PI+ PWM, some advanced control strategies are proposed. These strategies include as direct torque control (DTC) [11], direct power control (DPC) [12], deadbeat control (DBC) [13]-[15], and model predictive control (MPC) [16]-[22].

MPC is one of the most promising controllers for power electronic converters [16]-[27]. MPC has the advantages of simple concept, a fast dynamic response, multi-objective control, and easy inclusion of nonlinearities and constraints [18]-[27]. Finite control set MPC (FCS-MPC) takes advantage of the inherent discrete nature of power electronic converters to generate the control signals without an external modulator [18]-[27]. However, traditional FCS-MPC has some disadvantages. These disadvantages include high sampling frequency, high computational burden, complex weighting factor design, and variable switching frequency.

In multilevel converters, the number of candidates of switching states for FCS-MPC increases geometrically with the increase of the output levels [27]. Therefore, the improved FCS-MPC is still an open issue to be investigated to reduce the computational burden [21]. In order to address the issue of the high computational burden in the conventional FCS-MPC, some improved MPC strategies with a reduced computational burden have been proposed in [22]-[24], [27].

In [25], a traditional FCS-MPC for five-level SMC is proposed to achieve the multi-objective control of the load currents and floating-capacitor voltages, which results in a high computational burden. In [26], an improved FCS-MPC is proposed to reduce the computational burden by using the redundancies and separating the whole problem in two different FCS-MPC problems. However, the FCS-MPC strategies in [25] and [26] do not discuss the dc-link capacitor voltages or the switching principle, while resulting in unwanted switching transitions and a variable switching frequency. In [27], a fast FCS-MPC based on switching principle is proposed to reduce the computational cost and avoid the unwanted switching transitions. However, the fast FCS-MPC requires high sampling frequency and complex weighting factor design, and leads to variable switching frequency.

In order to solve the problem of a variable switching frequency and to reduce the ripples of the control variables in the conventional FCS-MPC, some improved predictive control strategies have been proposed in [28]-[33]. These strategies include PWM-based MPC [28], MPC with duty cycle optimization (DCO) [29]-[31] and DBC [14], [32], [33]. In [28], model predictive direct power control (MP-DPC) with modulation function optimization is proposed to achieve zero steady-state errors and a fast dynamic response. In [29], a dead-beat predictive direct power control (DB-DPC) strategy with an improved voltage-vector sequences is presented. This method eliminates the steady-state power errors. An improved two-vector-based model predictive torque control (MPTC) without a weighting factors is presented in [30] to reduce both torque and flux ripples. In [31], a predictive duty cycle control is proposed to achieve zero steady-state average error and a fast dynamic response. However, the online optimizing algorithm is complicated and has a high computational burden.

According to a predictive model, DBC calculates the required reference voltage vector in order to track the desired reference values of the control variables, which is an inverse-model-based solution. DBC has the advantages of zero steady-state error, a fast dynamic response and easy digital implementation [13]-[15], [32], [33]. However, DBC requires an external modulator and multi-objective control is not easy to implement. In [32], advanced deadbeat direct torque and flux control (A-DB-DTFC) is presented to improve steady-state and transient-state performances by adopting two improved deadbeat methods. In [33], DBC for permanent-magnet synchronous motor (PMSM) drives is proposed to reduce the current and torque ripples.

This paper focuses on the multi-objective optimal control problem (MOOCP) for five-level NNPP converters, including the output currents, floating-capacitor voltage balance, dc- link capacitor voltage balance, and system constraints. A deadbeat and hierarchical predictive control with space- vector modulation (DB-HPC-SVM) is presented to improve the steady-state and dynamic performances. When compared to FCS-MPC in [27], the proposed DB-HPC-SVM does not require high sampling frequency and complex weighting factor design, and achieves fixed switching frequency. According to a system predictive model, the deadbeat reference voltage vector (DB-RVV) is calculated by DBC, which achieves zero steady-state error and a fast dynamic response. According to the fast space-vector modulation (SVM) principle proposed in [9], three basic voltage vectors adjacent to DB-RVV are selected and the corresponding duty cycles are calculated. To solve the problem of a high computational burden, this paper presents a hierarchical MPC. In the first stage, MPC with simple logical judgment is proposed to balance the floating-capacitor voltages. In the second stage, MPC based on optimal switching sequence (OSS) is proposed to control the dc-link capacitor voltages. Comparative simulation and experimental results under dynamic and steady-state conditions are presented to validate the proposed DB-HPC-SVM.

Ⅱ. SWITCHING PRINCIPLE AND MATHEMATICAL MODEL

A. Five-Level NNPP Converter

A three-phase five-level NNPP converter is shown in Fig. 1. In this paper, x represents phases (a, b, and c). If V_dc = 4E, the reference voltages of the dc-link capacitors C₁ and C₂ are 2E, and the reference voltages of floating capacitors C_fx1 and C_fx2 are E. The switches S_x11 and S_x12, S_x15 and S_x16, S_x21 and S_x22, and S_x25 and S_x26 are two power semiconductor devices connected in series. The directions of the instantaneous currents i_o, i_xo, i_cfx1, i_cfx2 and i_x are shown in Fig. 1.

Fig. 1. Three-phase five-level NNPP converter.

The switch combination is defined as (S_x11 S_x21 S_x13 S_x23), where 1 and 0 represent the turn-on and turn-off statuses, respectively. Five output voltage levels for each phase are generated by nine distinct switch combinations V₁-V₉, which are listed in Table I. The output voltage level of each phase is described as the switch variable S_x. The output voltage levels -2E, -E, 0, E and 2E are represented by 0, 1, 2, 3 and 4 respectively. Moreover, Fig. 1 shows circuit diagrams for all of the work modes of a five-level NNPP converter, which are represented by the switch combinations V₁-V₉.

TABLE I SWITCH COMBINATIONS OF FIVE-LEVEL NNPP CONVERTER

Vn	Sx11	Sx21	Sx13	Sx23	vxo	icfx1	icfx1	ixo
V1	1	1	1	1	2E	0	0	0
V2	1	0	1	1	E	-ix	0	0
V3	0	1	1	1	E	ix	0	ix
V4	1	0	1	0	0	-ix	-ix	0
V5	0	0	1	1	0	0	0	ix
V6	0	1	0	1	0	ix	ix	0
V7	0	0	0	1	-E	0	ix	0
V8	0	0	1	0	-E	0	-ix	ix
V9	0	0	0	0	-2E	0	0	0

B. Switching Principle

In order to ensure safe operation, the output phase voltage of a multilevel converter should switch between adjacent output levels in a switching process. Moreover, the output phase voltage will be clamped to other unwanted voltage levels during the dead-time period if improper switching operation modes are applied [9], [27]. Therefore, the switching operation of a five-level NNPP converter should meet the switching principle [9], [27]:

1) S_x11 (S_x12) and S_x14, S_x15 (S_x16) and S_x13, S_x21 (S_x22) and S_x24, and S_x25 (S_x26) and S_x23 operate in the complementary mode in order to avoid a short-circuit between the dc-link capacitors and the floating capacitors.

2) S_x11, S_x12, S_x15 and S_x16 as well as S_x21, S_x22, S_x25 and S_x26 should not simultaneously turn on.

3) Switching operation is implemented between adjacent output levels to avoid a high voltage level jump.

4) Switch combinations should follow specific switching operation modes to avoid improper freewheeling circuits and unwanted voltage levels.

Fig. 2 shows the switching operation modes of a five-level NNPP converter. As can be seen in this figure, the specific switching operation modes represented by solid lines meet the above switching principle. In addition, the other switching operation modes represented by dashed lines may lead to high output voltage level jumps.

Fig. 2. Switching operation modes of a five-level NNPP converter.

C. Mathematical Model

According to the topology, the output phase voltage is:

     (1)

where V_c1, V_c2, V_cfx1 and V_cfx2 are the voltages of the capacitors C₁, C₂, C_cfx1 and C_cfx2, respectively.

To ensure that the power electronic switching devices work in the safe operating area (SOA), floating-capacitor voltages and dc-link capacitor voltages should be stabilized at their reference voltages [9]. If the capacitor voltages are balanced, v_xo can be simplified as:

         (2)

According to the topology, the instantaneous currents of floating capacitors can be represented by:

   (3)

   (4)

The total instantaneous current of the dc-link neutral point for three-phase is:

           (5)

The continuous-time models of the floating-capacitor voltages are:

     (6)

    (7)

The continuous-time models of the dc-link capacitor voltages are:

    (8)

The duty cycles of the switches S_x11, S_x21, S_x13 and S_x23 in a sampling period T_s are described as D_x11, D_x21, D_x13 and D_x23. The average currents of three-phase floating capacitors and dc-link neutral point at the k-th sampling instant are:

     (9)

    (10)

           (11)

In one-step prediction, the discrete-time models of the floating-capacitor voltages and dc-link capacitor voltages are:

         (12)

    (13)

For the sake of simplicity, a three-phase five-level NNPP converter feeds the RL load. According to Kirchhoff’s voltage law (KVL), continuous-time models of the load currents in the abc coordinate system can be represented by:

       (14)

where x = a, b, c, and v_no(t) is the common-mode voltage:

        (15)

In the dq coordinate system, the continuous-time models of load currents are:

   (16)

where v_d(t), v_q(t), i_d(t) and i_q(t) are the coordinates of output voltages and currents in the dq coordinate system, and ω is the angular frequency.

Fig. 3 shows a block diagram of a conventional PI+SVM based on the dq coordinate system. The fast SVM algorithm for a five-level NNPP converter proposed in [9] is used and the floating-capacitor voltage balance and the dc-link capacitor voltage balance methods are based on the PWM scheme. The floating-capacitor voltages are balanced by selecting appropriate switch combinations for each phase. The dc-link capacitor voltages are balanced by dynamically selecting a seven-segment switching sequence and introducing a regulatory factor [9].

Fig. 3. Block diagram of a conventional PI+SVM.

The output current derivative is substituted by a forward Euler approximation. In the abc coordinate system, the discrete-time models of the output currents are:

          (17)

where A = T_s/L, B = 1-RA and T_s is the sampling period.

In the αβ coordinate system, the discrete-time models of output currents are:

         (18)

where v_α(k), v_β(k), i_α(k) and i_β(k) are the coordinates of the output voltages and currents at the instant k in the αβ coordinate system.

Ⅲ. DB-HPC-SVM FOR A FIVE-LEVEL NNPP CONVERTER

In addition to output current control, five-level NNPP converters also suffer from dc-link capacitor voltage balance control and three-phase floating-capacitor voltage balance control problems. Therefore, the control system of a five-level NNPP converter is a multi-objective control system. It can be seen from Table I that nine distinct switch combinations V₁-V₉ generate the five output voltage levels for each phase. Therefore, the number of three-phase candidate switch combinations used in the enumeration process of conventional FCS-MPC is 9³, which greatly increases the computational burden.

This paper proposes DB-HPC-SVM for a five-level NNPP converter. When compared to the FCS-MPC strategies in [25]-[27], the proposed DB-HPC-SVM reduces the steady- state ripples of the control variables and achieves a fixed switching frequency. When compared to the conventional PI+SVM, the proposed DB-HPC-SVM has the advantages of a fast dynamic response and easy inclusion of constraints. In [9], in order to reduce the common-mode voltage, the number of redundant switching states is reduced to four or five in a small sector. Therefore, the number of seven-segment switching sequences used to balance the dc-link capacitor voltages are reduced to one or two, which may reduce the dynamic response of the capacitor voltages. Moreover, the capacitor voltage balance methods proposed in [9] are implemented based on the measured voltage and current values at the instant k, and the control actions are applied at the instant k+1, which results in a delay problem. In the proposed DB-HPC-SVM, all of the candidate five-segment switching sequences are enumerated by a cost function to balance the capacitor voltages. The number of five-segment switching sequences is always larger than that of the seven- segment switching sequences in [9], which may result in a fast voltage balance capability. Unlike [9], the proposed hierarchical MPC balances the capacitor voltages according to the predictive values of the capacitor voltage and current, which eliminates the delay effects and achieves a fast dynamic response for the capacitor voltages.

Fig. 4 shows a block diagram of the proposed DB-HPC- SVM. As shown in this figure, the proposed DB-HPC-SVM has three main steps.

Fig. 4. Block diagram of the proposed DB-HPC-SVM.

1) According to the system predictive model, calculate the DB-RVV by means of DBC to track the reference currents.

2) According to the fast SVM principle, determine the three adjacent basic voltage vectors that synthesize the DB-RVV and calculate the corresponding duty cycles.

3) Determine the finite control subset of the hierarchical MPC, which is composed of all of the candidate switching sequences in the optimal small sector. Then select the OSC and OSS by the hierarchical MPC to balance the capacitor voltages.

The stability of the predictive control in power converters is still an open topic of research [13, 21, 33]. In [13], the stability and robustness of deadbeat current controllers are enhanced by using delay compensation and an adaptive load model. In [33], it is demonstrated that model predictive direct current control guarantees stability and provides robustness under parameter uncertainties.

In the proposed DB-HPC-SVM, the DB-RVV is calculated based on the system predictive model to achieve zero steady- state error of the output currents. DB-RVV is the continuous variable and is always synthesized by the candidate switching sequences. Moreover, only switching sequences that synthesize the DB-RVV are considered in the hierarchical MPC. Then the OSC and OSS are selected from the candidate switching sequences to balance the capacitor voltages. Therefore, the proposed DB-HPC-SVM guarantees practical stability. In order to address the parameter sensitivity issue of the deadbeat controller, the novel adaptive self-tuning load model proposed in [13] and the repetitive-control-based observer proposed in [14] can be used.

A. DBC

In multilevel converters, the number of candidate voltage vectors increases exponentially with the number of output voltage levels. The conventional FCS-MPC enumerates all candidates to minimize the cost function at every sampling interval, which leads to high computational burden. This paper uses DBC to calculate the DB-RVV directly instead of selecting the optimal voltage vector (OVV) in the voltage vector selection process. This avoids enumerating all of the candidate voltage vectors in the FCS-MPC.

In general, the control strategies require massive calculations, which introduces the time delay during execution. According to the Lagrange extrapolation formula, the future reference values of the output currents at the instant k+2 can be estimated as:

         (19)

where , , and are the reference values of the currents at the instants k+2, k, k-1 and k-2, respectively.

The discrete-time models of the output currents at the instant k+2 in the αβ coordinate system can be predicted:

    (20)

In theory, as long as the required reference voltage vector is within the converter output capacity, zero steady-state error of the output current can be achieved at the instant k+2. By making the output currents at the instant k+2 equal to the desired reference values, the required reference voltage vector applied at the instant k+1 is described as the deadbeat reference voltage vector V_DB(k+1) and is calculated from (18)-(20).

        (21)

where v_{α_DB}(k+1) and v_{β_DB}(k+1) are the coordinates of V_DB(k+1) at the instant k+1 in the αβ coordinate system, and are the future reference values of the output currents at the instant k+2 in the αβ coordinate system.

The maximal output voltage capacity of a power electric converter is generally restricted by the dc-link voltage. In this paper, DB-RVV is generated by using the fast SVM principle. Therefore, the output voltage of the converter should follow:

          (22)

B. Fast SVM Principle

In this paper, all of the candidate switching sequences that synthesize DB-RVV are obtained by using the fast SVM principle based on the gh coordinate system proposed in [9]. This SVM principle is easily implemented by addition and subtraction calculations without the need for a complex sector judgment or a large number of trigonometric calculations.

Fig. 5 shows the first big sector of a five-level space vector diagram. The small sector which contains DB-RVV is described as the deadbeat optimal small sector. The duty cycles of the three adjacent basic voltage vectors in the deadbeat optimal small sector are calculated as D₁, D₂ and D₃. All of the redundant switching states in the deadbeat optimal small sector can be obtained by using the fast SVM principle. Thus, all of the candidate switching sequences for the hierarchical MPC are derived.

Fig. 5. First big sector of a five-level space vector diagram.

As shown in Fig. 5, there are seven redundant switching states in the deadbeat optimal small sector for V_DB(k+1). In order to reduce the switching losses, the five-segment switching sequence is adopted in this paper. There are five candidate switching sequences in the deadbeat optimal small sector for V_DB(k+1), as listed in Table II.

TABLE II FIVE-SEGMENT CANDIDATE SWITCHING SEQUENCES

Switching sequences	N	io(k+1) in one case
210-310-320-310-210	4*4*1	-ic(k+1)*(D3+D1+D2)
310-320-321-320-310	1*4*2	-ic(k+1)*(D1+D2)
320-321-421-321-320	2*1*2	-ic(k+1)*D2-ia(k+1)*D1
321-421-431-421-321	2*4*1	-ia(k+1)*(D1+D2)
421-431-432-431-421	1*4*4	-ia(k+1)*(D1+D2+D3)

Moreover, due to the redundancy of the switch combinations for each phase, each switching sequence has several different three-phase switching operation modes to generate three-phase control signals. According to the switching operation modes in Fig. 2, the number of three-phase switching operation modes for each switching sequence can be obtained, which is described as N. Taking V_DB(k+1) as an example, the number N for each switching sequence is listed in Table II. According to the duty cycles of each voltage vector in the switching sequence and the specific switching operation mode for each phase, the corresponding duty cycles of each switch can be calculated.

C. Hierarchical MPC

In order to reduce the computational burden, this paper presents the hierarchical MPC, which is divided into two stages: MPC with a simple logical judgment and MPC based on OSS. In the first stage, according to the redundancy of the switch combination, the floating-capacitor voltages are balanced by selecting the OSC for each phase. In the second stage, according to the redundancy of the switching sequence, the control objectives of the dc-link capacitor voltages and the switching constraints are evaluated in a cost function to obtain OSS. Therefore, the computational burden is significantly reduced without sacrificing the fast dynamic response.

The average currents of floating capacitors and dc-link neutral point at the instant k+1 are calculated as:

    (23)

   (24)

          (25)

Discrete-time models of the floating-capacitor voltages and dc-link capacitor voltages at the instant k+2 are represented by:

    (26)

         (27)

Moreover, extra switching control between two adjacent switching sequences is added to the cost function to reduce the switching transitions. The number of the switches that change between two adjacent sampling periods is calculated by using the last three-phase switch combinations at the instant k and the first three-phase switch combinations at the instant k+1. The number of extra switching transitions between two adjacent switching sequences is:

   (28)

In the FCS-MPC strategies in [25]-[27], the control objectives of the output currents, dc-link capacitor voltages and three-phase floating-capacitor voltages and system constraints are included in a cost function to achieve multi- objective control. All of the three-phase candidate switch combinations are evaluated by the cost function in [25]. The cost function for the conventional FCS-MPC is:

           (29)

where W_dc, W_cf and W_fs are the weighting factors, V_cref = V_dc/4.

However, the complexity of the weighting factor design for different control variables is significantly increased. In general, the different natures of the control variables hinder the design of the weighting factors [21]. Moreover, the conventional FCS-MPC requires an exhaustive exploration of all the possible states by using (29), which significantly increases the computational burden. In [27], the number of candidate switch combinations is reduced from 9³ to 4³ by using switching principle.

In this paper, the output currents are controlled by DBC, and all of the candidate switching sequences are obtained by using the fast SVM principle. The control variables in this stage are reduced to capacitor voltages and system constraints. Moreover, the finite control subset of MPC is a component of the candidate switching sequences. All of the candidate switching sequences can be evaluated by the cost function as follows:

   (30)

According to the switching operation modes in Fig. 2, the maximum number of reasonable switching operation modes between adjacent output voltage levels is 4. In a five-segment switching sequence, there are two phases to change the output voltage level and there is a phase to maintain the output voltage level. Therefore, the maximum number of three-phase switching operation modes for each switching sequence is 4², which increases the computational burden.

In order to address the problems of a high computational burden and a complex weighting factor design in the conventional FCS-MPC with a cost function (30), a hierarchical MPC is proposed to control the floating-capacitor voltages and the dc-link capacitor voltages by using different MPC methods.

As listed in Table I, a five-level NNPP converter has the redundant switch combinations to generate the same output voltage level. In order to simplify the switching operation, V₅ is chosen to generate the output level of 0 in this paper. The switch combinations V₂ and V₃ have opposite effects on the voltage of the floating capacitor C_fx1, and the switch combinations V₇ and V₈ have the opposite effects on the voltage of the floating capacitor C_fx2.

Since the floating-capacitor voltages for each phase are only related to the switch combinations corresponding to the single-phase output voltage level, the floating-capacitor voltages for each phase can be independently balanced. Moreover, because the number of redundant switch combinations used in this paper is only two, the cost function can be replaced by a simple logical judgment method. Unlike the method in [9], in order to compensate the digital implementation delay, the OSC applied at the instant k+1 for each phase is selected by a simple logical judgment based on predictive values at the instant k+1. Therefore, in the first stage, MPC with a simple logical judgment for each phase is adopted in this paper, which avoids the three-phase unified control and reduces the computational burden.

According to the predictive values of the floating-capacitor voltages and the output currents at the instant k+1, the OSC for each phase is determined by a simple logical judgment as follow. If [V_cfx1(k+1)-V_cref]i_x(k+1) > 0, V₃ is chosen to generate the output level E. When the opposite is true, V₂ is chosen. If [V_cfx2(k+1)-V_cref]i_x(k+1) > 0, V₇ is chosen to generate the output level -E. When the opposite is true, V₈ is chosen.

After the OSC for each phase is selected by the simple logical judgment, each switching sequence has only one three-phase switching operation mode to generate the three- phase control signals. As a result, the maximum number of three-phase switching operation modes for each switching sequence is reduced from 4² to 1. The corresponding duty cycles of each switch at the instant k+1 can be calculated. According to (25) and (27), the dc-link capacitor voltages at the instant k+2 can be predicted.

Since there are several redundant switching states for a multilevel converter to generate the same basic voltage vector, different five-segment switching sequences can be obtained to synthesize the same DB-RVV in the deadbeat optimal small sector.

As listed in Table II, five candidate switch sequences in the deadbeat optimal small sector can be applied to synthesize V_DB(k+1) at the instant k+1. If V₈ is selected to generate the voltage level -E and V₃ is selected to generate the voltage level E for three phases by using the MPC with a simple logical judgment, the neutral-point current i_o(k+1) for each candidate switch sequence in this case is listed in Table II.

According to the redundancy of the switching sequence, the dc-link capacitor voltages are balanced by using the MPC based on the OSS. All of the five-segment candidate switching sequences are evaluated by the cost function and the switching sequence minimizing the cost function is selected as the OSS.

Moreover, in order to reduce the switching losses, an extra switching control between two adjacent switching sequences is added to the cost function. The cost function for the MPC in the second stage is:

    (31)

When compared with the conventional FCS-MPC with a cost function (30), the hierarchical MPC reduces the computational burden and avoids a complex weighting factor design.

Ⅳ. SIMULATION RESULTS

To evaluate the proposed DB-HPC-SVM, a three-phase five-level NNPP converter simulation model is constructed using MATLAB software. Comparative simulation results between the conventional PI+SVM, the conventional FCS- MPC with a cost function (29) and the proposed DB-HPC- SVM are presented. The main parameters of the simulation model are listed in Table III. The output reference currents in the dq coordinate system are i_dref = 35.35 A and i_qref = 91.91 A. Then they are changed to i_dref = 35.35 A and i_qref = 183.82 A at 0.15 s.

TABLE III MAIN PARAMETERS OF THE SIMULATION MODEL

Parameter	Value
dc-link voltage	5000V
Dc-link capacitors	4700μF
Floating capacitors	2200μF
Switching frequency	2kHz
Fundamental frequency	50Hz
RL load	10 Ω, 30mH

To ensure fairness, the sampling frequency f_s for the conventional FCS-MPC is chosen as 10 kHz. By using the branch and bound techniques, the weighting factors in the conventional FCS-MPC are as follows: W_cf = 0.3, W_dc = 0.4, and W_fs = 1.8. The switching frequency band is mainly distributed between 1 kHz and 3 kHz. The PI controller parameters are as follows: K_p = 2.0, K_i = 150 and f_s = 2 kHz. In the proposed DB-HPC-SVM, the control parameters are as follows: W_fs = 0.5 and f_s = 2 kHz.

Fig. 6 shows comparative simulation results of the line voltage and three-phase output currents between three different control strategies under dynamic conditions. As shown in Fig. 6(a)-(c), the output current THDs for the three different control strategies when i_dref = 35.35 A and i_qref = 183.82 A are 0.33%, 0.67% and 0.35%. It can be clearly observed from Fig. 6 that the dynamic response times for three different control strategies are 8 ms, 2 ms and 3 ms.

Fig. 6. Simulation results for different control strategies under dynamic conditions: (a) Conventional PI+SVM; (b) Conventional FCS-MPC; (c) Proposed DB-HPC-SVM.

(a)

(b)

(c)

As can be observed from Fig. 6(a) and (c), the proposed DB-HPC-SVM obtains similar steady-state current ripples when compared to the conventional PI+SVM, while achieving a fast dynamic response. As can be observed from Fig. 6(b) and (c), the proposed DB-HPC-SVM reduces the steady-state current ripples and current THD when compared to the conventional FCS-MPC, while achieving a fast dynamic response. Nevertheless, the dynamic response time for the proposed DB-HPC-SVM is a little larger than that for the conventional FCS-MPC. This can be explained by the higher sample frequency of the FCS-MPC. Comparative simulation results show that the proposed DB-HPC-SVM combines the advantages of DBC, SVM, and MPC to improve both the steady-state and dynamic performances.

Moreover, as shown in Fig. 6(b), the output voltage for the conventional FCS-MPC shows a high output voltage level jump and unwanted switching transitions, especially under dynamic conditions. It can be seen from Fig. 6(a) and (c) that the proposed DB-HPC-SVM and the conventional PI+SVM avoid high output voltage level jumps and unwanted switching transitions.

To evaluate the steady-state performance of the three control strategies, the output current quality is evaluated in term of the THD. Fig. 7 shows plots of the current THD versus i_qref for the three control strategies when i_dref = 35.35 A. It can be seen from Fig. 7 that the proposed DB-HPC-SVM provides a lower current THD when compared to the conventional FCS-MPC. This can be explained by the fact that the DBC achieves zero steady-state error of the output currents. Moreover, the proposed DB-HPC-SVM and the conventional PI+SVM present similar current THDs in most of the i_qref range. Therefore, the proposed DB-HPC-SVM maintains similar steady-state performance of the output current with the PI+SVM. Simulation results show that the proposed DB-HPC-SVM maintains the advantages of zero steady-state error and a fast dynamic response.

Fig. 7. Plots of current THD versus i_qref for three control strategies.C

In order to verify the steady-state tracking performance of the three different control strategies, Fig. 8 shows comparisons of the tracking error of i_b between the three different control strategies when i_dref = 35.35 A and i_qref = 183.82 A. As can be seen from Fig. 8(a)-(c), the steady-state tracking error of i_b for the conventional FCS-MPC is the largest, and the proposed DB-HPC-SVM and the conventional PI+SVM provide similar steady-state tracking performance.

Fig. 8. Tracking error of i_b for different control strategies: (a) Conventional PI+SVM; (b) Conventional FCS-MPC; (c) Proposed DB-HPC-SVM.

(a)

(b)

(c)

To verify the improved harmonic spectrum of the proposed DB-HPC-SVM, Fig. 9 shows a FFT analysis of the line voltage for the three different control strategies when i_dref = 35.35 A and i_qref = 183.82 A. It can be seen from Fig. 9(a) that the harmonic spectrum for the conventional PI+SVM is mainly concentrated around the switching frequency f_s and its multiples. As shown in Fig. 9(b), the conventional FCS-MPC results in a variable switching frequency and a spread spectrum. Moreover, the line voltage contains some low-order harmonics that are not easily eliminated by an output filter. As shown in Fig. 9(c), the proposed DB-HPC-SVM improves the generated waveforms harmonic spectrum with a fixed switching frequency.

Fig. 9. FFT analysis of the line voltage for different control strategies: (a) Conventional PI+SVM; (b) Conventional FCS- MPC; (c) Proposed DB-HPC-SVM.

(a)

(b)

(c)

One of the main contributions of the proposed DB-HPC- SVM is its ability to achieve a fixed switching frequency. As shown in Fig. 9, although the proposed DB-HPC-SVM provides a higher voltage THD than the conventional FCS- MPC, the proposed DB-HPC-SVM improves the harmonic spectrum with a fixed switching frequency and eliminates low-order harmonics. The increment of the THD is mainly caused by the harmonics around the switching frequency, which are easy to filter. Moreover, the line voltage THD for the proposed DB-HPC-SVM is higher than that for the conventional PI+SVM. This can be explained by the fact that all of the five-segment switching sequences are dynamically selected by the MPC and require fewer switching transitions in a switching period. However, the seven-segment switching sequence used in [9] is generally predefined and requires higher switching transitions in a switching period.

Fig. 10 shows comparative simulation results of the capacitor voltages for different control strategies. As shown in Fig. 10, all three control strategies can balance the three-phase floating-capacitor voltages and dc-link capacitor voltages under steady-state and dynamic conditions.

Fig. 10. Simulation results of capacitor voltages for different control strategies: (a) Conventional PI+SVM; (b) Conventional FCS-MPC; (c) Proposed DB-HPC-SVM.

(a)

(b)

(c)

As can be seen from Fig. 10(a), the fluctuation amplitude of the floating-capacitor voltages for the conventional PI+SVM is maximal and the dc-link capacitor voltage ripples are average. As shown in Fig. 10(b), by using the conventional FCS-MPC, the fluctuation amplitude of the floating-capacitor voltages is average and the dc-link capacitor voltage ripples are maximal. As shown in Fig. 10(c), the fluctuation amplitudes of the floating-capacitor voltages and the dc-link capacitor voltages are minimal using the proposed DB-HPC-SVM. Comparative simulation results show that the proposed DB-HPC-SVM reduces the capacitor voltage ripples. On the one hand, the predictive values of the floating-capacitor voltages and output currents at the instant k+1 are used in the MPC with a simple logical judgment to balance the floating-capacitor voltages. On the other hand, the dc-link capacitor voltages at the instant k+2 are predicted in the MPC based on OSS to compensate the control delay. Moreover, the proposed DB-HPC-SVM avoids the complex weighting factor design and the interaction effect between different control variables.

Ⅴ. EXPERIMENTAL RESULTS

An experimental setup of a five-level NNPP converter shown in Fig. 11 has been constructed to verify the proposed DB-HPC-SVM. The proposed DB-HPC-SVM has been implemented by the control system which contains a DSP (TI TMS320F28335) and a FPGA (ACTEL A3P250). Table IV shows the main experimental parameters. In order to keep the capacitor voltage fluctuations within an allowable range, the capacitance of the floating capacitors and dc-link capacitors required in a low voltage system is greater than that in simulation. In a low-voltage experimental setup, the parameters of the RL load are designed to generate one-tenth the output currents of the simulation with a similar modulation index.

Fig. 11. Experimental setup of a five-level NNPP converter.

TABLE IV Main Parameters for the Experimental Setup

Parameter	Value
dc-link voltage	200V
Dc-link capacitors	6800μF
Floating capacitors	3400μF
Switching frequency	2kHz
Fundamental frequency	50Hz
RL load	5 Ω, 15mH

Since the conventional FCS-MPC has a high computational burden and is not easy to implement, experimental results of the conventional FCS-MPC are not presented. Comparative experimental results between the conventional PI+SVM and the proposed DB-SVM-MPC are presented. The PI controller parameters are as follows: K_p = 1.2, K_i = 70 and f_s = 2 kHz. In the proposed DB-SVM-MPC, the control parameters are as follows: W_fs = 0.5 and f_s = 2 kHz. The output reference currents in the dq coordinate system are as follow: i_dref = 3.535 A, and i_qref changes from 9.191 A to 18.382 A under dynamic conditions.

A. Steady-state Performance

Fig. 12 shows a comparisons of the phase voltage, line voltage, dc-link voltage and output current between the conventional PI+SVM and the proposed DB-HPC-SVM under steady-state conditions, when i_dref = 3.535 A and i_qref = 18.382 A. As shown in Fig. 12, the line voltages and output currents for both control strategies have similar steady-state performances. The proposed DB-HPC-SVM achieves zero steady-state error of the output currents, which is consistent with the simulation results. Moreover, the results of the phase voltage for the proposed DB-HPC-SVM show that the output voltage level does not change during several switching periods, which reduces the switching losses. On the one hand, two phases change the output voltage level, while one phase maintains the same output voltage level in every five-segment switching sequence. On the other hand, the extra switching control in the MPC based on OSS reduces the switching transitions between two adjacent switching sequences. However, the results of the phase voltage for the PI+SVM show that the number of switching transitions for the seven-segment switching sequence used in [9] is larger than that of the proposed DB-HPC-SVM. Therefore, the proposed DB-HPC-SVM also combines the characteristic of easy inclusion of constraints, such as extra switching control.

Fig. 12. Experimental results for different control strategies under steady-state conditions: (a) Conventional PI+SVM; (b) Proposed DB-HPC-SVM.

(a)

(b)

Moreover, as shown in Fig. 12, an FFT analysis of the line voltages for both control strategies is also presented. It can be seen from Fig. 12(a) that the harmonic spectrum for the conventional PI+SVM is mainly concentrated around the switching frequency f_s. As shown in Fig. 12(b), the proposed DB-HPC-SVM also combines the advantage of a fixed switching frequency and eliminates low-order harmonics, which is one of the main contributions of the proposed DB-HPC-SVM.

B. Dynamic Performance

Fig. 13 shows comparative experimental results of the line voltage and three-phase output currents between the conventional PI+SVM and the proposed DB-HPC-SVM under dynamic conditions. It is clearly observed from Fig. 13 that the dynamic response times of the output currents for the conventional PI+SVM and the proposed DB-HPC-SVM are 8 ms and 3 ms, respectively. These results are consistent with the simulation results. Moreover, the proposed DB-HPC- SVM presents a fast dynamic response without current overshoot, while the current overshoot of the conventional PI+SVM is about 10%. As can be observed from Fig. 13(a) and (b), the proposed DB-HPC-SVM achieves a fast dynamic response when compared to the conventional PI+SVM, while obtaining similar steady-state current ripples.

Fig. 13. Experimental results for different control strategies under dynamic condition: (a) Conventional PI+SVM; (b) Proposed DB-HPC-SVM.

(a)

(b)

Moreover, as shown in Fig. 13, both the conventional PI+SVM and the proposed DB-HPC-SVM avoid high output voltage level jumps and unwanted switching transitions under steady-state and dynamic conditions.

Fig. 14 shows comparative experimental results of the capacitor voltages between the conventional PI+SVM and the proposed DB-HPC-SVM under dynamic condition. As shown in Fig. 14, both control strategies can balance the three-phase floating-capacitor voltages and dc-link capacitor voltages under steady-state and dynamic conditions.

As can be seen from Fig. 14, the dynamic response times of the capacitor voltages for the conventional PI+SVM and the proposed DB-HPC-SVM are 80 ms and 40 ms, respectively. Therefore, the floating-capacitor voltages and the dc-link capacitor voltages for the proposed DB-HPC-SVM have faster dynamic responses when compared to the capacitor voltages for the conventional PI+SVM. Moreover, the fluctuation amplitude of the floating-capacitor voltages for the conventional PI+SVM is larger than that for the proposed DB-HPC-SVM, while the dc-link capacitor voltages for both of the control strategies present similar steady-state ripples. When compared with the capacitor voltage balance methods in [9], the proposed DB-HPC-SVM balances the capacitor voltages by using the predictive values of the capacitor voltage and current, which compensates the control delay.

Fig. 14. Experimental results of capacitor voltages for different control strategies under dynamic conditions: (a) Conventional PI+SVM; (b) Proposed DB-HPC-SVM.

(a)

(b)

The comparative experimental results above show that the proposed DB-HPC-SVM combines the advantages of DBC, fast SVM and MPC to improve both the steady-state and dynamic performance.

Ⅵ. CONCLUSIONS

In this paper, DB-HPC-SVM is presented to achieve a fast dynamic response, balance capacitor voltages, and reduce steady-state current ripples. Unlike the exhaustive exploration in FCS-MPC, the voltage vector selection process is simplified by using DBC to obtain DB-RVV, which achieves zero steady-state current error and a fast dynamic response. The fast SVM principle is used to obtain all of the candidate switching sequences that synthesize the DB-RVV. In order to reduce the computational burden and the complexity of the weighting factor design, a hierarchical MPC is proposed to balance the capacitor voltages. The OSC for each phase is selected by the MPC with a simple logical judgment and the OSS is selected by minimizing the cost function of the MPC. The proposed DB-HPC-SVM combines the advantages of DBC, fast SVM and MPC. When compared with the conventional PI+SVM, the proposed DB-HPC-SVM has a fast dynamic response. When compared with the conventional FCS-MPC, the proposed DB-HPC-SVM improves steady-state performances, such as a fixed switching frequency and a lower steady-state ripple. Comparative results verify the feasibility and validity of the proposed DB-HPC-SVM under different conditions.

ACKNOWLEDGMENT

The authors appreciate the financial supports provided by the National High Technology Research and Development Program of China (863 Program), Grant No. 2014AA052602 and National Key Basic Research Program of China (973 Program) Grant No. 2014CB046306.

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Junjie Li was born in Pingyao, China, in 1989. He received his B.S. and M.S. degrees in Electrical Engineering from the China University of Mining and Technology, Xuzhou, China, in 2011 and 2013, respectively. He is presently working towards his Ph.D. degree in Power Electronics and Power Drives at the Key Laboratory of Control of Power Transmission and Conversion, Shanghai Jiao Tong University, Shanghai, China. His current research interests include multilevel converters, STATCOMs, and motor drives.

Xiangyu Chang was born in Jiangsu, China, in 1990. She received her B.S. and M.S. degrees from the East China Normal University, Shanghai, China, in 2012 and 2015, respectively. She is presently working towards her Ph.D. degree in Linguistics at Shanghai International Studies University, Shanghai, China. Her current research interests include linguistics, russian and english.

Dirui Yang was born in Nanchang, China, in 1987. He received his B.S. degree in Electrical Engineering from Fudan University, Shanghai, China, in 2010; and his M.S. degree in Electrical Engineering from the University of Shanghai for Science and Technology, Shanghai, China, in 2016. He is presently working towards his Ph.D. degree in Power Electronics and Power Drives at the Key Laboratory of Control of Power Transmission and Conversion, Shanghai Jiao Tong University, Shanghai, China. His current research interests include multilevel converters and STATCOMs.

Yunlong Liu was born in Jiangsu, China, in 1989. He received his M.S. degree in Power Electronics and Power Drives from the School of Electrical and Information Engineering, Jiangsu University, Zhenjiang, China, in 2015. He is presently working towards his Ph.D. degree in School of Mechanical Electronic and Information Engineering, China University of Mining and Technology, Beijing, China. His curren research interests include reactive power compensation and multi-level converters.

Jianguo Jiang was born in Jiangsu, China, in 1956. He received his Ph.D. degree in Electrical Engineering from the China University of Mining and Technology, Xuzhou, China, in 1988. He is presently working as a Professor of Electrical Engineering at Shanghai Jiao Tong University, Shanghai, China. His current research interests include high power motor drives and control.