사각형입니다.

https://doi.org/10.6113/JPE.2018.18.6.1866

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Compensation of Neutral Point Deviation under Generalized 3-Phase Imbalance in 3-level NPC Converters


Kyungsub Jung* and Yongsug Suh


†,*Department of Electronic Engineering, Chonbuk National University, Jeonju, Korea



Abstract

This paper presents a neutral point deviation and ripple compensation control method for application to 3-level NPC converters. The neutral point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral point of the dc-link. This paper also proposes a control scheme to compensate for the neutral point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the pole voltages and ac input currents are employed to accurately explain the behavior of 3-level NPC converters. Simulation and experimental results are presented to verify the validity of the proposed method.


Key words: 3-level NPC converter, Dual-frame current regulator, Imbalance factor, Neutral point current, Neutral point deviation, Single-frame current regulator, Unbalanced grid input


Manuscript received Mar. 22, 2018; accepted Aug. 16, 2018

Recommended for publication by Associate Editor Kyo-Beum Lee.

Corresponding Author: ysuh@jbnu.ac.kr Tel: +82-63-270-3381, Chonbuk National University

*Dept. of Electronic Eng., Chonbuk National University, Korea



Ⅰ. INTRODUCTION

Multilevel converters are widely used in high-power applications such as motor drives, utility applications and wind generation systems. Extensive research has been carried out/on multilevel topologies, modulation and control strategies [1]. Multilevel converters can provide more than two voltage levels at the output. Therefore, relatively high voltages can be handled on both the dc and ac sides of a converter in a more efficient way. As a result, the input/output voltage and current waveforms tend to have a lower Total Harmonic Distortion (THD) [2]. The multilevel converter topology that is the most extensively applied at present is the 3-level Neutral-Point-Clamped (NPC) Voltage Source Converter (VSC) shown in Fig. 1. In a 3-level NPC VSC, maintaining balanced dc link voltages (having the same upper and lower half dc-link voltages) is an important issue. If the neutral point potential is not controlled properly, the output voltage of the converter deviates from the reference value, which might damage devices and equipment [3]. In the practical operation of a 3-level NPC VSC, the neutral point potential variation often causes a fault-trip of the converter due to the over-voltage of either the upper dc-link capacitor or the lower dc-link capacitor.


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Fig. 1. PMSG wind turbine with a back-to-back 3-Level NPC VSC.


The control strategies of neutral point potential that have appeared in the literature can be grouped according to the Pulse Width Modulation (PWM) method utilized. In the control strategies using Space Vector Modulation (SVM), the voltage vectors can be divided into four categories, depending on the amplitude of the reference vector such as the zero, small, middle and large vectors. The relationship between the neutral point potential and each of the switching state vectors can be used. While the zero and large vectors do not affect the neutral point potential, the middle and small vectors are known to influence it. Notice that there are two different switching states (positive or negative) with reverse directions (either charged or discharged) for the neutral point potential corresponding to one particular small vector. Therefore, the main task is to adjust the dwell time between the redundant switching states of the small vectors [4]-[9]. In many solutions using the SVM strategy for 3-level NPC converters, one or two switching sequences are strictly assigned to a particular subsector [10], [11]. DC-link voltage balancing control strategies are based on a change in the switching sequence under an imbalance dc-link voltage [12]- [17]. If carrier-based PWM (CBPWM) is used, the control of the neutral point potential can be considered an issue to identify zero sequence voltages. The voltage of the zero sequence added to the reference voltage does not change the output line voltage. However, it does affect the switching state and the neutral point potential. Neutral point voltage fluctuations due to injected zero sequence voltage have been studied, and several methods injected an appropriate zero sequence voltage to maintain the neutral point voltage balance [18]-[24].

Among the many possible causes of the neutral point deviation and ripple in 3-level NPC converters, an unbalanced grid supply can generate significant amounts of neutral point deviation and ripple. The impact of an unbalanced grid input on the neutral point deviation and ripple together with suitable compensating control strategies have been given less attention considering their importance in practical operations. In addition, previous works have not deeply analyzed the relationship between an unbalanced grid input and neutral point deviation under a wide range of unbalanced conditions. This paper investigates the characteristics of neutral point deviation and its ripple in terms of the sequential components of the grid voltage and input current. The positive and negative sequence components of the converter pole voltages and ac input currents are employed to derive a model of neutral point current. Based on this model, this paper proposes a unique control strategy to minimize the ripple of neutral point deviation particularly under various unbalanced operating conditions by nullifying the negative sequential component of the ac input current, i.e. achieving a balanced ac input current. The control strategy is implemented as a positive and negative sequential dq component current regulator in both the positive-rotating and negative-rotating synchronous reference frames.

This paper is structured as follows. First, a basic model describing the relationship between the neutral point deviation and the neutral point current in a 3-level NPC VSC is introduced in Section II. Based on this model, the behavior of the neutral point deviation and its voltage ripple under unbalanced operating conditions is investigated in Section III. In Section IV, a proper control method to reduce this voltage ripple is presented. Section V provides simulation verification results for a 5MW PMSG wind turbine model. Finally, experimental results obtained with a laboratory prototype of 15kW is presented in Section VI.



Ⅱ. RELATIONSHIP BETWEEN NEUTRAL POINT DEVIATION AND NEUTRAL POINT CURRENT

Fig. 2 illustrates a simplified 3-level NPC VSC using Single-Pole Triple-Throw (SPTT) switches in the grid-side converter of a wind generation system. The operation of the simplified 3-level NPC VSC using SPTT switches can be better described by employing the corresponding switching functions (Sx) defined in (1). In general, the converter output voltages (vx) with respect to the mid-point of the dc-link, i.e. the neutral point, can be represented by switching functions as (2).

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Fig. 2. 3-level NPC voltage source converter with a simplified topology using SPTT switches.


The neutral point current (inp) can be correlated with the phase currents (ix) and the switching functions as shown in (3). Therefore, by applying (2) into (3), the neutral point current can be explained by the converter output voltages and phase currents as in (4).

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In general, the 3-level NPC converter output voltage can be approximated by a PWM waveform with voltage levels of Vdc/2, 0 and -Vdc/2. The converter output voltages of the PWM waveforms can be effectively resolved into three components in a frequency spectrum: the fundamental frequency component (vx_fund), the harmonic frequency components (vx_harmonics), and the zero sequence component of the non-fundamental frequency (vcomp). These three components are described in (5). The zero sequence component of the non-fundamental frequency component is the added to compensate for the deviation of the neutral point voltage in the control systems [16]-[20].

In this paper, the harmonic frequency components are ignored in the neutral point current model as shown in (6), i.e. in the localized average model. Only the fundamental frequency component of the pole voltage and the AC input current are considered in the localized average model described in this paper. Simulations and experiment tests have focused on the fundamental frequency component of the neutral point current. These assumptions do not lead to significant errors in controlling the neutral point deviation because the high-order harmonics are effectively attenuated. In addition, in most cases, they does not contribute to a neutral point deviation or voltage ripple.

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In Fig. 2, it is readily understood that as long as the neutral point current (inp) is kept zero, the voltages of the upper and lower dc-link capacitors become equal to each other, i.e. zero neutral point deviation. This is because the upper and lower capacitors are charged or discharged at the same current level. However, even if the SPTT switches have this switching vector connected to a neutral point, the localized average model of the neutral point current can still be controlled as zero. This is made possible by the fact that the higher harmonics component of the neutral point current has been continuously ignored in the proposed model as described in (6). Consequently, a localized average model with a zero neutral point current is required to maintain the voltage balance at the upper and lower dc-link capacitors.

It should also be noted that this zero neutral point current value is not sufficient to achieve dc-link voltage balance. In other words, even when the neutral point current is zero, it is likely that the upper and lower dc-link voltages that do not match the upper and lower dc-link voltages are same as the initial charge conditions of the capacitor. In this paper, these effects were not considered in the modelling of the neutral point deviation in order to simplify the problems of dc-link imbalance, and to focus more on the effects of the AC grid imbalance on the neutral point and ripple voltages in dc-link capacitors. In this paper, the final goal of the investigation is to minimize the deviation of the neutral point voltage. However, an analysis and validation have been performed with respect to the variable of the neutral point current. This is because the variable of the neutral point current, instead of the neutral point voltage, is better characterized by the sequential components of the ac input current.



Ⅲ. ANALYSIS OF NEUTRAL POINT DEVIATION UNDER UNBALANCED THREE-PHASE GRID CONDITIONS

Under unbalanced ac grid conditions, the three-phase input currents flowing through the input filter stage of the grid-side converter become unbalanced unless proper compensating control measures are employed. This means that the ac input currents start to contain the negative sequence component under an unbalanced grid input. This negative sequence component of the ac input current further deteriorates the neutral point deviation and ripple of a 3-level NPC converter on top of the typical causes of dc-link imbalance such as the mismatch of the upper and lower dc-link capacitance, switching dead time, asymmetric modulation effects, etc. Therefore, in order to correctly explain the behavior of neutral point deviation and neutral point current under an ac grid imbalance, the negative sequence components of the ac input current as well as the negative sequence components of the converter output voltage at the pole of the converter should be incorporated into the description of the neutral point current in (4). Equation (4) is only valid for balanced dc-links; same upper and lower dc-link voltage. However, this model can still be applied to investigate ripples, i.e. the harmonic terms of the neutral point current under an unbalanced ac grid, which is the target variable of this paper. The symmetric components of the ac input current and converter output voltage are defined as shown in (7). In (7) the subscript p, n and o represent the positive, negative and zero sequence components, respectively. Applying (7) into the description of the neutral point current in (4) leads to (8). The signum function is employed to further simplify (8). In (8), it is intended to analyze the neutral point current under unbalanced operating conditions. The direct influence of the negative sequence components of both the ac input current and the converter output voltage upon the neutral point current needs to be investigated.

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In this paper, the influence of the grid imbalance upon the neutral point current is analyzed by employing the positive and negative sequential components of both the converter output pole voltages and the ac input currents. The sequential components of the converter output pole voltages and ac input currents are defined as shown in (9) and (10). It is more intuitive to derive the target model on the basis of the sequential components defined in (9) and (10) when compared to the positive and negative sequential component in the positive-rotating and negative-rotating synchronous reference frames, respectively.

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After integrating (9) and (10) into (8), the description of the neutral point current becomes (11).

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The coefficients employed for a simpler expression of (11) are defined in (12), (13) and (14).

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Therefore, further development of (11) requires information on the sign of each converter output voltage. In general, there can be eight different combinations of sign values for converter output voltages. These eight cases are described in Table I.


TABLE I IGN VALUES OF THE CONVERTER OUTPUT VOLTAGE

Case

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1

+

+

+

2

+

+

-

3

+

-

+

4

-

+

+

5

+

-

-

6

-

+

+

7

-

-

+

8

-

-

-


It can be readily understood that these sign combinations are closely related to the variable power factor operation of the grid-side converter. The description of the neutral point current in (11) can be further simplified as shown in (15).

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The numerical description of the neutral point current in (15) changes depending on the sign combination of the converter pole voltages during one complete line period. This means the coefficient values of X, Y and Z in (15) depend on the sign combination of the converter pole voltages. The coefficient values of X, Y and Z of (15) under all possible sign combinations of the converter pole voltages from Table I are obtained and presented in (16).

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According to IEEE Standard 1159 [25], the Imbalance Factor, the metric indicating the unbalanced depth of a three-phase system, is defined as the ratio of the magnitude of the negative sequence component to the magnitude of the positive sequence component as shown in (17). The definition of IF (Imbalance Factor) in (17) is adopted to quantitatively describe the unbalanced depth of the grid in this paper. Equation (17) is further developed into (18) using the variables considered in this paper.

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The proposed model and control technique are evaluated under these representative types of grid imbalance. However, the proposed concept is not necessarily limited to these four types of grid imbalances since the proposed model and the control technique are formulated on the basis of generalized unbalanced operating conditions. The Imbalance Factor can effectively describe the unbalanced depth, which is the metric of how the grid is unbalanced, in all four cases. Therefore, the different behaviors of converter under different types of grid imbalance can be compared with each other in a more consistent manner.

As an example, the correlation of IF against the per unit amplitude of the smallest phase voltage for Type B, Type C and Type D are given in Table II. Using the model of the neutral point current described in (11)-(16), the effect of an unbalanced ac grid on the neutral point deviation and its voltage ripple can be analyzed.


TABLE II IF ACCORDING TO THE UNBALANCED DEGREE

Voltage (PU)

Imbalance Factor (%)

Type B

Type C

Type D

1

0

0

0

0.9

3.45

3.45

3.57

0.8

7.14

7.14

7.69

0.7

11.11

11.11

12.5

0.6

15.38

15.38

18.18

0.5

20

20

25

0.4

25

25

33.33

0.3

30.43

30.43

43.75

0.2

36.36

36.36

57.14

0.1

42.86

42.86

75

0

50

50

100


Fig. 3 presents the frequency spectrum of the neutral point current using the proposed model of (15) under three different types of unbalanced ac grids: Type B, C and D. without applying the proposed compensation control scheme. The dominant low-order harmonic components up to the 3rd-order including the dc offset and the fundamental component are plotted with respect to various Imbalance Factor values. All of the types (B, C and D) exhibit a similar pattern of increased fundamental component vs. increased IF. It is noted from Fig. 3 that even under normal balanced grid input conditions (IF = 0) the neutral point current is rich in the 3rd-order harmonic component. This observation is consistent with the models of (4) and (A-4).


Fig. 3. Harmonic components of the neutral point current [A] vs. the Imbalance Factor [%] under unbalanced three-phase conditions using the conventional control scheme.

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When the grid input becomes unbalanced, the uncontrolled negative sequential component of the ac input current is generated, i.e. the ac input current becomes unbalanced. This uncontrolled negative sequential component of the ac input current interacts with the second-order harmonic of the absolute value of the switching function to generate the fundamental component of the neutral point current as described in (A-4) of the Appendix. As a result, it can be concluded that an unbalanced ac grid causes a significant fundamental component of the neutral point current which may lead to a neutral point deviation and ripple in dc-link voltage.



Ⅳ. CONTROL OF NEUTRAL POINT DEVIATION UNDER UNBALANCED THREE-PHASE GRID CONDITIONS

In this paper, a control strategy is proposed to reduce ripple under a neutral point deviation and unbalanced AC grid. This control strategy is based on (15) and observations are shown in Fig. 3. As noted before, the statement of the neutral point current in (15) has different values (X, Y and Z) depending on the symbolic values of the converter pole voltage shown in Table I. Table I has eight combinations of symbol values. However, case 5 is only the inverse of the symbol in case 1. Therefore, if focusing on the absolute amplitude of the neutral point current, only four different combinations of symbols need to be considered during one fundamental line cycle of 16.76ms. The proposed control strategy is to minimize the peak of the neutral point current, especially for the basic component under an unbalanced AC grid input. It should be noted that the numerical description of (15), i.e. the values of the coefficients, is dependent on the combination of symbols in the converter poles. During one primary line period, a neutral point current (15) can follow several different explanations. Therefore, the dc and second harmonic terms described in (15) are not necessarily equivalent to dc and twice the input line frequency terms of the neutral point current for one complete line period. It is found from a graphical reconstruction of the neutral point current based on (15) that the localized twice harmonic terms of (15) are associated more with the generation of the higher-order harmonic terms of the neutral point current for one complete line period. In a similar manner, the localized dc offset term of (15) is associated more with the generation of the fundamental component of the neutral point current which is shown to be almost linearly proportional to the Imbalance Factor of the ac grid in Fig. 3. Therefore, this paper focuses on this localized dc offset term in order to minimize the fundamental component of the neutral point current under an unbalanced ac grid input. Therefore, in other words, it may be possible to minimize the peak of neutral point current by decreasing the localized dc offset term in (15). The localized dc offset term in (15) corresponding to a particular sign combination under which the neutral point current reaches its peak is described in (19) for a 3-phase imbalance condition of Type B.

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There are many ways to minimize or even nullify (19) in order to reduce the fundamental component of neutral point current under unbalanced operating conditions. Among these many possible methods, this paper employs a control scheme to keep the negative sequential component of the ac input current zero; In = 0. It is understood from (19) that keeping the zero negative sequential component of ac input current reduces the absolute value of the dc offset term in (15). In order to further validate the reasoning of the proposed control scheme, the localized dc offset term and total neutral point current in (15) are reconstructed under both the conventional and proposed control schemes.

At the top of Fig. 4, the localized dc offset term during one complete line period is compared. In addition, the total neutral point current during one complete line period is compared in the bottom of Fig. 4. This control action is intended to reduce the localized dc offset term (X+Z) of the neutral point current as described in Fig. 4. It is noted that this localized dc offset term (X+Z) is not directly related to the conventional dc component of the neutral point current. This localized dc offset term (X+Z) is more directly associated with the fundamental frequency component of the neutral point current. When compared to uncompensated control action, the proposed control strategy can successfully reduce the value of (19) even under the existence of the Vn term. It is noted from the comparison result of Fig. 4 that the localized dc offset term of X+Z in (19) is influenced more by In than Vn. The regulation of the negative sequence component of the ac input current to zero greatly reduces the twice fundamental frequency ripple of the dc-link voltage. As a result, this paper adopts this regulation of the negative sequence component of the ac input current to zero.


Fig. 4. Reconstruction of neutral point current based on (16) under imbalance type B condition.

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The overall control structure consists of two nested regulating loops: the outer dc-link voltage regulating loop and the inner ac current regulating loop, as shown in Fig. 5. The proposed control scheme is implemented in dual current regulators, i.e. positive sequence and negative sequence synchronous frame current regulators, as shown in Fig. 6. The inner current loop is made up of two parallel dq synchronous frame current regulators: one for the positive sequence and the other for the negative sequence. It is required that the bandwidth of the current regulation loop is high enough to maintain the fast dynamics of the entire system. In general, the sequence separation method of the input current involves a low pass filter or notch filter to filter out the negative (positive) sequential component of twice the input frequency in the positive (negative) sequence reference frame. The low pass filter and notch filter in the current feedback path usually undermine the bandwidth of the current regulation loop or phase margin of the system.


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Fig. 5. Overall control block diagram for the proposed control method in a grid-side converter.


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Fig. 6. Proposed control block diagram (dual frame current regulator).



Ⅴ. SIMULATION RESULTS OF THE PROPOSED COMPENSATING METHOD

The proposed control method is verified through the simulations and the results are presented in this section. The simulations are performed based on the circuit parameters and operating conditions summarized in Table III.


TABLE III IRCUIT PARAMETERS AND OPERATING CONDITIONS FOR THE SIMULATION

Parameters

Values

Rated power (Prated)

5 MW

Rated line voltage (Vllrated)

4160 V

Rated ac input current (Irated)

693 A

Frequency (fin)

60 Hz

DC link voltage (VDC)

7000 V

DC link capacitance (CDC)

2 mF

Converter switching frequency (fsw)

1020 Hz

Grid side line inductance (Ls)

0.46 mH (0.05 pu)

Transformer leakage inductance (Ltr)

1.1 mH (0.12 pu)

Filter inductance (Lf)

1.5 mH (0.16 pu)

Filter capacitance (Cf)

0.34 mF (0.45 pu)

Filter resistance (Rf)

0.92 Ω (0.267 pu)


Fig. 7 shows the dc-link voltages along with its frequency spectrum under unbalanced grid input conditions (IF=20) for two different control methods: the conventional control and the proposed control method. The conventional control method refers to a single frame current regulator that only regulates the positive sequential component of the ac input current. It is noted from Fig. 8 that the voltage ripple of the dc link is smaller for the proposed control method in both the time domain and the frequency domain.


Fig. 7. Waveforms and frequency spectrums of dc-link voltage under unbalanced operating conditions.

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Fig. 8. Waveforms and frequency spectrums of neutral point current under unbalanced operating conditions.

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The dominant 2nd-order harmonic component is clearly reduced by the proposed controller when compared to the conventional case. Simulated waveforms of the neutral point current under the same conditions as Fig. 7 are presented in Fig. 8. The proposed control scheme reduces the amplitude of the dominant harmonic of the fundamental component. Figs. 7 and 8 confirm the target of the proposed control scheme, which is to minimize the fundamental component of the neutral point current by nullifying the negative sequential component of the ac input current (In) in (19).

A comparison of the conventional and proposed control schemes under various values for the Imbalance Factor has been carried out in simulation and the key harmonic spectrum is provided in Figs. 9 and 10. Fig. 9 presents the harmonic spectrum of dc-link voltage under various values for the Imbalance Factor for both the conventional and proposed control schemes. In addition, the harmonic spectrum of the neutral point current is given in Fig. 10. It is noted from Figs. 9 and 10, that the 2nd-order harmonic of the dc-link voltage and the fundamental component of the neutral point current are clearly reduced by employing the proposed control scheme.


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Fig. 9. Frequency spectrums of dc-link voltage under various unbalanced operating conditions using the conventional and proposed control methods.


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Fig. 10. Frequency spectrums of neutral point current under various unbalanced conditions using the conventional and proposed control methods.



Ⅵ. EXPERIMENT RESULTS

The proposed control method is also verified through experiments. The experiments have been performed using a laboratory prototype of 15kW. The circuit parameters and operating conditions of the experiments are given in Table IV.


TABLE IV PARAMETERS AND OPERATING CONDITIONS FOR THE EXPERIMENTS

Parameters

Values

Rated power (P)

11 KW

Rated line voltage (Vll)

346 V

Rated ac input current (I)

18 A

Frequency (fin)

60 Hz

DC link voltage (VDC)

300 V

DC link capacitance (CDC)

2 mF (9.6 J/kVA)

Converter switching frequency (fsw)

4 KHz

Imbalance Factor (IF)

3.5%

Balance grid condition

Grid side line inductance (Ls)

0.56 mH(0.02PU)

Unbalanced grid condition

A-phase line inductance (Las)

0.56 mH(0.02PU)

B-phase line inductance (Lbs)

0.56 mH(0.02PU)

C-phase line inductance (Lcs)

3.86 mH(0.11PU)


Fig. 11 shows the experiment setup for the proposed control strategy in a 3-level NPC converter. The experiment setup consists of a DSP controller, a power stage and a load. The unbalanced operating conditions are implemented by connecting an additional filter inductor in the ac input side of c-phase during the experiment.


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Fig. 11. Experimental setup.


The depth of the grid imbalance in terms of the proposed metric (Imbalance Factor) corresponding to the condition employed in the experiment is given in Table IV. All of the experimental result presented in this paper have been obtained under this particular imbalance implementation setup unless otherwise noted. Figs. 12 and 13 show experimental waveforms of the conventional control method under unbalanced grid operating conditions. Three-phase ac input currents and dc-link voltage are given in Fig. 12. It is noted from Fig. 12 that the ac input currents are unbalanced. This unbalanced ac input current is caused by an ac grid imbalance condition without a proper compensation method.


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Fig. 12. Waveforms of input currents and dc-link voltage using the conventional control method under unbalanced condition.


Fig. 13 presents the d-component and q-component of the ac input currents in a positive rotating synchronous reference frame and a negative rotating synchronous reference frame, respectively. The negative sequential component becomes a ripple component of 120 Hz in the positive rotating synchronous reference frame. In addition, the positive sequential component becomes a ripple component of 120 Hz in the negative rotating synchronous reference frame. The different offset and ripple size of the waveforms in Fig. 13 are due to the fact that the positive and negative sequential component have different amplitudes.


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Fig. 13. Waveforms of the dq-components of the ac input currents in positive and negative rotating synchronous reference frames using the conventional control method under unbalanced condition.


An experiment is performed under the same unbalanced operating conditions for the proposed control scheme and the results are shown in Figs. 14 and 15. As expected from the control target, the ac input currents are kept balanced in Fig. 14. Since the negative sequential component of the ac input current is almost negligible, the ripple component of 120 Hz in the positive rotating synchronous reference frame is also almost zero as shown in Fig. 15. On the other hand, the d-component and q-component of the ac input currents in the negative rotating synchronous reference frame have a dominant ripple component of 120 Hz due to the positive sequential component. This observation verifies the intended function of the proposed control scheme, which is to regulate the negative sequential component of the ac input currents at zero.


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Fig. 14. Waveforms of input currents and dc-link voltage using the proposed control method under unbalanced condition.


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Fig. 15. Waveforms of the dq-components of ac input currents in the positive and negative rotating synchronous reference frames using the proposed control method under unbalanced condition.


In Fig. 16, the dc-link voltage along with the upper and lower half of the dc-link voltage are described for the case of the conventional control method. The neutral point current under the same unbalanced operating conditions as in Fig. 16 is presented in Fig. 17. The measured neutral point current has been averaged in a localized time window and plotted in Fig. 17.


Fig. 16. Waveforms and frequency spectrum of dc-link voltage using the conventional control method under unbalanced condition (Ch.1: Vdc; Ch.2: Vdc_upper; Ch.3: Vdc_lower).

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Fig. 17. Spectrum of local averaged neutral point current using the conventional control method under unbalanced condition.

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In other words, the higher order harmonics due to the switching frequency are filtered out from the scope data in order to better display the lower order harmonic components of the neutral point current. The frequency spectrum of the local averaged neutral point current is shown at the bottom of Fig. 17. It is noted from Fig. 17 that the fundamental and 3rd-order harmonic components are dominant as expected from the theoretical result of Fig. 3.

The performance of the proposed control method has been tested and some waveforms are presented in Fig. 18 and 19 under unbalanced operating conditions (IF=3.5). The dc-link voltage along with the upper and lower half of the dc-link voltage are described in Fig. 18. When compared to the waveforms in Fig. 16, the dc-link voltage has a reduced size of the ripple component in Fig. 18.


Fig. 18. Waveforms and frequency spectrum of dc-link voltage using the proposed control method under unbalanced condition.

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Fig. 19. Spectrum of local averaged neutral point current using the proposed control method under unbalanced condition.

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The local averaged neutral point current is illustrated in Fig. 19. This figure also gives the frequency spectrum of the local averaged neutral point current. When compared to the frequency spectrum shown in Fig. 17, the proposed control method clearly reduces the fundamental component of the neutral point current. This observation is in line with the simulation results confirming the intended feature of the proposed control scheme.



Ⅶ. CONCLUSION

This paper presents an analysis of the neutral point potential variation and its harmonic contents for a 3-level NPC converter under an unbalanced ac grid input. The analysis is carried out based on a model of the average current flowing through the neutral point of the dc-link. In this paper, the control scheme for compensating neutral point deviations and the dominant harmonic components under unbalanced ac grid conditions is also investigated. This control scheme can be effectively analyzed by using both the positive and negative sequence components of the converter output voltages and ac input currents. The proposed control scheme is intended to nullify the negative sequential component of the ac input currents, which keeps the ac input currents balanced. Simulation and experimental results confirm that the proposed control scheme makes it possible to reduce the neutral point potential variation and its ripple under unbalanced ac grid operating conditions.



APPENDIX

The proposed model of the neutral point current in (3) is repeated in (A1).

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It is assumed that the switching modulation functions of the converter output pole voltages are balanced without any added negative sequential components. Then the absolute value of the switching function can be effectively represented by a dc offset term and a dominant second-order harmonic term as shown in (A2).

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It is also assumed that the ac input current becomes unbalanced due to the influence of grid imbalance. Then the ac input current can be represented by both the positive and negative sequential components as in (A3).

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It is noted from (A4) that the neutral point current finally has two major frequency components: the fundamental and the third-order. The fundamental frequency component of the neutral point current depends on the negative sequential component of the ac input current, while the third-order harmonic component depends on the positive sequential component of the ac input current. Equation (A4) is expressed to illustrate the features of Fig. 3. There are two main features shown in Fig. 3. Under balanced grid conditions, the dominant frequency term of the neutral point current is 180Hz. However, under unbalanced grid conditions, the 180Hz component is kept similar to that of the balanced condition while the 60Hz component is clearly increased. Thus, equation (A4) explains the characteristics of the neutral point current according to various grid conditions.

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ACKNOWLEDGMENT

This research was supported by Korea Electric Power Corporation. (Grant number: R18XA04)



REFERENCES

[1] J. Zarogoza, J. Pou, S. Ceballos, E. Robles, and C. Jaen, “Voltage-balance compensator for a carrier-based modulation in the neutral-point-clamped converter,” IEEE Trans. Ind. Electron., Vol. 56, No. 2, pp. 305-314, Feb. 2009.

[2] J. Zarogoza, J. Pou, S. Ceballos, E. Robles, P. Ibanez, and J. L. Villate, “A comprehensive study of a hybrid modulation technique for the neutral-point-clamped converter,” IEEE Trans. Ind. Electron., Vol. 56, No. 2, pp. 294-304, Feb. 2009.

[3] C. Wang and Y. Li, “Analysis and calculation of zero- sequence voltage considering neutral-point potential balancing in three-level NPC converter,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2262-2271, Jul. 2010.

[4] C. Wang and Y. Li, “Analysis and calculation of zero- sequence voltage considering neutral-point potential balancing in three-level NPC converter,” IEEE Trans. Ind. Electron., Vol. 57, No. 7, pp. 2262-2271, Jul. 2010.

[5] W. Lixiang, W. Yuliang, L. Chongjian, W. Huiqing, L. Shixiang, and L. Fahai, “A novel space vector control of three-level PWM converter,” Proc. IEEE Power Electron. Drive Syst., pp.745-750, 1999.

[6] N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters,” IEEE Trans. Power Electron., Vol. 15, No. 2, pp.242-249, Mar. 2000.

[7] K. Yamanaka, A. M. Hava, H. Kirino, Y. Tanaka, N. Koga, and T. Kume, “A novel neutral point potential stabilization technique using the information of output current polarities and voltage vector,” in Conf. Rec. IEEE IAS Annu. Meeting, pp. 851-858, 2001.

[8] S. Busquets-Monge, J. D. Ortega, J. Bordonau, J. A. Beristain, and J. Rocabert, “Closed-loop control of a three-phase neutral-point-clamped inverter using an optimized virtual-vector-based pulsewidth modulation,” IEEE Trans. Ind. Electron., Vol. 55, No. 5, pp. 2061-2071, May 2008.

[9] B. Abdul Rahiman, G. Narayanan, and V. T. Ranganathan, “Modified SVPWM method for three level VSI with synchronized and symmetrical waveforms,” IEEE Trans. Ind. Electron., Vol. 54, No. 1, pp. 486-494, Feb. 2007.

[10] Y. Lai, Y. Chou, and S. Pai, “Simple PWM technique of capacitor voltage balance for three-level inverter with dc-link voltage sensor only,” in Proc. 33rd Annu. Conf. IEEE IECON, pp. 1749-1754, 2007.

[11] K. H. Bhalodi and P. Agrawal, “Space vector modulation with dc-link voltage balancing control for three-level inverters,” in Proc. Int. Conf. PEDES, pp. 1-6, 2006.

[12] J. Suh, C. Choi, and D. Hyun, “A new simplified space- vector PWM method for three-level inverters,” in Proc. 14th Annu. APEC, pp. 515-520, 1999.

[13] J. Holtz and N. Oikonomou, “Neutral point potential balancing method at low modulation index for three-level inverter medium voltage drives,” in Conf. Rec. IEEE IAS Annu. Meeting, pp. 1246-1252, 2005.

[14] J. Holtz and N. Oikonomou, “Neutral point potential balancing method at low modulation index for three-level inverter medium voltage drives,” IEEE Trans. Ind. Electron., Vol. 43, No. 3, pp. 761-768, May/Jun. 2007.

[15] M. Malinowski, S. Stynski, W. Kolomyjski, and M. P. Kazmierkowski, “Control of three-level PWM converter applied to variable-speed-type turbines,” IEEE Trans. Ind. Electron., Vol. 56, No. 1, pp. 69-77, Jan. 2009.

[16] A. Choudhury and P. Pillay, “Modified DC-bus voltage balancing algorithm for a three-level neutral-point-clamped PMSM inverter drive with reduced commom-mode voltage,” IEEE Trans. Ind. Appl., Vol. 52, No. 1, pp. 272- 292, Jan./Feb. 2016.

[17] U. Choi, F. Blaabjerg, and K. Lee, “Method to minimize the low-frequency neutral-point voltage oscillations with time-offset injection for neutral-point-clamped inverters,” IEEE Trans. Ind. Appl., Vol. 51, No. 2, pp. 1678-1691, Mar./Apr. 2015.

[18] S. Ogasawara and H. Akagi, “Analysis of variation of neutral point potential in neutral-point-clamped voltage source PWM inverter,” in Conf. Rec. IEEE IAS Annu. Meeting, pp. 965-970, 1993.

[19] S. Qiang, L. Wenhua, Y. Qingguang, X. Xiaorong, and W. Zhonghong, “A neutral-point potential balancing method for three-level NPC inverters using analytically injected zero-sequence voltage,” in Proc. IEEE Appl. Power. Electron. Conf., pp. 228-233, 2003.

[20] L. Jun, Q. H. Alex, Q. Zhaoming, and Z. Huijie, “A novel carrier-based PWM method for 3-level NPC inverter utilizing control freedom degree,” in Proc. IEEE Power Electron. Spec. Conf., pp. 1899-1904, 2007.

[21] A. Videt, P. Le Moigne, N. Idir, P. Baudesson, and X. Cimetiere, “A new carrier-based PWM providing common- mode-current reduction and dc-bus balancing for three- level inverters,” IEEE Trans. Ind. Electron., Vol. 54, No. 6, pp. 3001-3011, Dec. 2007.

[22] K. Jung and Y. Suh, “Analysis of neutral point deviation in 3-level NPC converter under unbalanced 3-phase AC grid,” IEEE Energy Conversion Congress and Expopsition (ECCE)., pp. 1-8, Sep. 2016.

[23] J. Shen, S. Schroder, B. Duro, and R. Roesner, “A neutral- point balancing controller for a three-level inverter with full power-factor range and low distortion,” IEEE Trans. Ind. Appl., Vol. 49, No. 1, pp. 138-148, Jan./Feb. 2013.

[24] A. Choudhury and P. Pillay, “Discontinuous hybrid-PWM- based dc-link voltage balancing algorithm for a three-level neutral-point-clamped (NPC) traction inverter drive,” IEEE Trans. Ind. Appl., Vol. 52, No. 4, pp. 3071-3082, Jul./Aug. 2016.

[25]  “IEEE recommended practice for monitoring electric power quality,” IEEE Std 1159-2009 (Revision of IEEE Std 1159-1995), pp. 15, Jun. 2009.

[26] M. Bollen, “Characterisation of voltage sags experienced by three-phase adjustable-speed drives,” IEEE Trans. Power. Del., Vol. 12, No. 4, pp. 1666-1671, Oct. 1997.

[27] Y. Suh, Y. Go, and D. Roh, “A comparative study on control algorithm for active front-end rectifier of large motor drives under unbalanced input,” IEEE Trans. Ind. Appl., Vol. 47, No. 3, pp. 1419-1431, May/Jun. 2011.

[28] Y. Suh and A. Lipo, “Control scheme in hybrid synchronous stationary frame for PWM AC/DC converter under generalized unbalanced operating conditions,” IEEE Trans. Ind. Appl., Vol. 42, No. 3, pp. 825-835, May/Jun. 2016.



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Kyungsub Jung was born in the Republic of Korea, in 1982. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from Chonbuk National University, Jeonju, Korea, in 2008, 2012 and 2018, respectively. His current research interests include high-power power conversion systems for renewable energy sources and medium-power electric drive systems.


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Yongsug Suh was born in Seoul, Korea. He received his B.S. and M.S. degrees in Electrical Engineering from Yonsei University, Seoul, Korea, in 1991 and 1993, respectively; and his Ph.D. degree in Electrical Engineering from the University of Wisconsin, Madison, WI, USA, in 2004. From 1993 to 1998, he was an Application Engineer in the Power Semiconductor Division of Samsung Electronics, Seoul, Korea. From 2004 to 2008, he was a Senior Engineer in the Power Electronics and Medium-Voltage Drives Division of ABB, Turgi, Switzerland. Since 2008, he has been with the Department of Electrical Engineering, Chonbuk National University, Jeonju, Korea, where he is presently working as a Professor. His current research interests include high-power power conversion systems for renewable energy sources and medium-voltage electric drive systems.