사각형입니다.

https://doi.org/10.6113/JPE.2018.18.3.802

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Hybrid Control Strategy of Phase-Shifted Full-Bridge LLC Converter Based on Digital Direct Phase-Shift Control


Bing Guo, Yiming Zhang*, Jialin Zhang*, and Junxia Gao*


†,*Faculty of Information Technology, Beijing University of Technology, Beijing, China



Abstract

A digital direct phase-shift control (DDPSC) method based on the phase-shifted full-bridge LLC (PSFB-LLC) converter is presented. This work combines DDPSC with the conventional linear control to obtain a hybrid control strategy that has the advantages of linear control and DDPSC control. The strategy is easy to realize and has good dynamic responses. The PSFB-LLC circuit structure is simple and works in the fixed frequency mode, which is beneficial to magnetic component design; it can realize the ZVS of the switch and the ZCS of the rectifier diode in a wide load range. In this work, the PSFB-LLC converter resonator is analyzed in detail, and the concrete realization scheme of the hybrid control strategy is provided by analyzing the state-plane trajectory and the time-domain model. Finally, a 3 kW prototype is developed, and the feasibility and effectiveness of the DDPSC controller and the hybrid strategy are verified by experimental results.


Key words: Dynamic performance, Full-bridge converter, LLC, Soft-switching, State-plane analysis


Manuscript received Oct. 10, 2017; accepted Feb. 6, 2018

Recommended for publication by Associate Editor Chun-An Cheng.

Corresponding Author: guobing2014@emails.bjut.edu.cn Tel: +86-1067396621, Beijing University of Technology

*Faculty of Inform. Technol., Beijing University of Technology, China



Ⅰ. INTRODUCTION

The helicopter transient electromagnetic (HTEM) system is one of the most important platforms in the geological exploration field owing to its high efficiency and low cost [1], [2]. HTEM survey is an effective means of exploring complex terrain conditions, such as desert, swamp, and forest [2], [3]. By taking advantage of pulsed magnetic fields, a typical HTEM system generates eddy currents in the target reservoir and uses a detection device to detect the induced electromagnetic field for inferring the underground electrical structure [4]. Along with the development of modern HTEM systems, the requirements of transmitter power converters are gradually increasing, including efficiency, power density, and dynamic response performance [5]-[7]. Resonant converter topologies, such as quasi-resonant converter, series resonant converter, parallel resonant converter, and LLC resonant converter, are usually employed in HTEM transmitter power converters [8]-[12]. The LLC resonant converter is becoming increasingly popular for its inherent merits, including wide soft-switching range, high power density, and low electromagnetic interference noise [13], [14].

Variable frequency control is usually used to adjust the voltage gain of the LLC converter resonator. When the voltage gain is less than 1, the secondary side rectifier cannot achieve ZCS and the converter efficiency becomes low [15]. Besides, the wide switching frequency range is not helpful to the design of magnetic components and electromagnetic compatibility [16]. In addition, the output power of the HTEM transmitter pulsates, which requires the power supply to adapt to drastic load changes and have good dynamic performance.

Recently, some new control methods have been proposed for LLC converters, including PWM control, phase-shift control, and variable frequency and phase-shift hybrid control. A PWM control method is introduced into the LLC converter in [17] to address the problem of high loss in high-frequency and light-load conditions. A frequency adaptive phase-shift modulation control strategy is proposed in [18] for LLC resonant converters with wide-input-voltage applications, and an active rectifier is employed to reduce rectifier losses. For the distributed and server power supplies, a secondary phase- shift control of the LLC resonant converter is introduced to provide accurate shutdown time settings [19]. In the normal operating mode, the converter efficiency is higher than that of the conventional LLC converter because the resonator is operated at resonant frequency. A fixed-frequency PWM control method for dual-bridge LLC converters is developed in [20] and [21] to extend the input voltage range. The converter improves the range of voltage gain, which simplifies the design of parameters and magnetic components. A hybrid control strategy of phase-shift and variable-frequency controls extends the output range of bidirectional LLC converters in [22], and a linear regulator is used to realize a closed-loop control. The above research focuses on the basic working principle of the LLC converter control method, and the feedback compensation adopts the traditional linear compensation. Lee et al. propose an optimal trajectory control (SOTC) method using LLC converters based on the phase plane trajectory method to achieve the rapid adjustment of load mutations [23], [24]. However, the method is deduced based on the frequency conversion control model and cannot be applied directly to the PSFB-LLC converter. Therefore, the dynamic response of the PSFB-LLC converter in the case of load parameter change should be improved.

The present study proposes a digital direct phase-shift angle control method that is combined with the traditional linear compensator to obtain a hybrid feedback control strategy for PSFB-LLC converters. Compared with the conventional linear feedback control, the proposed strategy improves transient response performance while maintaining control accuracy. The PSFB-LLC converter uses the constant frequency phase-shift control, thereby simplifying the design of circuit parameters and magnetic components. This paper also presents the five working stages and seven modes of the PSFB-LLC converter and establishes an accurate time- domain model. All main switches and rectifier diodes are softly switched over a wide load range. On the basis of the state-plane trajectory method and the time-domain model, this study realizes DDPSC and proposes a hybrid controller with a simple logical structure. Finally, the experimental waveform of the strategy is provided, and the correctness of theoretical analysis is verified.



Ⅱ. ESTABLISHMENT OF THE MODEL FOR PSFB-LLC CONVERTER

Fig. 1 illustrates the PSFB-LLC resonant converter circuit topology, which is the same as that of the traditional full-bridge LLC converter, and is thus not described here in detail. In the figure, the input voltage of the converter is Vin; the output voltage of the converter is Vo; the switching frequency of the phase shifter is fs; the switching frequency is set to the resonant frequency, that is, fs = fr; and the phase-shift angle is 그림입니다.
원본 그림의 이름: CLP000013c8003e.bmp
원본 그림의 크기: 가로 45pixel, 세로 49pixel. The transformer turns ratio is n, the resonant inductance is Lr, the resonant capacitor is Cr, and the transformer magnetic inductor is Lm.


그림입니다.
원본 그림의 이름: CLP00001f0044eb.bmp
원본 그림의 크기: 가로 1472pixel, 세로 701pixel

Fig. 1. PSFB-LLC converter topology.


A. Converter Resonant Stages

The working states of the PSFB-LLC converter circuit in two half cycles are symmetrical. An analysis of the first half cycle shows five stages, namely, stages P, O, Px, Nx, and Ox [22]. Stages P and O exist when S1 and S4 are ON, while stages Px, Nx, and Ox exist when S3 and S4 are ON. The equivalent circuit is shown in Fig. 2. The stages are defined as follows:


Fig. 2. Simplified equivalent circuit of the resonant cavity.

그림입니다.
원본 그림의 이름: CLP000013c8003b.bmp
원본 그림의 크기: 가로 653pixel, 세로 484pixel

(a) P, Px, Nx

그림입니다.
원본 그림의 이름: CLP000013c8003c.bmp
원본 그림의 크기: 가로 706pixel, 세로 482pixel

(b) O, Ox


Stage P: S1 and S4 are ON, Dr1 and Dr4 are ON, and the energy is delivered from the transformer’s primary side to its secondary side. vm = nVo, ir > im, im increases linearly.

Stage O: S1 and S4 are ON, Dr1Dr4 are OFF, and no energy delivery occurs. vm < nVo, ir = im, and the magnetizing inductor Lm joins the resonance.

Stage Px: S3 and S4 are ON, Dr1 and Dr4 are ON, the input power is disconnected from the resonator, and the energy is delivered from the resonator to the secondary side. vm = nVo, ir > im, im increases linearly.

Stage Nx: S3 and S4 are ON, Dr2 and Dr3 are ON, the input power is disconnected from the resonator, and the energy is delivered from the primary side to the secondary side. vm = –nVo, ir < im, im decreases linearly.

Stage Ox: S3 and S4 are ON, Dr1Dr4 are OFF, and Cr is resonant with Lr and Lm, vm < nVo, ir = im.

Normalization is carried out to facilitate the calculation and analysis. The subscript with n indicates a normalized value, and the selected reference values are vbase=nVo, ibase = nVo/Zr, Zbase = Zr, fbase = fr, and pbase = 그림입니다.
원본 그림의 이름: CLP000013c8007a.bmp
원본 그림의 크기: 가로 192pixel, 세로 76pixel, where

그림입니다.
원본 그림의 이름: CLP00001f000003.bmp
원본 그림의 크기: 가로 437pixel, 세로 202pixel           (1)

Other symbols are listed in Table I.


TABLE I SYMBOL DESCRIPTION OF THE TIME-DOMAIN MODEL

Symbol

Description

irXn

normalized current of Lr in stage X

IrXn

normalized max current of Lr

그림입니다.
원본 그림의 이름: CLP0000164014fc.bmp
원본 그림의 크기: 가로 50pixel, 세로 56pixel

phase-shift angle in stage X

그림입니다.
원본 그림의 이름: CLP000016400001.bmp
원본 그림의 크기: 가로 72pixel, 세로 52pixel

initial phase of irXn

imXn

normalized current of Lm in stage X

ImXn

normalized starting current of Lm in stage X

vCXn

normalized voltage of Cr in stage X

vmXn

normalized voltage of Lm in stage X


When 그림입니다.
원본 그림의 이름: CLP000016400002.bmp
원본 그림의 크기: 가로 161pixel, 세로 62pixel, stages P and O may be represented in the circuit, and their resonance values are expressed by Equations (2) and (3), respectively.

그림입니다.
원본 그림의 이름: CLP000015d40bfa.bmp
원본 그림의 크기: 가로 809pixel, 세로 397pixel        (2)

그림입니다.
원본 그림의 이름: CLP00000aec0001.bmp
원본 그림의 크기: 가로 949pixel, 세로 425pixel   (3)

where 그림입니다.
원본 그림의 이름: CLP000016400003.bmp
원본 그림의 크기: 가로 171pixel, 세로 49pixel frt, m = (Lm+Lr)/Lr, and M = nVo/Vin.

When 그림입니다.
원본 그림의 이름: CLP000016400004.bmp
원본 그림의 크기: 가로 212pixel, 세로 66pixel, stages Px, Nx, and Ox may be represented in the circuit, and their resonance values are expressed by Equations (4) to (6), respectively.

그림입니다.
원본 그림의 이름: CLP00000aec0002.bmp
원본 그림의 크기: 가로 735pixel, 세로 417pixel   (4)

그림입니다.
원본 그림의 이름: CLP00000aec0003.bmp
원본 그림의 크기: 가로 746pixel, 세로 420pixel   (5)

그림입니다.
원본 그림의 이름: CLP00000aec0004.bmp
원본 그림의 크기: 가로 862pixel, 세로 438pixel      (6)


B. Working Modes

The five stages are combined in different orders to form different working modes. For example, the PPxOx mode indicates that the resonant tank first operates in stage P, then enters stage Px, and ends with Ox during a half cycle. Within the entire output power range and phase-shift angle, seven major working modes exist: P, OPO, PPxNx, PPxOx, OPPxOx, OPOOx, and PPxOxNx. Fig. 3 shows the normalized resonant voltage and current waveforms of these seven working modes.


Fig. 3. Typical waveforms of the PSFB-LLC operating modes. (a) P. (b) OPO. (c) OPPxOx. (d) OPOOx. (e) PPxOx. (f) PPxOxNx. (g) PPxNx

그림입니다.
원본 그림의 이름: CLP000015d40002.bmp
원본 그림의 크기: 가로 1262pixel, 세로 493pixel

(a)

그림입니다.
원본 그림의 이름: CLP000015d40003.bmp
원본 그림의 크기: 가로 1243pixel, 세로 482pixel

(b)

그림입니다.
원본 그림의 이름: CLP000015d40004.bmp
원본 그림의 크기: 가로 1251pixel, 세로 483pixel

(c)

그림입니다.
원본 그림의 이름: CLP000015d40005.bmp
원본 그림의 크기: 가로 1247pixel, 세로 494pixel

(d)

그림입니다.
원본 그림의 이름: CLP000015d40006.bmp
원본 그림의 크기: 가로 1246pixel, 세로 480pixel

(e)

그림입니다.
원본 그림의 이름: CLP000015d40007.bmp
원본 그림의 크기: 가로 1260pixel, 세로 486pixel

(f)

그림입니다.
원본 그림의 이름: CLP000015d40008.bmp
원본 그림의 크기: 가로 1246pixel, 세로 489pixel

(g)


When the phase-shift angle is equal to π, stage P will dominate the entire half cycle while the other stages vanish. In the P mode, θP = π, ir, vCr is pure sinusoidal, and im is a triangle waveform, as shown in Fig. 3(a). However, under a light-load condition, the resonator may operate in OPO mode, which is shown in Fig. 3(b). When the phase-shift angle is smaller than π, OPOOx, OPPxOx, PPxOx, PPxOxNx, and PPxNx occur in turn as the output power increases, as shown in Figs. 3(c) to 3(g).

Depending on the continuity of the capacitor voltage and the inductor current, the convergence between the different stages of each mode should satisfy the continuity condition. If A and B represent two adjacent stages, then the continuity condition can be expressed as

그림입니다.
원본 그림의 이름: CLP000015d40009.bmp
원본 그림의 크기: 가로 461pixel, 세로 265pixel         (7)

Symmetrically, the values of ir, im, and vCr at the beginning should be equal to those at the end of the half cycle, but their signs should be opposites. If we use S to denote the start stage and T to denote the end stage in a half cycle, then the symmetry conditions are given by

그림입니다.
원본 그림의 이름: CLP000015d4000a.bmp
원본 그림의 크기: 가로 512pixel, 세로 261pixel        (8)

Given that the output current is discontinued in stages O and Ox, only stages P, Px, and Nx are involved in energy delivery. Thus, the normalized output power can be expressed as (9).

그림입니다.
원본 그림의 이름: CLP000015d4000b.bmp
원본 그림의 크기: 가로 1056pixel, 세로 294pixel           (9)

According to the sequence of the seven modes, stage O is only linked with stage Ox or P. When stage O is adjoined with stage Ox, the absolute value of voltage vm should be less than nVo. When stage O is adjoined with stage P,

그림입니다.
원본 그림의 이름: CLP000015d4000c.bmp
원본 그림의 크기: 가로 331pixel, 세로 97pixel     (10)

Stage Ox is possibly linked with stage Nx. When stage Ox is adjoined with stage Nx, vm equals –nVo in stage Nx. Thus, at the end of stage Ox,

그림입니다.
원본 그림의 이름: CLP000015d4000d.bmp
원본 그림의 크기: 가로 395pixel, 세로 86pixel   (11)

According to a previous analysis of the stages, at half a switching cycle, when 그림입니다.
원본 그림의 이름: CLP000016400005.bmp
원본 그림의 크기: 가로 163pixel, 세로 64pixel, only stages P and O may be present; therefore,

그림입니다.
원본 그림의 이름: CLP000015d4000e.bmp
원본 그림의 크기: 가로 302pixel, 세로 172pixel      (12)

The complete set of equations of the seven working modes can be obtained according to the boundary constraint of Equations (7)–(12) and the resonance of Equations (2)–(6). Given Pon, 그림입니다.
원본 그림의 이름: CLP000013c80042.bmp
원본 그림의 크기: 가로 45pixel, 세로 49pixel and m, each working mode can be solved. Given that im waveform is sinusoidal in stage O/Ox and linear in stages P, Px, and Nx, the boundary equation of im will lead to a transcendental equation if a working mode contains stage O or Ox. Hence, all DCMs, such as OPO, PPxOx, PPxOxNx, OPPxOx, and OPOOx, have no accurate analytical solutions, whereas modes P and PPxNx can be solved analytically. A numerical analysis tool is used to solve the equations in the working mode of DCM, and an approximate solution can be obtained. Fig. 4 shows that the curves of gain M change with the phase-shift angle.


그림입니다.
원본 그림의 이름: CLP000015d40011.bmp
원본 그림의 크기: 가로 965pixel, 세로 875pixel

Fig. 4. Relationship between phase shift and gain with different output power.


Fig. 4 shows that the gain of the resonator is affected by the phase-shift angle and the output power. Gain M increases monotonically from 0 to 1 as the phase-shift angle increases from 0 to 그림입니다.
원본 그림의 이름: CLP000013c8005d.bmp
원본 그림의 크기: 가로 39pixel, 세로 35pixel when the output power is constant. When the normalized output power is less than 0.1, the gain is slightly greater than 1, and this trend is consistent with the analysis in the literature [25]. When the phase-shift angle remains constant, the gain of the resonant decreases gradually as the output power increases, and the resonant gain tends to be constant when the normalized output power, pon, is greater than 1.

The seven working modes of the PSFB-LLC correspond to different output powers and phase-shift angles. To obtain complete distribution, the dividing lines of different working modes should to be obtained first.

When 그림입니다.
원본 그림의 이름: CLP000016400006.bmp
원본 그림의 크기: 가로 157pixel, 세로 51pixel, the converter works in modes P and OPO. Mode P is heavily loaded, whereas mode OPO is lightly loaded. Mode P only has stage P. Thus, 그림입니다.
원본 그림의 이름: CLP000004241505.bmp
원본 그림의 크기: 가로 181pixel, 세로 65pixel, and the waveforms of ir and vCr are pure sinusoidal. According to the symmetric constraint (8), Equation set (13) can be deduced.

그림입니다.
원본 그림의 이름: CLP000015d40012.bmp
원본 그림의 크기: 가로 357pixel, 세로 234pixel   (13)

Under a light-load condition, the resonator may work in the OPO mode, where vm equals nVo in stage P, and the values of im and ir are equal at the beginning. Therefore, the boundary condition at the edge of mode P to mode OPO is [22]

그림입니다.
원본 그림의 이름: CLP000015d40013.bmp
원본 그림의 크기: 가로 930pixel, 세로 152pixel        (14)

When (14) is substituted into (9), the boundary load power expression is obtained as

그림입니다.
원본 그림의 이름: CLP000015d40014.bmp
원본 그림의 크기: 가로 363pixel, 세로 111pixel   (15)

When 그림입니다.
원본 그림의 이름: CLP000004240001.bmp
원본 그림의 크기: 가로 183pixel, 세로 55pixel, the converter has five modes: OPOOx, OPPxOx, PPxOx, PPxOxNx, and PPxNx. With the increasing output power, the circuit goes through the five stages in order. When the output load tends to zero, the converter is in mode OPOOx; when the output load increases sufficiently, the converter is in PPxNx. PPxNx is the boundary mode of PPxOxNx and PPxNx, PPxOx is the boundary mode of PPxOxNx and PPxOx, while OPOOx is the boundary mode of OPPxOx and OPOOx. Modes PPxOx and OPOOx can be solved by MATLAB, which can obtain an accurate analytical solution of PPxNx.

At the boundary of PPxOxNx and PPxNx, as the output power increases, stages Px and Nx extend gradually, but stage Ox gradually shortens and finally disappears. The PPxNx mode requires that the initial vm of stage Nx is sufficiently low to turn on Dr2 and Dr3 for the converter to directly enter stage Nx after Px without the transition of stage Ox. Therefore, in the boundary PPxNx mode, the initial vm of stage Nx should be equal to –nVo. Given that im and ir are equal at the start of stage Nx, this boundary constraint can thus be expressed as

그림입니다.
원본 그림의 이름: CLP000015d40015.bmp
원본 그림의 크기: 가로 1051pixel, 세로 138pixel      (16)

Furthermore, the im linear variation over the full cycle is represented as a triangle. According to the symmetry,

그림입니다.
원본 그림의 이름: CLP000015d40016.bmp
원본 그림의 크기: 가로 582pixel, 세로 163pixel        &p; (17)

Combining (16) and (17) with (7)–(9) and (12) can solve the gain and load expressions as shown by (18) and (19).

그림입니다.
원본 그림의 이름: CLP000015d40017.bmp
원본 그림의 크기: 가로 799pixel, 세로 198pixel         (18)

그림입니다.
원본 그림의 이름: CLP000015d40018.bmp
원본 그림의 크기: 가로 784pixel, 세로 158pixel          (19)

where

그림입니다.
원본 그림의 이름: CLP000015d40019.bmp
원본 그림의 크기: 가로 666pixel, 세로 187pixel        (20)

그림입니다.
원본 그림의 이름: CLP000015d4001a.bmp
원본 그림의 크기: 가로 386pixel, 세로 192pixel                     (21)

그림입니다.
원본 그림의 이름: CLP000015d4001b.bmp
원본 그림의 크기: 가로 1072pixel, 세로 377pixel          (22)

On the basis of the above result analysis, the final working mode distribution is obtained by using MATLAB, as shown in Fig. 5.


그림입니다.
원본 그림의 이름: CLP000015d4001c.bmp
원본 그림의 크기: 가로 1023pixel, 세로 869pixel

Fig. 5. PSFB-LLC operating modes distribution with m = 5.


C. Soft-Switching Performance

The secondary rectifier diode in the disconnect mode (DCM) can be achieved in natural shutdown and no reverse recovery loss is incurred. Therefore, the condition of secondary ZCS implementation is whether it works in the DCM or not. According to the current waveform of each mode in Fig. 3, PPxNx and P are critical DCMs, while the other modes are DCMs. Therefore, the secondary rectifier diode can realize ZCS in all modes.

The resonant current is assumed to be capable of completing the junction capacitance charge and discharge and the diode conduction in dead time. Regardless of the mode the converter is in, it always has four switching moments in one cycle, namely, tS13, tS31, tS24, and tS42, respectively indicating the S1-OFF-S3-ON, S3-OFF-S1-ON, S2-OFF-S4-ON, and S4-OFF-S2-ON moments. As shown in Fig. 6, for sets S1 and S3 for the leading leg and S2 and S4 for the lagging leg, the conditions of ZVS realization are as follows:

그림입니다.
원본 그림의 이름: CLP000015d4001d.bmp
원본 그림의 크기: 가로 359pixel, 세로 54pixel        (23)

그림입니다.
원본 그림의 이름: CLP000015d4001e.bmp
원본 그림의 크기: 가로 372pixel, 세로 67pixel       &sp;  (24)

그림입니다.
원본 그림의 이름: CLP000015d4001f.bmp
원본 그림의 크기: 가로 369pixel, 세로 63pixel       (25)

그림입니다.
원본 그림의 이름: CLP000015d40020.bmp
원본 그림의 크기: 가로 385pixel, 세로 61pixel       (26)


그림입니다.
원본 그림의 이름: CLP000015d40021.bmp
원본 그림의 크기: 가로 956pixel, 세로 711pixel

Fig. 6. LLC full-bridge converter primary side equivalent circuit.


According to the symmetry, only Equations (23) and (26) should be satisfied. In a half switching cycle, (23) is the ZVS realization condition of the leading leg, and Equation (26) is the condition of the lagging leg. tS13 is the ending moment of the phase-shift stage, which indicates the end of stage P or O. ir should be no less than im at the end of stage P, and ir should be equal to im at the end of stage O. Therefore, both cases can satisfy the ZVS realization condition of the leading leg. tS42 corresponds to the end of a half switching cycle, which may have four cases, P, O, Ox, and Nx. The analysis of the seven kinds of circuit work modes shows that P and OPO satisfy the ZVS realization conditions of the lagging leg. PPxOx, OPOOx, and OPPxOx all end with Ox, and Lm is in resonance at stage Ox. Given that Lm is usually large, resonant current ir can be almost considered a constant. Thus, these three modes can guarantee the ZVS realization of the leading and lagging legs. PPxOxNx and PPxNx end with Nx, where vm is clamped at –nVo. The resonance is made up of Lr and Cr, and it outputs energy to the secondary side. ir decreases sinusoidal. The critical moment is when ir equals 0, that is,

그림입니다.
원본 그림의 이름: CLP000015d40023.bmp
원본 그림의 크기: 가로 610pixel, 세로 82pixel         (27)

그림입니다.
원본 그림의 이름: CLP000015d40024.bmp
원본 그림의 크기: 가로 795pixel, 세로 74pixel         (28)

As shown in Fig. 7, the distribution area of ZVS can be obtained by MATLAB by combining Equation (27), Equation (28), and the boundary conditions of PPxOxNx and PPxNx. When designing circuit parameters, the converter normalized maximum output power should be within the red line area in Fig. 7 to guarantee ZVS realization in the full power range. According to the trend of the boundary in Fig. 7, ZVS can be realized in the full power range if the converter satisfies the ZVS condition at the minimum phase-shift angle.


그림입니다.
원본 그림의 이름: CLP000015d40022.bmp
원본 그림의 크기: 가로 988pixel, 세로 830pixel

Fig. 7. ZVS range, red line enclosed area.



Ⅲ. HYBRID CONTROL STRATEGY

In this section, the state-plane trajectories in different working modes are analyzed by using the graphical state- plane method, and the state-plane trajectory migration of the load step changes is obtained. When the analysis is combined with the results of the previous time-domain analysis, the DDPSC controller is established. A hybrid control strategy is proposed based on the conventional linear control and the DDPSC. The main idea of the control strategy is that the working state of the converter can be defined as two states depending on the output current change, 그림입니다.
원본 그림의 이름: CLP000004240002.bmp
원본 그림의 크기: 가로 80pixel, 세로 53pixel, namely, transient state and steady state. In the steady state, the converter is controlled by a linear regulator (PI) to eliminate static errors, while in the transient state, the converter is controlled by DDPSC for good transient response performance.

This section introduces these states in detail from three aspects: state-plane trajectory, trajectory migration, and hybrid controller.


A. State-plane Trajectory

The steady and dynamic characteristics of different resonant converters are presented by using the graphical state-plane method in [26] and [27]. Table II lists the state-plane trajectory shapes of the five stages (P, O, Px, Nx, and Ox), and the state-plane trajectories in different working modes are plotted in Fig. 8. The red and blue lines represent half switching cycles. The trajectory changes in a clockwise direction.


TABLE II STAGE TRAJECTORIES

Stage

VEn

Shape

Center

P

1/M 1

Circle

(1/M 1, 0)

O

1/M

Oval

(1/M, 0)

Px

1

Circle

(1, 0)

Nx

1

Circle

(1, 0)

Ox

0

Oval

(0, 0)


Fig. 8. State-plane trajectory of different operating modes. (a) P and OPO. (b) PPxNx and PPxOxNx. (c) PPxOx and OPOOx. (d) OPPxOx.

그림입니다.
원본 그림의 이름: CLP000015d40025.bmp
원본 그림의 크기: 가로 1303pixel, 세로 626pixel

그림입니다.
원본 그림의 이름: CLP000015d40025.bmp
원본 그림의 크기: 가로 1303pixel, 세로 626pixel

(a)

그림입니다.
원본 그림의 이름: CLP000015d40028.bmp
원본 그림의 크기: 가로 1449pixel, 세로 688pixel

그림입니다.
원본 그림의 이름: CLP000015d40028.bmp
원본 그림의 크기: 가로 1449pixel, 세로 688pixel

(b)

그림입니다.
원본 그림의 이름: CLP000015d40029.bmp
원본 그림의 크기: 가로 1457pixel, 세로 614pixel

그림입니다.
원본 그림의 이름: CLP000015d40029.bmp
원본 그림의 크기: 가로 1457pixel, 세로 614pixel

(c)

그림입니다.
원본 그림의 이름: CLP000015d4002a.bmp
원본 그림의 크기: 가로 1066pixel, 세로 703pixel

(d)


B. Trajectory Migration

According to Fig. 5, two kinds of mode migrations exist during the load step change: intra-mode migration and between-modes migration.

Intra-mode migration occurs when the converter remains at the same working mode before and after the load step change. The intra-mode migration trajectory of mode P, which adjusts the energy of the resonator by temporarily adding stage O or stage Px, is shown in Fig. 9 [23]. For mode OPO, the converter can automatically adjust the ratio of stage O to stage P during load changes. When the output power is increased to the critical value given in (15), the converter turns into mode P. The migration trajectory of mode PPxOx is shown in Fig. 10, where stages P and Px are adjusted by modifying the phase-shift angle, and the phase-shift angle increment is derived from the time-domain model. The trajectory migration of other working modes can be obtained by combining the three modes above.


그림입니다.
원본 그림의 이름: CLP000015d4002b.bmp
원본 그림의 크기: 가로 1562pixel, 세로 730pixel

Fig. 9. Trajectory migration process of P mode.


그림입니다.
원본 그림의 이름: CLP000015d4002c.bmp
원본 그림의 크기: 가로 1600pixel, 세로 867pixel

Fig. 10. Trajectory migration process of PPxOx mode.


Between-modes migration occurs when the trajectory shifts from one working mode to another before and after the load step change. Fig. 11 shows the trajectory migration between P and PPxOx. When the output power steps up, the phase-shift angle is increased to 그림입니다.
원본 그림의 이름: CLP000013c80061.bmp
원본 그림의 크기: 가로 39pixel, 세로 35pixel first. Then, the converter goes into the intra-mode migration of mode P. When the output power steps down, the time-domain model is used to reduce the phase-shift angle. When the phase-shift angle is directly decreased to a specified angle, the trajectory passes through two green lines (Px and Ox) and then enters a new steady state. In mode PPxOxNx, stages Ox and Nx are not directly controlled by the phase-shift angle but by the load. Therefore, the migration between PPxOxNx and PPxNx, and PPxOxNx and PPxOx is the same as that of mode PPxOx.


그림입니다.
원본 그림의 이름: CLP000015d4002d.bmp
원본 그림의 크기: 가로 1611pixel, 세로 796pixel

Fig. 11. Trajectory migration process between P and PPxOx.


C. PI-DDPSC Hybrid Controller

In the transient process of load step change, the resonant circuit current and voltage are rapidly brought into steady state by precisely controlling the trajectory of the resonant state variable (ir, vCr), which reduces the dynamic adjustment time. According to the migration analysis, the control of the resonant state variable can be divided into two cases. (1) When 그림입니다.
원본 그림의 이름: CLP000004240003.bmp
원본 그림의 크기: 가로 154pixel, 세로 52pixel, the DDPSC control method is adopted, that is, the phase-shift angle is adjusted directly. (2) When 그림입니다.
원본 그림의 이름: CLP000004240004.bmp
원본 그림의 크기: 가로 162pixel, 세로 48pixel, the SOTC control proposed in [23] is used. After moving into the steady state, the linear controller is used to fine-tune the converter to eliminate static errors. Hence, a hybrid controller based on PI and DDPSC is designed. The structure is shown in Fig. 12.


그림입니다.
원본 그림의 이름: CLP000015d4002f.bmp
원본 그림의 크기: 가로 1459pixel, 세로 863pixel

Fig. 12. PI-DDPSC hybrid controller block diagram.


The main modules in detail:

1) Parameter Preprocessing Module

The output power is calculated from the output voltage vo and the output current io, and then normalized. Gain M is calculated, with the input voltage vin, the output voltage vo, and the transformer turn ratios. The output power, pon, gain M, phase-shift angle 그림입니다.
원본 그림의 이름: CLP000013c80047.bmp
원본 그림의 크기: 가로 45pixel, 세로 49pixel are filtered and stored.

2) State Estimator Module

A threshold load-step change, Ith, is set to trigger the transient process. The output current increment, 그림입니다.
원본 그림의 이름: CLP000004240006.bmp
원본 그림의 크기: 가로 80pixel, 세로 52pixel, is calculated using the new output current and the last output current: 그림입니다.
원본 그림의 이름: CLP000004240005.bmp
원본 그림의 크기: 가로 532pixel, 세로 62pixel. 그림입니다.
원본 그림의 이름: CLP000004240006.bmp
원본 그림의 크기: 가로 80pixel, 세로 52pixel is compared with threshold Ith to determine whether it should enter the transient process flow. If 그림입니다.
원본 그림의 이름: CLP000004240007.bmp
원본 그림의 크기: 가로 218pixel, 세로 56pixel, then the following steps are performed. Otherwise, the steady-state process is maintained using the PI controller.

3) DDPSC Module

The core function of DDPSC is to calculate 그림입니다.
원본 그림의 이름: CLP00002e9029cf.bmp
원본 그림의 크기: 가로 89pixel, 세로 59pixel. It can be calculated by solving the time-domain model. However, this step is complex and difficult to realize in a converter controller. To solve this problem, the relationship between 그림입니다.
원본 그림의 이름: CLP000013c80049.bmp
원본 그림의 크기: 가로 45pixel, 세로 49pixel, M, and pon is fitted based on the numerical solution of the time-domain model, and the fitting result is as follows:

그림입니다.
원본 그림의 이름: CLP000015d40030.bmp
원본 그림의 크기: 가로 930pixel, 세로 267pixel         (29)

where a00, a01, …, a30 are the coefficients calculated by MATLAB based on the numerical solution of the time-domain model. They can be calculated when the resonant circuit design is completed.

When M is constant, the relationship between 그림입니다.
원본 그림의 이름: CLP000013c8004a.bmp
원본 그림의 크기: 가로 45pixel, 세로 49pixel and pon is monotonic. The unique 그림입니다.
원본 그림의 이름: CLP000013c8004b.bmp
원본 그림의 크기: 가로 45pixel, 세로 49pixel can be determined by M and pon. When the load changes, the voltage gain can be considered a constant value because output capacitance Co is generally large. The increment of the phase-shift angle can be calculated from the increment of the output power, as shown in Equation (30).

그림입니다.
원본 그림의 이름: CLP000015d40032.bmp
원본 그림의 크기: 가로 1013pixel, 세로 96pixel      (30)

where pon_1 is the output power before the load step change, and pon_2 is the output power after the load step change. pon_1 and pon_2 can be calculated by Equation (31).

그림입니다.
원본 그림의 이름: CLP000015d40033.bmp
원본 그림의 크기: 가로 429pixel, 세로 208pixel   (31)

To verify the accuracy of the fitting formula, the simulation circuit is built by simulation software Saber, with consideration of the actual parameters of the system converter power MOSFET switches and inductors. The simulation and fitting results are compared. The comparison results are shown in Fig. 13. The figure shows that the fitting results are consistent with the simulation results.


그림입니다.
원본 그림의 이름: CLP000015d40031.bmp
원본 그림의 크기: 가로 1300pixel, 세로 801pixel

Fig. 13. Comparison of the simulation results and the fitting formula calculation.


The second function is based on the value of 그림입니다.
원본 그림의 이름: CLP00002e9029cf.bmp
원본 그림의 크기: 가로 89pixel, 세로 59pixel to determine whether OSTC should be executed. If 그림입니다.
원본 그림의 이름: CLP000004240008.bmp
원본 그림의 크기: 가로 286pixel, 세로 62pixel, then the phase angle will be directly adjusted. If 그림입니다.
원본 그림의 이름: CLP000004240009.bmp
원본 그림의 크기: 가로 311pixel, 세로 59pixel, 그림입니다.
원본 그림의 이름: CLP00000424000a.bmp
원본 그림의 크기: 가로 150pixel, 세로 47pixel is set at first, and then in the next switching cycle, the intra-mode adjustment will be performed by the SOTC module.

4) SOTC Module

When the load steps up, according to the derivation result in [23], the length of O stage is

그림입니다.
원본 그림의 이름: CLP000015d40034.bmp
원본 그림의 크기: 가로 613pixel, 세로 163pixel    (32)

When the load steps down, the duration of the Px stage is

그림입니다.
원본 그림의 이름: CLP000015d40035.bmp
원본 그림의 크기: 가로 583pixel, 세로 197pixel     (33)

where ILL is the light load current, IHL is the heavy load current, and T is one switching cycle.

In this module, the variable frequency control method can be employed to extend the output voltage range. When the phase shift reaches its maximum value, the converter reaches the maximum gain. Although the transient output power can be adjusted by the SOTC method, the PI controller cannot adjust the output voltage by shifting the phase angle. In this case, increasing the variable frequency control is a good way to extend the gain range of the converter.

To reveal the superiority of the proposed PI-PPDSC clearly based on simulated dynamic responses, the stateplane trajectories of PI and PI-PPDSC are compared, as shown in Figs. 14 and 15. The dynamic responses trajectories with conventional linear compensators are given in Figs. 14(a), 14(b), 15(a), and 15(b). Figs. 14(a) and 15(a) show the response trajectories of the PI controller with high bandwidth and a small phase margin. The response is fast, but some dynamic oscillations exist. In addition, Figs. 14(b) and 15(b) show the dynamic response of the PI controller with a slightly lower bandwidth and larger phase margin. The oscillation is eliminated, but the response is slightly slower. From the state plane, in both linear PI controller designs, many trajectory loci exist when jumping from the small light-load circle to the large heavy-load circle or from the large heavy-load circle to the small light-load circle. With the proposed PI-DDPSC, Figs. 14(c) and 15(c) show that almost no dynamic oscillation exists. All state variables (iLr and vCr) settle to the new steady state quickly. After two pulse jumps, the dynamic trajectory is quite clean. The linear PI takes less effort to converge to the new steady state.


Fig. 14. Load step-up response of (a) PI controller with high bandwidth and small phase margin, (b) PI controller with low bandwidth and large phase margin, (c) PI-DDPSC.

그림입니다.
원본 그림의 이름: 1.PNG
원본 그림의 크기: 가로 585pixel, 세로 663pixel

(a)

그림입니다.
원본 그림의 이름: 1.PNG
원본 그림의 크기: 가로 580pixel, 세로 667pixel

(b)

그림입니다.
원본 그림의 이름: 1.PNG
원본 그림의 크기: 가로 482pixel, 세로 645pixel

(c)


Fig. 15. Load step-down response of (a) PI controller with high bandwidth and small phase margin, (b) PI controller with low bandwidth and large phase margin, (c) PI-DDPSC.

그림입니다.
원본 그림의 이름: 0.PNG
원본 그림의 크기: 가로 1525pixel, 세로 666pixel

(a)

그림입니다.
원본 그림의 이름: 0 - 복사본.PNG
원본 그림의 크기: 가로 1525pixel, 세로 666pixel

(b)

그림입니다.
원본 그림의 이름: 0 - 복사본 (2).PNG
원본 그림의 크기: 가로 1525pixel, 세로 666pixel

(c)



Ⅳ. EXPERIMENT AND ANALYSIS

To verify the effectiveness of the proposed control method, a 3 kW prototype is built with the components listed in Table III. Fig. 16 shows the prototype converter.


TABLE III LIST OF PROTOTYPE CIRCUIT COMPONENTS

Main switches (S1S4)

IPW90R120C3

Rectifier diodes (Dr1Dr4)

IDT10S60C

Transformer

Core- NCD E65, Turns Np = 16, Ns = 16, Lm = 64.4 그림입니다.
원본 그림의 이름: CLP000013c8006d.bmp
원본 그림의 크기: 가로 31pixel, 세로 46pixelH, Llk = 1.9 그림입니다.
원본 그림의 이름: CLP000013c8006c.bmp
원본 그림의 크기: 가로 31pixel, 세로 46pixelH

Resonant capacitor (Cr)

110 nF/750 Vac

Resonance inductance (Lr)

12.7 그림입니다.
원본 그림의 이름: CLP000013c8006b.bmp
원본 그림의 크기: 가로 31pixel, 세로 46pixelH

Output capacitor (Co)

100 그림입니다.
원본 그림의 이름: CLP000013c8006e.bmp
원본 그림의 크기: 가로 31pixel, 세로 46pixelF/450 V

Controller

TMS320F28335

ADC chip

AD7606-4

PI proportional parameter

0.085

PI integral parameter

675


그림입니다.
원본 그림의 이름: CLP000015d40038.bmp
원본 그림의 크기: 가로 1289pixel, 세로 823pixel

Fig. 16. Hardware prototype of the PSFB-LLC converter.


The prototype circuit has the following specifications:

⋅ Input voltage range: Vinmin = 360 V, Vinmax = 500 V;

⋅ Output voltage: Vo = 360 V;

⋅ Output current: Iomax = 8 A;

⋅ Resonant frequency: fr = 126 kHz;

⋅ Switching frequency: fs = 126 kHz.

The resonant tank of PSFB-LLC is designed following the flow chart shown in Fig. 17.


그림입니다.
원본 그림의 이름: CLP000015d4003c.bmp
원본 그림의 크기: 가로 610pixel, 세로 902pixel

Fig. 17. Design procedure for PSFB-LLC resonant converter.


First, transformer turns ratio is calculated to ensure the converter can achieve the maximum and minimum gains at extreme input voltage conditions, and the transformer turns ratio should satisfy the following condition:

그림입니다.
원본 그림의 이름: CLP000015d40039.bmp
원본 그림의 크기: 가로 421pixel, 세로 161pixel        (34)

To facilitate the transformer design, n = 1. Then, the minimum and maximum gains of the LLC resonant converter can be calculated by

그림입니다.
원본 그림의 이름: CLP000015d4003a.bmp
원본 그림의 크기: 가로 479pixel, 세로 133pixel      (35)

그림입니다.
원본 그림의 이름: CLP000015d4003b.bmp
원본 그림의 크기: 가로 362pixel, 세로 149pixel   (36)

Second, a magnetizing inductor is selected. A higher Lm improves the efficiency because of the low-circulating current [28]. However, a high Lm may cause the LLC resonant converter to lose the ZVS. To ensure ZVS operation, Lmmax must satisfy

그림입니다.
원본 그림의 이름: CLP000015d4003d.bmp
원본 그림의 크기: 가로 565pixel, 세로 185pixel    (37)

Apparently, the magnetizing inductor should be designed based on the tradeoff between the switching and conduction losses. With the dead time, td = 100 ns, and Cds of IPW90R120C3, Lmmax can be calculated according to Equation (37), and thus Lmmax is 124 그림입니다.
원본 그림의 이름: CLP00000424000b.bmp
원본 그림의 크기: 가로 82pixel, 세로 62pixel. According to Equation (38), the product of inductor ratio 그림입니다.
원본 그림의 이름: CLP00001b6c001a.bmp
원본 그림의 크기: 가로 43pixel, 세로 52pixel and pon is only determined by the magnetizing inductor.

그림입니다.
원본 그림의 이름: CLP000015d4003e.bmp
원본 그림의 크기: 가로 785pixel, 세로 264pixel    (38)

where

그림입니다.
원본 그림의 이름: CLP000015d4003f.bmp
원본 그림의 크기: 가로 344pixel, 세로 155pixel    (39)

그림입니다.
원본 그림의 이름: CLP000015d40040.bmp
원본 그림의 크기: 가로 490pixel, 세로 162pixel       (40)

According to the first cycle in the flowchart (Fig. 17), with design parameters 그림입니다.
원본 그림의 이름: CLP00000424000c.bmp
원본 그림의 크기: 가로 326pixel, 세로 59pixel, Mmin = 0.72, Mmax = 1, and fr = 126 kHz, the value of Lm is designed as 64.4 그림입니다.
원본 그림의 이름: CLP00002e900001.bmp
원본 그림의 크기: 가로 82pixel, 세로 62pixel. The inductor radio range is 2 to 6 [29]. Then, through the second cycle in Fig. 17, the inductor ratio is selected as 4.4. Finally, Lr and Cr are calculated according to Equations (41) to (43).

그림입니다.
원본 그림의 이름: CLP000015d40041.bmp
원본 그림의 크기: 가로 368pixel, 세로 172pixel   (41)

그림입니다.
원본 그림의 이름: CLP000015d40042.bmp
원본 그림의 크기: 가로 371pixel, 세로 172pixel   (42)

그림입니다.
원본 그림의 이름: CLP000015d40043.bmp
원본 그림의 크기: 가로 274pixel, 세로 160pixel       (43)

The hybrid control method is digitally implemented using a TMS320F28335. Fig. 18 shows the control flowchart implemented in the digital controller. PI controller is used in the proposed control method and the comparative test. The proportional and integral gain parameters of the PI controller are calculated according to the Ziegler–Nichols tuning method [30] and are summarized in Table III.


그림입니다.
원본 그림의 이름: CLP000015d40044.bmp
원본 그림의 크기: 가로 862pixel, 세로 885pixel

Fig. 18. Control flowchart of one PI-DDPSC control cycle.


To verify the soft-switching characteristics of the PSFB- LLC converter, switching device waveforms are measured at different loads. Figs. 10 and 11 show the ZVS waveforms of leading leg S3 and lagging leg S4. The switches are successfully turned on with ZVS under full load and 10% full-load conditions. Figs. 12 and 13 show the measured waveforms of the rectifier diodes Dr1 in which the rectifier diodes current, iDr1, and voltage, vDr1, are shown. The rectifier currents drop to zero before the rectifier diodes turn off, thereby achieving ZCS.

To verify the dynamic response capability of PI-DDPSC, the control effects of the PI and PI-DDPSC controllers when the load step changes are compared further. The same control parameters shown in Table III are adopted in the PI and PI-DDPSC controllers. The load step changes are tested for two cases with input voltages 500 and 360 V, and four sets of experimental waveforms are obtained, as shown in Figs. 23 to 26. The former two groups of experiments compare the PI and PI-DDPSC controllers. The input voltage is 500 V, and the output voltage is 360 V. As shown in Figs. 23 and 24, the circuit works in mode PPxOx, 그림입니다.
원본 그림의 이름: CLP000004240003.bmp
원본 그림의 크기: 가로 154pixel, 세로 52pixel. The latter two groups of experimental circuits work in mode P, the input and output voltages are both 360 V. As shown in Figs. 25 and 26, 그림입니다.
원본 그림의 이름: CLP00000424000d.bmp
원본 그림의 크기: 가로 130pixel, 세로 49pixel, and the SOTC module in the controller plays a major role in the transient response.

The dynamic adjustment process of the linear compensator is shown in Fig. 23(a). According to Equation (28), the phase-shift angle of the drive signal increases by approximately 0.08그림입니다.
원본 그림의 이름: CLP000013c80069.bmp
원본 그림의 크기: 가로 39pixel, 세로 35pixel after the DDPSC controller is involved. The load increases and ir quickly stabilizes when the phase-shift angle is directly adjusted. According to Fig. 23 (b), the output voltage has a small overshoot and settling time. In the expansion waveform at the instantaneous moment, as shown in Fig. 23(c), ir increases in the original sinusoidal trajectory in stage P of the phase-shift angle increasing switching period and enters a new trajectory in the subsequent Px and Ox stages.


Fig. 19. Achievement waveforms of ZVS at full load with RL = 45그림입니다.
원본 그림의 이름: CLP00000424000e.bmp
원본 그림의 크기: 가로 50pixel, 세로 43pixel: (a) when Vin = 500 V, (b) when Vin = 500 V, (c) when Vin = 360, (d) when Vin = 360 V.

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(d)


Fig. 20. Achievement waveforms of ZVS at 10% full load with RL = 450 그림입니다.
원본 그림의 이름: CLP00000424000e.bmp
원본 그림의 크기: 가로 50pixel, 세로 43pixel: (a) when Vin = 500 V, (b) when Vin = 500 V, (c) when Vin = 360, (d) when Vin = 360 V.

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Fig. 21. Measured waveforms of the output rectifier diodes at full load with input voltage of (a) 500 V, (b) 360 V.

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Fig. 22. Measured waveforms of the output rectifier diodes at 10% full load with input voltage of (a) 500 V, (b) 360 V.

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Fig. 23. Transient response to the step-up change of the output current from 4A to 8A with Vin = 500 V: (a) Voltage dynamic response with a PI compensator. (b) Improved dynamic response with PI-DDPSC. (c) Detailed waveform of the PI-DDPSC at the load step-up moment.

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(c)


Fig. 24. Transient response to the step-down change of the output current from 8A to 4A with Vin = 500 V: (a) Voltage dynamic response with a PI compensator. (b) Improved dynamic response with PI-DDPSC. (c) Detailed waveform of the PI-DDPSC at the load step-down moment.

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Fig. 25. Transient response to the step-up change of the output current from 4A to 8A with Vin = 360 V: (a) Voltage dynamic response with SOTC; (b) Zoom-in view at the load step-up moment.

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Fig. 26. Transient response to the step-down change of the output current from 8A to 4A with Vin = 360 V: (a) Voltage dynamic response with SOTC. (b) Zoom-in view at the load step-down moment.

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(b)


The transient waveform with load steps down is shown in Fig. 24. The transient response when using the PI compensator is shown in Fig. 24(a). Fig. 24(b) shows that DDPSC significantly improves the dynamic performance, reducing the overshoot to 100 mV. Fig. 24(c) illustrates that within DDPSC, the phase-shift angle decreases by approximately 0.08그림입니다.
원본 그림의 이름: CLP000013c8006a.bmp
원본 그림의 크기: 가로 39pixel, 세로 35pixel at the step-down moment. After the phase-shift angle decreases, the ir peak current becomes smaller, followed by the two transitional stages Px and Ox. Then, the resonant inductor current, ir, can settle to the light-load steady state within one switching cycle. Finally, the static errors are gradually eliminated by the PI regulator.

When the input voltage is 360 V, the transient waveform under increasing and decreasing output loads are given as shown in Fig. 25 and 26, respectively. The circuit works in mode P, and ir is a sine wave. When the load steps up, the drive waveform is adjusted according to the change in output current, and the switching frequency is increased temporarily. After stage P, stage O is added, as shown in Fig. 25 (b), and the resonant energy increases. When the load steps down, stage P is shortened and stage Px appears. Thus, the resonance energy decreases and ir is deduced in stage Px, as shown in Fig. 26. Figs. 25 and 26 also show that the output load step influences the output voltage, and a voltage deviation exists between the steady value and the set value before and after the load change. Now, when the current gain equals 1, the output voltage cannot maintain a fixed value under different loads due to the conduction losses in the actual circuit. Therefore, the PSFB-LLC is only applied to the buck mode, and when the input voltage is close to the output voltage, the voltage is not fixed even if the current can be adjusted according to the load.



Ⅴ. CONCLUSIONS

A hybrid control strategy for the PSFB-LLC resonant converter is proposed in this paper. The strategy improves the response performance when load changes. The time-domain model of the PSFB-LLC converter is established, the boundary conditions of the primary ZVS and the secondary ZCS are analyzed, and the realization range of the soft switch is given. An analysis of the state-plane migration trajectory leads to the use of DSP to implement the PI-DDPSC hybrid controller, and a 3 kW prototype is built. Through the experimental results, the following conclusions can be drawn:

(1) Using the PI-DDPSC controller can enable the PSFB-LLC converter to achieve a constant voltage output when the gain is less than 1, and its dynamic performance is improved compared with that using the PI controller.

(2) The PSFB-LLC converter can achieve a primary ZVS and a secondary ZCS in the full range of power output.

(3) The PI-DDPSC controller realized in this study is easy to extend with a frequency control module, and its structure is simple and flexible.



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Bing Guo was born in Hebei, China, in 1990. He received his B.S. degree in Electronic Information Engineering from the Shijiazhang Tiedao University, Hebei, China, in 2011, and his M.S. degree in Control Science and Engineering from Beijing University of Technology, Beijing, China, in 2014. He is currently studying for a doctor's degree in power electronics and geophysical prospecting at Beijing University of Technology.


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Yiming Zhang was born in Hubei, China, in 1964. He received his B.S. degree from the School of Electronic, Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China, in 1988; and his M.S. degree from the School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin, China, in 1992. From 2000 to 2007, he was a senior researcher in the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China. Since 2008, he has been a professor in the College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, China. His current research interests include intelligent power management, motor speed control, servo drivers and motor energy conservation.


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Jialin Zhang was born in Hebei, China, in 1990. He received his B.S. degree from the School of Electrical Engineering, Hebei University of Science and Technology, Hebei, China, in 2012; and his M.S. degree from the College of Information Science and Engineering, Northeastern University, Liaoning, China, in 2014. He is currently working towards his Ph.D. degree in the Faculty of Information, Beijing University of Technology, Beijing, China. His current research interests include control of pulse width modulation rectifier connected with permanent sychronous generator and its application in geophysics.


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Junxia Gao was born in Tianjin, China, in 1978. She received her B.S. degree from the College Information Engineering, Taiyuan University of Technology, Taiyuan, China, in 2001; and her M.S. degree from the Faculty of Information, Beijing University of Technology, Beijing, China, in 2004. Since 2004, she has been a senior lecturer in the Faculty of Information, Beijing University of Technology. Her current research interests include power electronics, electromagnetic fields and nondestructive examination.