사각형입니다.

https://doi.org/10.6113/JPE.2018.18.3.863

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Shunt Active Filter for Multi-Level Inverters Using DDSRF with State Delay Controller


C. R. Rajesh and S. P. Umayal*


Department of Electrical and Electronics Engineering, CSI Institute of Technology, Thovalai, India

*Department of Electrical and Electronics Engineering, Muthayammal Engineering College, Namakkal, India



Abstract

The traditional power control theories for the harmonic reduction methods in multilevel inverters are found to be unreliable under unbalanced load conditions. The unreliability in harmonic mitigation is caused by voltage fluctuations, non-linear loads, the use of power switches, etc. In general, the harmonics are reduced by filters. However, such devices are an expensive way to provide a smooth and fast response to secure power systems during dynamic conditions. Hence, the Decoupled Double Synchronous Reference Frame (DDSRF) theory combined with a State Delay Controller (SDC) is proposed to achieve a harmonic reduction in power systems. The DDSRF produces a sinusoidal harmonic that is the opposite of the load harmonic. Then, it injects this harmonic into power systems, which reduces the effect of harmonics. The SDC is used to reduce the delay between the compensation time for power injection and the generation of a reference signal. The proposed technique has been simulated using MATLAB and its reliability has been verified experimentally under unbalanced conditions.


Key words: Cascaded multi-level inverter, Decoupled double synchronous reference frame, Instantaneous PQ theory, Positive, Negative and zero sequence components, Shunt active filter, State delay controller


Manuscript received Jul. 22, 2017; accepted Jan. 8, 2018

Recommended for publication by Associate Editor Kyo-Beum Lee.

Corresponding Author: crrajesh99@gmail.com Tel: +919443559702, CSI Institute of Technology

*Dept. of Electr. and Electron. Eng., Muthayammal Eng. College, India



Ⅰ. INTRODUCTION

Recently, power quality problems have been aggravated due to the introduction of power electronic equipment in industrial and domestic products. Since power electronic circuits exhibit non-linear characteristics, they induce both harmonics and distortions of the voltage and current in power system networks. This can result in a poor power factor, active and reactive power problems, electromagnetic interference, poor efficiency, heating of the equipment and conductors, and increased line losses. These problems affect the longevity of power system components. To suppress the harmonic components in power systems, various filtering techniques have been widely used in recent years [1], [2]. These filters can be active or passive. The active filters include the series active and Shunt Active Filters (SAF). Meanwhile, the passive filters are based on components used for filtering.

Series filters provide a high impedance to the harmonic currents. However, they allow the fundamental frequency of the current to reach the supply voltage. Shunt active filters provide a low impedance path for harmonic currents, and divert harmonics to the ground [3]. Shunt filters are less expensive when compared to series filters since they do not carry the full load current. Passive filters are comparatively bulky and are not economical at high power ratings. Hence, there is a need for precise fine tuning to reduce harmonic currents over a wide range of the frequency spectrum. The Fourier transformation method is widely employed to solve frequency domain characteristics [4]. Many researchers and industrialists have implemented shunt active power filters to compensate for power system harmonics by injecting the required component to retain the balanced voltage and current profile [5]-[9]. In the extraction of harmonics from an unbalanced system with a non-linear load, the reference signal plays a significant role. A targeted output is achieved by controlling the DC link voltage with suitable switching pulses to the inverter circuit.

Three-phase power systems have distorted power content and harmonics. The Synchronous Reference Frame (SRF) theory was implemented by a Phase Locked Loop (PLL) and its performance was unsatisfactory under unbalanced and severely distorted conditions [10], [11]. Hence, the authors of this paper proposed a decoupled double synchronous reference frame theory, to detect the positive, negative and zero sequence components of the power consumed by non-linear loads and sources [12]. This theory overcomes the above mentioned drawbacks and gives an accurate estimation of all the sequences of components without a reduction of the bandwidth. The rotating double synchronous reference frame generates the signals of dq1 and dq2 from αβ and they are translated into β, which is equal to zero.

In addition, the harmonic losses are estimated under an unbalanced load to generate a reference signal for injecting adequate compensating power into the grid. To warrant a precise compensation from unbalanced source and load distortions, a discrete PID controller is used to provide the feedback of the decoupling block. Thus, an exact gating signal has been provided to a Five Level Cascaded – Multi Level Inverter (FLC-MLI) circuit with feedback.



Ⅱ. RE-EXAMINATION OF THE INSTANTANEOUS POWER THEORY AND UNBALANCED CONDITIONS


A. Unbalanced Source and Power

In three-phase unsymmetrical power systems, equations that represent the zero, positive and negative sequences of the components are:

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where:

y - cos

ωt - angular frequency

Vas, Vbs, Vcs - supply voltages of phases a, b, c

V1, V2, V0 - positive, negative and zero sequence voltages

φ1, φ2, φ0 - positive, negative and zero sequence angles

V0, V1 and V2 are the peak values of the unsymmetrical voltage components, which can be simplified as:

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Similarly, the unsymmetrical source current component is represented as:

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Vs – supply voltage

Is - supply current

Va1, Va2, Va0 – positive, negative and zero sequence voltages of phase ‘a’

Similarly, Vb1, Vb2, Vb0 and Vc1, Vc2, Vc0 are the sequence voltages of phases ‘b’ and ‘c’

Ias, Ibs, Ics – supply current of phases a, b, c

Ia1, Ia2, Ia0 – positive, negative and zero sequence currents of phase ‘a’

Similarly, Ib1, Ib2, Ib0 and Ic1, Ic2, Ic0 are the sequence currents of phase ‘b’ and ‘c’

In general, the apparent power of the source is:

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where: 

Ssapparent power of the source

Ps - real power of the source

Qs - reactive power of the source

According to the instantaneous PQ theory from Fig.1, the power balancing equation is:

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The subscripts 1, 2 and 0 indicate the positive, negative and zero sequence components. Ss120 is the apparent power of the supply source connected in the non-linear load condition. Sl120 is the total power consumed by the non-linear load, and Sf20 is the total power injected by the shunt active power filter under source and non-linear loads. Hence, the effective value of the unbalanced power is determined on both sides of the source and load. Therefore, the SAF required to inject the grid power is determined by:

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where, Sh120 is the harmonic power loss component due to the non-linear load. ps120and qs120 are the active and reactive powers of the load consumed from the source. ph120(t) and qh120(t) are the real and reactive power losses of the load harmonics component.


B. Fundamental Transform Theory

The proposed method of a DDSRF based instantaneous PQ theory with a state delay control technique for the five level cascaded multilevel inverter configurations in a SAF is given in Fig. 1.


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Fig. 1. Proposed DDSRF-PQ with SDC for a FLC-MLI SAF.


The proposed DDSRF theory transforms an unbalanced three-phase power abc into αβ0 using Clark’s transformation theory.

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where:

Vαβ0, Iαβ0 – Clark’s transformation voltage and current of the alpha, beta and zero components.

The αβ origination describes the instantaneous voltage vector by considering the positive sequence reference. It can be obtained by neglecting the zero-sequence component of the voltage vector in αβ0.

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From Equ. (4), using the instantaneous power theory, the real and imaginary power (pq) of the stationary reference is obtained as follows:

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The resultant voltage in the αβ reference frame is determined from:

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Ⅲ. DDSRF POWER THEORY


A. Decoupled Double SRF Theory in PQ Calculation

The angular frequency of the rotating coordinate system is same as the frequency of the voltage vector in the stationary reference frame. The state of the decoupled double synchronous rotating reference frame is derived from a Park’s transformation by separating the positive and negative sequence components. The transformed dq12 is given by:

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From Equ. 13a and Equ. 13b, it can be concluded that:

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Equ. 16 and Equ. 17 represent the positive and negative sequences from the Park’s transformation. By substituting the decoupled voltage and current values obtained from the Park’s transformation, the following instantaneous PQ theory equations are obtained:

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The reference signal generated from the decoupled voltage and current is given by:

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where:

Vd1, Vd2 - direct axis voltages for the positive and negative sequence components

Vq1, Vq2 - quadrature axis voltages for the positive and negative sequence components

The positive sequence component in the q axis contains oscillations. To reduce these oscillations, a digital controller is implemented by providing the feedback angular frequency in terms of ‘θ’ angular error for the decoupling mechanism. The main advantage of the DDSRF when compared to the traditional SRF-PLL is that there is no need to limit the bandwidth of the PLL to cancel out higher order oscillations [13], [14], [16]-[18]. A Low Pass Filter (LPF) has been implemented to suppress the higher order oscillations in the signal.


B. State Delay Controller

There is a phase delay in the LPF output for producing the signal, due to the unbalanced condition of the operation. To eliminate the phase delay error, fine tuning is required in the entire system [15], [19].

The pre-state determination method, which is called a state delay controller (SDC), was introduced from the current state PQ calculations as shown in Fig. 2. In addition, Equ. (20) explains the procedure for the delay calculations.


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Fig. 2. State Delay Controller (SDC).


The pre-state time is considered as (k-1) and the current state is considered as (k). The next sample signal time is expressed as the (k+1) state as shown in Fig. 3.


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Fig. 3. New state calculation signal diagram.


The following equation is used to calculate the next-state:

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Current state : 그림입니다.
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where, 그림입니다.
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The error or delay time of the new state (k+1) is determined by the average of the pre-state sample (k-1) when compared to the reference (k-1)* delay, the current state sample (k) and the reference (k)* delay. The voltage and current profile of the positive and negative sequence is calculated, and these values are used to cancel out the signal delay error from the reference to the SAF output.



Ⅳ. EXPERIMENTAL RESULTS AND DISCUSSIONS

The proposed DDSRF was simulated using MATLAB/ Simulink and was found to be reliable under unbalanced condition.

From Figs. 4-5, it is inferred that an effective ruling method is required to change the non-linear character of the source and the load.


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Fig. 4. Three-phase source waveform before the compensation voltage of phase ‘abc’.


Fig. 5. Three Source current-waveform before compensation. (a) Phase ‘a’ current. (b) Phase ‘b’ current. (c) Phase ‘c’ current.

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(a)

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(b)

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(c)


To validate the proposed SAF algorithm a hardware prototype was built using the five level cascaded multi-level inverter structure. The unbalanced load consists of a three-phase diode rectifier circuit and has a Total Harmonic Distortion (THD) of 26.40% without the SAF as shown in Fig. 6.


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Fig. 6. Current spectrum and harmonics before compensation.


The load current and source current with voltage components were shown in Figs. 7-10. Using the DDSRF with the time delay controller technique, the value of the THD was reduced to 1.62%.


Fig. 7. Three-phase load current phase with the SAF compensation. (a) Current of phase ‘a.’ (b) Current of phase ‘b.’ (c) Current of phase ‘c’.

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(c)


Fig. 8. Unbalanced load compensation performance with the SAF of phase ‘a.’ (a) Load voltage. (b) Load current. (c) Injected current from the SAF. (d) FLC-MLI output voltage.

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(d)


Fig. 9. Three-phase load and with the FLC-MLI based SAF compensation under transient operation at t = 0.04s. (a) Source voltage. (b) Source current. (c) Injected current from the SAF. (d) FLC-MLI output voltage.

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(d)


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Fig. 10. THD spectrum of the load current after compensation.


Figs. 4-10 show simulated diagrams of the SAF. The performances are compared with an unbalanced load both with and without the SAF.

Figs. 11-13 show unbalanced three phase source voltage and current profiles with the current harmonics THD of phase ‘a.’


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Fig. 11. Unbalanced three-phase source voltage and current of phase ‘abc.’


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Fig. 12. Three-phase source current of phase ‘abc.’


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Fig. 13. Source current harmonics spectrum of phase ‘a.’


The magnitude of the phase and line voltages of an unbalanced load are measured and tabulated in Fig.14. The load current THD is at its minimum (24.785%) in phase ‘c’ and at its maximum (26.143%) in phase ‘a’ without the injection of compensation current in the PCC or without the connection of the SAF. In the unbalanced load condition, the maximum values of the P and Q components are 410.22W and 127.43W, respectively. Under the same conditions, the minimum values of the P and Q components are 389.23W and 119.66W, respectively. The current waveform is distorted and it consumed more reactive power. In order to reduce the harmonics in an unbalanced source and load, compensation power is injected at the junction of the Point of Common Coupling (PCC).


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Fig. 14. Three-phase load (L-L) and phase values without the SAF.


Fig. 14 and Fig. 17 show numerical values of the voltage, current, active power, reactive power, apparent power, voltage THD and current THD with and without the SAF. These values were obtained from a power quality analyzer.

From Figs. 15-17, it is evident that the harmonic components are considerably reduced by using the DDSRF algorithm with the time delay prediction of the dq1 and dq2 components of the positive and negative sequence PQ powers consumed by the unbalanced load. The harmonics are reduced to 1.425% in phase ‘c’, which is less than the standard value recommended by IEEE. Fig. 16.(a) shows the load voltage and load current before compensation, compensation current and voltage of the SAF under transient conditions at 84ms. The SAF achieves unbalanced load operation in the transient operating condition. The SAF is tested in the transient condition at 84ms, and the results are shown in Figs. 16(a)-17.


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Fig. 15. Three-phase load currents of phases a, b, c and the harmonics spectrum of the phase ‘a’ load current (with the SAF compensation).


Fig. 16. The load voltage and load current before compensation. (a) Load voltage and current, FLC-MLI based SAF compensation current and voltage under transient operating conditions at 84ms. (b) Expanded view at 84ms.

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(b)


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Fig. 17. Three-phase load L-L and phase values with SAF injected at 84ms.


It is observed from Fig. 16 and Fig. 17 that the oscillations in the current waveform are cancelled out when the SAF is connected at 84ms. At this instant, the THD component of the load current is 2.11% and the load voltage is 3.09%. With the SAF, the power consumption is drastically reduced in the proposed system when compared to the unbalanced state operation without the SAF.

An experimental setup of the shunt active filter for a multi-level inverter is shown in Fig 18. The three phase source voltages and dc-link voltages are sensed by a Hall effect voltage sensor (LV25-P), and the three phase source current, load current and filter current are sensed by a Hall effect current sensor (LA25-P), along with three iron core inductors (5mh/15A) that are used as filters. The switching signals for the Insulated-Gate Bipolar Transistors (IGBT- FGA40N120) are derived from the SRF theory. A driver circuit (TLP250IC) is used to drive the Pulse Width Modulation (PWM) pulses to the inverter. For the isolation of the inverter output voltage from the power circuit of the SAF, six toroidal core transformers are used in the hardware setup.


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Fig. 18. Experimental setup.


The SRF algorithm has been implemented using a Spartan 6 Field-Programmable Gate Array (FPGA) processor. FPGA technology is suitable for a wider range of applications. The Spartan 6 FPGA controller generates and controls the PWM pulses for the inverter [20]. The FPGA architecture is designed on the basis of the control algorithm. The output results are displayed on a CRO/Power quality analyzer to view the voltage and current waveforms.



Ⅴ. CONCLUSION

The DDSRF mathematical models for a cascaded H-bridge five level multilevel inverter have been simulated using MATLAB. The unbalanced condition of the DDSRF with a state delay controller in the instantaneous PQ theory was successfully analyzed. The delay time from the current state sampling time to the next state has effectively increased the speed of the reference signal generation. The transient state operation of the FLC-MLI based SAF was tested under different conditions. It performed satisfactorily under normal operation with a quick frequency response. In addition, it is proved to be the most reliable method. In the proposed method, the maximum value of % THD of voltage and % THD of current are 2.823 and 2.065, respectively. These values are lower than the IEEE standard values.



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C. R. Rajesh was born in Kanyakumari, India. He received his Bachelor of Engineering degree in Electrical and Electronics Engineering from Kuvempu University, Karnataka, India, in 1998; and his Master of Engineering degree in Power Electronics and Drives from Sathyabama University (Sathyabama Institute of Science and Technology), Chennai, India, in 2005. He is presently working towards his Ph.D. degree at Anna University, Chennai, India. Since 1999 he has been working as an Assistant Professor at the CSI Institute of Technology, Thovalai, India. His current research interests include multilevel inverters, shunt active filters, power electronics in renewable energy systems and FACTs devices.


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S. P. Umayal was born in Chennai India. She received her Bachelor of Engineering  degree in Electrical and Electronics Eng. and Master of Engineering degree in Power Systems from Thiagarajar college of Engineering, Madurai, India, in 1990 and  1999, respectively. She received her Ph.D. degree in Electrical Engineering from Anna University, Chennai, India, in 2008. In 1996 she joined Sethu Institute of Technology, Virudhunagar, India, as a Lecturer in the Department of Electrical and Electronics Engineering, where she was an Assistant Professor from 2001 to 2007, and Professor & Head of the Department from 2008 to 2013. She is presently working as Professor & Dean at Muthayammal Engineering College, Namakkal, India. Her current research interests include intelligent control techniques, power quality monitoring, power electronic converters and AC drives. She has published more than 20 technical papers in national and international journals.