https://doi.org/10.6113/JPE.2019.19.5.1074
ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718
Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources
Tarmizi Tarmizi*, Soib Taib**, and M. K. Mat Desa†
*Department of Electrical Engineering, Faculty of Engineering, Syiah Kuala University, Banda Aceh, Indonesia
†,**School of Electrical and Electronics Engineering, USM Engineering Campus, Penang, Malaysia
Abstract
This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W (48.3W) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load (R=54W dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.
Key words: Asymmetric source, Degree switching, Generation level, H-bridge, Multilevel inverter
Manuscript received Nov. 6, 2018; accepted Apr. 19, 2019
Recommended for publication by Associate Editor S. Padmanaban.
†Corresponding Author: khairunaz@usm.my Tel: +6045995873, USM Engineering Campus
*Dept. of Electr. Eng., Faculty of Eng., Syiah Kuala Univ., Indonesia
**Sch. of Electr. Electron. Eng., USM Eng. Campus, Malaysia
Ⅰ. INTRODUCTION
There are many types of inverter technologies available, such as the voltage source inverter (VSI) and the current source inverter (CSI), depending on the DC-link energy storage component. VSIs are classified into two-level inverters and multilevel inverters (MLI) [1]. The first MLI was introduced in 1981 by Nabae. It was a three-level inverter using the neutral point of the DC line. This topology is referred to as Neutral-Point-Clamped (NPC) [2]. Furthermore, the MLI fly capacitor topology [3]-[6] and the cascaded H-bridge [5]-[8] topology were proposed in the nineties.
In addition, some modulation and switching control techniques as well as those in two-level inverters are used by MLIs such as multilevel sinusoidal pulse width modulation (PWM), multilevel selective harmonic elimination, and space- vector modulation (SVM). The MLI type inverter is gaining popularity due to its better harmonic performance, high efficiency, lower electromagnetic interference, lower voltage stress and lower dv/dt ratio [9]-[16].
The cascaded H-bridge (CHB) is a recent MLI variant. With this topology, a higher number of output voltage levels can be achieved with fewer switches. The use of an H-bridge makes the circuit easy to modulate and easy to pack (making them faster and cheaper to build). However, the main disadvantage of the CHB-MLI is that a separate DC source is required [17]. The CHB-MLI is suitable for energy applications such as multi-panels PV systems, where the panels are connected as separate sources of the configuration.
Recently, there have been many proposed designs for reduced device count multilevel inverters (RDC-MLIs), especially H- bridge inverters such as the cascaded half-bridge-based multilevel DC-link (MLDCL) inverter, switched series/parallel sources (SSPS)-based MLI, series-connected switched sources (SCSS)-based MLI, multilevel module (MLM)-based MLI, reversing voltage (RV) topology, two-switch enabled level- generation (2SELG) based MLI and cascaded multilevel inverter minimum number of switches (MLI-MNS) [18], [19].
The MLDCL topology uses six symmetric DC sources, 12 switches at the generation level and 4 switches on the H-bridge sections. This topology obtained a result wave of 13 output levels, and harmonics (THDv) below 5% after using a low pass filter (LPF) [20], [21]. The MLI-MNS has the same topology as the MLDCL. The difference is in the number of DC sources and the number of switches at the generation level. It uses five symmetric DC sources and 10 switch sources on the generation level portion. The number of output wave levels is lower at only 11 levels [19].
A single-phase multilevel inverter using switched series/ parallel DC voltage sources has been presented [22], [23]. In this topology, the switch is operated in series and parallel to the DC source. In practice, with three symmetrical DC sources and 12 switches, 11-levels of output voltage waveform were obtained. The drawback of this topology is that it required a low pass filter to keep harmonics below 5%.
A new multilevel inverter topology has been presented in [24], [25], which is called reversing voltage (RV). This topology uses symmetrical DC sources, where 10 switches are required to obtain 7 levels of output voltage. The disadvantages of this topology include the use of PWM switching and a low pass filter to keep the THD below 5%.
A new cascaded multilevel inverter topology with a minimum number of switching has been described in [26]. In this topology, the number of switches is the number of DC sources plus five for resistive loads. For 41 levels of output voltage, 25 switches were used for resistive loads with 20 DC sources, where a THDv of 2% was obtained. However, it was found that a high number of sources and DC switches were required.
CHB type inverters can be operated as symmetric and asymmetric DC sources. In asymmetrical operation, the configuration ratios of the DC source voltages for each H-bridge are not equal. The first asymmetric CHB topology was proposed by Manjrekar. A DC input source that is not equal as a 1: 2 ratio that reaches 
is called an asymmetric binary configuration [27], [28]. Lai and Shu proposed a symmetrical topology with a DC ratio of a 1:3 input source, which is referred to as a trinary asymmetric configuration [29].
The topology in this paper is based on [16]-[18]. It uses an asymmetric DC source with a reduced number of switches. The topology proposed in this paper subtracts the switch at the generation level (eliminating the reverse switch) and uses an asymmetry DC source.
The proposed topology was first simulated using PSIM followed by a prototype circuit. Verification of the topology was conducted through laboratory experiments on resistive loads. Experiments were performed at a maximum power of 1,200W.
The contribution of this study is a comparison with papers [16]-[18]. For the same number of sources, the output wave level is higher and the THD is lower without using a low pass filter (LPF). The number of switches is lower so that the conduction loss and switching power loss are lower. Thus, a higher efficiency can be obtained. A lower the number of switches means lower manufacturing costs.
Ⅱ. TOPOLOGY, PRINCIPLE OF OPERATION AND DEGREE SWITCHING
A. Topology
This MLI topology reduces the number of switches used and four DC sources are asymmetric (not equal) voltage levels. The topology of the proposed multilevel inverter is shown in Fig. 1, which shows the number of switches used, four asymmetric DC sources voltage levels, generation levels (S1-S4 & D1-D4) and H-bridges (S5-S8). Level generation produces a multilevel wave of a half wave during a positive period and the H-bridge inverts the waveform for a complete one period waveform (positive and negative period).
Fig. 1. Proposed multilevel inverter with a reduced number of switches.
The VS1-VS4 source voltages are asymmetric binary, where VS1 is the least significant bit and VS4 is the most significant bit. Then the values VS1 
, VS2 
, VS3 
and VS4 
. Therefore. the ratio of the source voltage is VS1: VS2: VS3: VS4 = VS1: 2VS1: 4VS1: 8VS1.
The number of DC sources and switches at the generation level will determine the waveform output level. This can be calculated according to the equation below:
(1)Where Lvo is output level voltage and n is the number of DC sources. Based on equation (1) this multilevel inverter topology produces 31 levels.
The sequence for the switches S1-S8 for half of a period (t0-t31/mode operation 1-31), the instantaneous voltage at the output generation level (Vbus) and voltage drop in the switch (VSW) are shown in Table I.
The S5-S6 switches are ON for half a period, for the next half S7-S8 are ON so that the flow is opposite the load.
The maximum voltage at Vbus is calculated based on the following equation:
(2)The output RMS voltage is given by:
(3)The voltage sources Vs1-Vs4 are each calculated by the following equations:
(4)
(5)
(6)
(7)where 
is the RMS output voltage, and 
is the total voltage drop during switching. Based on Table I, 
can be calculated as follows:
(8)B. Principle of Operation
The principle of operation of the multilevel inverter in Fig. 1 is divided into 31 modes, where each mode forms one level. The operation modes from 1 to 31 half cycles starting at t0 to t31 are shown in Fig. 2-5.
|
(a) |
(b) |
|
(c) |
(d) |
|
(e) |
(f) |
|
(a) |
(b) |
|
(c) |
(d) |
|
(e) |
(f) |
|
(g) |
(h) |
|
(i) |
(j) |
|
(a) |
(b) |
|
(c) |
(d) |
|
(e) |
(f) |
|
(g) |
(h) |
|
(i) |
(j) |
|
(a) |
(b) |
|
|
|
|
(c) |
(d) |
|
(e) |
|
A waveform of Vbus for one period (t0-t62) is shown in Fig. 6(a) and an output waveform is shown in Fig. 6(b).
Fig. 6. Output waveforms. (a) Output level generation (Vbus). (b) Output of the inverter (Vo).
C. Switching Degree
The switching signal form for the generation level during t0 - t31 (0 - T/2) is shown in Fig. 7. The switching signal repeats for half a period (T/2 - T, T-3T/2, 3T/2 - 2T, etc.).
Fig. 7. Signal switching generation level. (a) Switch S1. (b) Switch S2. (c) Switch S3. (d) Switch S4.
The degree of the switching signal (α) is obtained using equations (9), (10) and (11).
(9)
(10)Here, Vm is the maximum voltage from the inverter output, which is 339.41V. In addition, Ln is the nth level, which is level 1 to 16, and Vkp is the voltage rise level, which is level 17 to 31. The value of Vkp is calculated using equation 11, and nL is the number of levels of the output voltage, which is 31. Therefore, Vkp is 22.63V.
(11)The middle values of the degree of signal switching (a) can be obtained from equations 9 and 10. For generating waves, as shown in Fig. 6 and Fig. 7, a starts from the rise time (rising time degree) and the fall time (falling time degrees). For the switch S1; α1=t1-t2, α2=t3-t4, α3=t5-t6, α4=t7-t8, α5=t9-t10, α6=t11-t12, α7=t13-t14, α8=t15-t16, α9=t17-t18, α10=t19-t20, α11=t21-t22, α12=t23-t24, α13=t25-t26, α14=t27-t28 and α15=t29-t30. For the switch S2; α1=t2-t4, α2=t6-t8, α3=t10-t12, α4=t14-t17, α5=t19-t21, α6=t23-t25 and α7=t27-t29. For the switch S3; α1=t4-t8, α2=t12-t19 and α3=t23-t27. For the switch S4; α1=t8-t23. The degrees of the rise time and the fall time can be calculated by equation 12.
(12)Where:
dan = Degree rises time to n
dbn = Degree down time to n
dtn = Degree middle time to n
dtn+1 = Degree time middle to n + 1
In the initial start, the lower degree value is 0 and the upper degree is 3.8. The value of the upper degree becomes the lower-grade in the 2nd degree. Then the degree value of the 2nd degree becomes the lower-grade on the 3rd degree and so on. From the width-degree calculation, the switching degrees for the S1-S4 switches are shown in Table II.
The source voltage Vs1-Vs4 is calculated based on the maximum voltage (Vm) of the output, namely:
(13)The effective voltage (Vrms) of the inverter output is 240V. Then Vm=339.41V. Based on equation 13, the voltage source VS1-VS4 is given in Table III.
| Source |
Comparison |
Voltage (V) |
| VS1 |
VS1 |
22.63 |
| VS2 |
2VS1 |
45.25 |
| VS3 |
4VS1 |
90.51 |
| VS4 |
8VS1 |
181.02 |
Ⅲ. EXPERIMENTAL CIRCUIT
The experiment circuit is based on the topology in Fig. 1, as shown in Fig. 8, where Fig. 8(a) is a power circuit and Fig. 8(b) is a control circuit. The maximum current flow in the switching device can be calculated with equation 14 for the output power (PO) 1200W, assuming an efficiency of h=0.94% and an output voltage of VO = 240V. Then the following relationship is obtained:
(14)The output voltage is 240V. Therefore, the max voltage (Vmak) is 339.4V and the maximum switch current is 5.3A. Based on these parameters, the S1-S8 switches use the IRFP460 MOSFET, which has a specifications of VDS 500 V, ID 20 A, RDS(on) 0.27Ω, tr 120ns and tf 98ns.
|
(a) |
|
(b) |
The switching signal in Fig. 6 has the shortest time from t1 to t3, which are t1 = 10.6µs and t3 = 53.3µs. Then the reverse recovery time diode D1-D4 is:
(15)In this case, the fast recovery type diode D1 - D4 (MUR 1560) can be used for the diode D1 - D4. This diode has specifications of VRMS 600 V, IFRMS 25 A and trr 35ns.
| Snubber Switch |
Dsn |
Csn (nF) |
Rsn (W) |
| S1 |
MUR 410 |
1.2 |
330 |
| S2 |
MUR 420 |
1.1 |
330 |
| S3 |
MUR 430 |
1 |
330 |
| S4 |
MUR 440 |
0.9 |
330 |
| S5-S8 |
MUR 460 |
12.9 |
470 |
The snubber circuit consists of diodes (Dsn), capacitors (Csn) and resistors (Rsn). Their values are given in Table IV. The Csn and Rsn values are calculated by the following equations:
(16)
(17)The port VS1 + until VS4 + is a positive port voltage, while the port VS1- until VS4- refers to a negative port DC source. The port VS1- until VS4 is separated from other ports (not unified). The port + G1 to + G8 and the port - G1 to -G8 make up the input switching signal from the circuit driver.
The drive circuit rated the generation of the S1- S4 switches using the TLP250 integrated circuit. These four integrated circuits use separate 18V power supplies. This is done so that the S1 - S4 switches become a floating earth point. The drive circuit for the H-bridge (S5-S8 switches) uses two IR210 integrated circuits. Both of these integrated circuits get an 18V supply. The switching control circuit for the switches S1-S8 uses a PIC 16F877 microcontroller and programming made using Basic Pro software. The power supply for this microcontroller circuit is from the same source as the H-bridge drive circuit. The experimental setup for the circuit in Fig. 8 is shown in Fig. 9.
Fig. 9. Experimental setup for the proposed circuit.
Ⅳ. RESULTS AND DISCUSSION
This inverter topology is designed for stand-alone systems with resistive and inductive loads. Simulations were carried out using PSIM software. For the prototype circuit, a fluke 43B dan scope Agilent DSOX 2012A was used for measurements.
A. Switching and DC Bus Wave
Simulation and experimental results at the generation level (switches S1, S2, S3, S4) are shown in Fig. 10(a) (simulation) and Fig. 10(b) (experiment), respectively. The simulated and experimental signals have the same shape and the ton-toff degree period for each signal (switch S1-S4) is given in Table II. This switching signal determines the output waveform of the multilevel inverter.
|
(a) |
|
(b) |
Simulation and experimental results for output voltage waveforms at the generation level (Vbus) are shown in Fig. 11(a) and Fig. 11(b), respectively. These simulated and experimental waveforms show a good agreement. This corresponds to the waveform in operation modes 1 to 62 (during the t0-t62 interval) as shown in Fig. 6(a). The waveforms consist of 31 voltage levels from V0 to V30, as given in Table I.
|
(a) |
|
(b) |
B. Resistive Loads
Voltage and current output waveforms simulation results for load of R = 48.3Ω (1200 watts of output power) are shown in Fig. 12, where a 240Vrms voltage and a 5.01A rms current were obtained. For comparison, experimental results as shown in Fig. 13, where a 240Vrms voltage and a 4.95A rms current were obtained. The experiment results agreed with the simulation for the resistance load analysis.
Fig. 12. Simulation output waveforms at a resistive load of 48.3Ω.
Fig. 13. Experiment output waveforms at a resistive load of 48.3Ω.
Waveforms of the voltage and current at a 48.3Ω resistive load are then measured with a Fluke 34B Power Quality as shown in Fig. 14. Fig. 14(a) shows a voltage waveform, a current wave and a power value display of 1.20kW, with a power factor of 1.00PF and a frequency of 50Hz. Meanwhile, Fig. 14(b) is also a voltage waveform, current wave with a 240.4V voltage value display, a 4.951A current value and a 50 Hz frequency.
|
(a) |
(b) |
The harmonic spectrums of the THDi and THDv at a 48.3Ω resistive load are shown in Fig. 15(a) and 15(b), respectively. The values of the obtained THDi and THDv are 1.7% and 1.6%, respectively.
|
(a) |
(b) |
Experimental results for the effect of load changes from 48.3Ω to 576Ω on the THDv are shown in Fig. 16, while the voltage is held constant at 240V.
Fig. 16. Effect on THDv from changes in the load resistance from 48.3Ω to 576Ω.
C. Inductive Load
In inductive loads, a spike voltage occurs due to self- induced emf (back emf). This spike voltage can be overcome (removed) by using a capacitor on the dc bus. The experimental voltage and output current R=54Ω and L= 146mH before the use of capacitors are shown in Fig. 17, and they are shown in Fig. 18 after the use of 22uF capacitors on the dc buses.
Fig. 17. Experimental output waveforms at an inductive load (R=54Ω dan L=146mH) without a capacitor.
Fig. 18. Experimental output waveforms at an inductive load (R=54Ω dan L=146mH) using a capacitor 22uF.
Harmonic spectrums of the THDi and THDv at an R=54Ω and L=146mH inductive load are shown in Fig. 19 and Fig. 20, respectively. The values of the THDi and THDv without a capacitor are 10.5% and 30.7% as shown in Fig. 19(a) and 19(b), respectively.
|
(a) |
(b) |
|
(a) |
(b) |
The values of the THDi and THDv using a capacitor 22uF on the dc bus are 2.4% and 1.1% as shown in Fig. 20(a) and 20(b), respectively.
The application of the inverter prototype on 36W fluorescent lamps is shown in Fig. 21-23. Current and voltage waveforms before and after the use of capacitors 3uF on the dc bus are shown in Fig. 21(a) and in Fig. 21(b), respectively.
|
(a) |
|
(b) |
The harmonic spectrum of the THDi and THDv for a 36W fluorescent lamp are shown in Fig. 22 and 23, respectively. The values of the THDi and THDv are 10.5% and 30.7%, respectively. This can be seen in Fig. 22(a) and Fig. 22(b).
|
(a) |
(b) |
The values of the THDi and THDv using a capacitor 3uF on the dc bus obtained are 9.2% and 1.3% as shown in Fig. 23(a) and Fig. 23(b), respectively. Here, the THDi value does not fall below 9.2%. This is caused by harmonics rather than the fluorescent lights which have a natural harmonic content (THDi).
|
(a) |
(b) |
The size of the capacitor value is determined based on the reactive power of the load produced by an inductive load. The capacitor value is calculated by the following equation:
(18)The power distributions at the PS1-PS4 input are not the same. The highest power on VS4 flows through the S4 switch and the lowest power on PS1 flows through the switch S1. The power distribution at a 48.3Ω resistive load is shown in Fig. 24(a). The total input power (Pts) of 1272W is distributed 67W (5%) on PS1, 150W (12%) on PS2, 316W (25%) on PS3 and 738W (58%) on PS4. The power losses (Plos) are 72W (6%) and the output power (Po) is 1200W (94%). The MLI efficiency that uses an IRFP460 MOSFET on the S1-S8 switches in the range from 100W to 1200W is shown in Fig. 24(b). The maximum efficiency was 97.02% at a 600W load, and it decreases to 94.37% at a 1200W load. Meanwhile, the optimum efficiency simulation result is 99.84%. This efficiency decrease was proportional to the load power increase of 97.28% at a 1200W load.
|
(a) |
|
(b) |
The THD value obtained from the proposed topology was better than that of the CMLI-RDC topology [19]-[26], [30]- [32]. The higher the number of output wave levels the lower the THD value. When compared with the CMLI-RDC inverter, the MSMLI topology has better performance based on the ratio of the output wave levels to the number of switches (L/NoS), as shown in Table V. The proposed MSMLI-CC topology has the highest L/NoS value of 3.87. In terms of the number of conduction switches, this topology is equivalent to the CMLI-RDC topology, and the number of switches determines the efficiency of the inverter.
| Topology of RDC-MLI |
DC Source |
Switch |
Output wave level |
L/NoS |
|
| Amount |
Conduction |
||||
| 4 |
12 |
3-6 |
9 |
0.75 |
|
| CMLI-MNS [19] |
4 |
12 |
3-6 |
9 |
0.75 |
| 4 |
13 |
3-6 |
9 |
0.69 |
|
| MLI-SCSS [30] |
4 |
12 |
3-6 |
9 |
0.75 |
| MLM [31] |
4 |
14 |
3-6 |
9 |
0.64 |
| 4 |
12 |
4-7 |
9 |
0.75 |
|
| MLI-2SELG [32] |
4 |
12 |
4 |
9 |
0.75 |
| CMLI-MNCS [26] |
4 |
12 |
3 |
7 |
0.58 |
| MSMLI (proposed) |
4 |
8 |
3-6 |
31 |
3.87 |
The use of a MLI with an asymmetric source is possible in PVs, especially in large power systems, due to the large number of PV panels that can be attached to asymmetric sources and the large number of sources for a MLI. While the number of switches used in a converter might be low, it should also be noted that some of the switches require a higher voltage rating in order to block the full DC link voltage. Thus, this should be taken into consideration when designing the converter.
Ⅴ. CONCLUSION
The cascaded multilevel inverter proposed in this paper obtained fairly good results when compared with other topologies for certain power ranges. The proposed topology can generate 31 wave levels with only eight switches and four asymmetric DC sources. Results show that with a resistive load of 48.3Ω and an output power of 1200W, the total harmonic distortion THDv is 1.7%, the THDi is 1.6% and the efficiency is found to be 94.37%. In practice, a maximum efficiency of 97.02% was obtained at 600W of load power. One drawback of this topology is the occurrence of voltage surges in the inductive load due to the emf effect. However, by using capacitors on the dc bus, the emf effect can be minimized. The size of the capacitor used should be proportional to the reactive power of the load. Nevertheless, the proposed inverter can achieve high output levels with a minimal number of switches.
ACKNOWLEDGMENT
This work was supported by Universiti Sains Malaysia under short term research grant 304/PELECT/60313042 and research university grant 1001/PELECT/8014028.
REFERENCES
[1] J. Rodríguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., Vol. 54, No. 6, pp. 2930-2945, Dec. 2007.
[2] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral- point-clamped PWM inverter,” IEEE Trans. Ind. Appl., Vol. IA-17, No. 5, pp. 518-523, Sep. 1981.
[3] T. Meynard and H. Foch, “Multi-level choppers for high voltage applications,” EPE J., Vol. 2, No. 1, pp. 45-50, Sep. 1992.
[4] C. Hochgraf, R. Lasseter, D. Divan, and T. Lipo, “Comparison of multilevel inverters for static var compensation,” in Conference Record-IEEE Industry Applications Society Annual Meeting, pp. 921-921, 1994.
[5] J.-S. Lai and F. Z. Peng, “Multilevel converters-a new breed of power converters,” IEEE Trans. Ind. Appl., Vol. 32, No. 3, pp. 509-517, May 1996.
[6] T. Meynard and H. Foch, “Multi-level conversion: high voltage choppers and voltage-source inverters,” in Power Electronics Specialists Conference, 1992. PESC'92 Record., 23rd Annual IEEE, pp. 397-403, 1992.
[7] P. W. Hammond, “A new approach to enhance power quality for medium voltage AC drives,” IEEE Trans. Ind. Appl., Vol. 33, No. 1, pp. 202-208, Jan. 1997.
[8] F. Z. Peng, J. W. McKeever, and D. J. Adams, “A power line conditioner using cascade multilevel inverters for distribution systems,” IEEE Trans. Ind. Appl., Vol. 34, No. 6, pp. 1293-1298, Nov. 1998.
[9] K. A. Aganah, C. Luciano, M. Ndoye, and G. Murphy, “New Switched-dual-source multilevel inverter for symmetrical and asymmetrical operation,” Energies, Vol. 11, No. 4, pp. 984-984, Apr. 2018.
[10] J. RodrÃguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 724-738, Aug. 2002.
[11] G. Ceglia, V. Guzman, C. Sanchez, F. Ibanez, J. Walter, and M. I. Gimenez, “A new simplified multilevel inverter topology for DC-AC conversion,” IEEE Trans. Power Electron., Vol. 21, No. 5, pp. 1311-1319, Sep. 2006.
[12] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel converters: An enabling technology for high-power applications,” Proc. the IEEE, Vol. 97, No. 11, pp. 1786-1817, Nov. 2009.
[13] J. Wang and D. Ahmadi, “A precise and practical harmonic elimination method for multilevel inverters,” IEEE Trans. Ind. Appl., Vol. 46, No. 2, pp. 857-865, Mar. 2010.
[14] I. Colak, E. Kabalci, and R. Bayindir, “Review of multilevel voltage source inverter topologies and control schemes,” Energy Convers. Manage., Vol. 52, No. 2, pp. 1114-1128, Feb. 2011.
[15] E. Babaei, S. Laali, and S. Alilu, “Cascaded multilevel inverter with series connection of novel H-bridge basic units,” IEEE Trans. Ind. Electron., Vol. 61, No. 12, pp. 6664-6671, Apr. 2014.
[16] E. Babaei, S. Laali, and Z. Bayat, “A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches,” IEEE Trans. Ind. Electron., Vol. 62, No. 2, pp. 922-929, Feb. 2015.
[17] K. N. V. Prasad, G. R. Kumar, T. V. Kiran, and G. S. Narayana, “Comparison of different topologies of cascaded H-Bridge multilevel inverter,” 2013 International Conference on Computer Communication and Informatics. IEEE, pp. 1-6, 2013.
[18] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel inverter topologies with reduced device count: A review,” IEEE Trans. Power Electron., Vol. 31, No. 1, pp. 135-151, Jan. 2016.
[19] E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topology with minimum number of switches,” Energy Conversion and Management, Vol. 50, No. 11, pp. 2761-2767, Nov. 2009.
[21] G. J. Su, “Multilevel DC-link inverter,” IEEE Trans. Ind. Appl., Vol. 41, No. 3, pp. 848-854, May 2005.
[22] Y. Hinago and H. Koizumi, “A single phase multilevel inverter using switched series/parallel DC voltage sources,” in Energy Conversion Congress and Exposition, ECCE, pp. 1962-1967, 2009.
[23] Y. Hinago and H. Koizumi, “A single-phase multilevel inverter using switched series/parallel DC voltage sources,” IEEE Trans. Ind. Electron., Vol. 57, No. 8, pp. 2643-2650, Aug. 2010.
[24] E. Najafi, A. Yatim, and A. Samosir, “A new topology -Reversing Voltage (RV)- for multi level inverters,” in Power and Energy Conference, 2008. PECon 2008. IEEE 2nd International, pp. 604-608, 2008.
[25] E. Najafi and A. H. M. Yatim, “Design and implementation of a new multilevel inverter topology,” IEEE Trans. Ind. Electron., Vol. 59, No. 11, pp. 4148-4154, Nov. 2012.
[26] A. S. Mohamad, N. Mariun, N. Sulaiman, and M. A. M. Radzi, “A new cascaded multilevel inverter topology with minimum number of conducting switches,” in Innovative Smart Grid Technologies-Asia (ISGT Asia), 2014 IEEE, pp. 164-169, 2014.
[27] M. D. Manjrekar and T. A. Lipo, “A hybrid multilevel inverter topology for drive applications,” in Applied Power Electronics Conference and Exposition, 1998. APEC'98. Conference Proceedings 1998., Thirteenth Annual, pp. 523-529, 1998.
[28] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, “Hybrid multilevel power conversion system: A competitive solution for high-power applications,” IEEE Trans. Ind. Appl., Vol. 36, No. 3, pp. 834-841, May 2000.
[29] Y.-S. Lai and F.-S. Shyu, “Topology for hybrid multilevel inverter,” IEE Proceedings-Electric Power Applications, Vol. 149, No. 6, pp. 449-458, Nov, 2002.
[30] W.-K. Choi and F.-s. Kang, “H-bridge based multilevel inverter using PWM switching function,” in Telecommunications Energy Conference, 2009. INTELEC 2009. 31st International, pp. 1-5, 2009.
[31] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel converter topology with reduced number of power electronic components,” IEEE Trans. Ind. Electron., Vol. 59, No. 2, pp. 655-667, Feb, 2012.
[32] M. F. Kangarlu and E. Babaei, “A generalized cascaded multilevel inverter using series connection of submultilevel inverters,” IEEE Trans. Power Electron., Vol. 28, No. 2, pp. 625-636, Feb. 2013.
Tarmizi Tarmizi was born in Aceh, Indonesia. He received his B.S. (S.T.) degree in Electrical Engineering from North Sumatera University, Medan, Indonesia; and his M.S. and Ph.D. degrees in Electrical and Electronics Engineering from the Universiti Sains Malaysia, Penang, Malaysia. He started working as a Lecturer in 1999, and became an Associate Professor in 2011 in the Department of Electrical Engineering, Syiah Kuala University, Banda Aceh, Indonesia. His current research interests include power electronics, power quality, renewable energy and electric drives.
Soib Taib was born in Penang, Malaysia. He received his M.S. and Ph.D. degrees in Power Electronics from the University of Bradford, Bradford, ENG, UK, in 1987 and 1990, respectively. Since 1990, he has been with the School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia, where he is presently working as a Key Researcher of the Green Technology Cluster, and a Task Manager for the CETREE and GT. He was a Visiting Lecturer at Monash University, Clayton, VIC, Australia; and at the University of Western Sydney, Sydney, NSW, Australia. He was also a Visiting Scientist at Kyoto University, Kyoto, Japan. His current research interests include power electronics, computer- aided engineering, renewable energy and thermography.
M. K. Mat Desa was born in Kuala Lumpur, Malaysia. He received his M.S. degree in Electrical and Electronic Engineering from Loughborough University, Loughborough, ENG, UK; and his Ph.D. from the National University of Malaysia, Bandar Baru Bangi, Malaysia. He has been working as a Senior Lecturer in School of Electrical and Electronics Engineering, Universiti Sains Malaysia, Penang, Malaysia, since 2014. His current research interests include solar photovoltaics, photovoltaic thermals and concentrators, and power converters.