https://doi.org/10.6113/JPE.2019.19.5.1108

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Design Methodology for Optimal Phase-Shift Modulation of Non-Inverting Buck-Boost Converters

Bingqing Shi^*, Zhengming Zhao^†, Kai Li^**, Gaohui Feng^*, Shiqi Ji^***, and Jiayue Zhou^*

^†,*Department of Electrical Engineering, Tsinghua University, Beijing, China

^**School of Electrical Engineering, Beijing Jiaotong University, Beijing, China

^***Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, TN, USA

Abstract

The non-inverting buck-boost converter (NIBB) is a step-up and step-down DC-DC converter suitable for wide-input-voltage- range applications. However, when the input voltage is close to the output voltage, the NIBB needs to operate in the buck-boost mode, causing a significant efficiency reduction since all four switches operates in the PWM mode. Considering both the current stress limitation and the efficiency optimization, a novel design methodology for the optimal phase-shift modulation of a NIBB in the buck-boost mode is proposed in this paper. Since the four switches in the NIBB form two bridges, the shifted phase between the two bridges can serve as an extra degree of freedom for performance optimization. With general phase-shift modulation, the analytic current expressions for every duty ratio, shifted phase and input voltage are derived. Then with the two key factors in the NIBB, the converter efficiency and the switch current stress, taken into account, an objective function with constraints is derived. By optimizing the derived objective function over the full input voltage range, an offline design methodology for the optimal modulation scheme is proposed for efficiency optimization on the premise of current stress limitation. Finally, the designed optimal modulation scheme is implemented on a DSPs and the design methodology is verified with experimental results on a 300V-1.5kW NIBB prototype.

Key words: Buck-boost mode, Current stress limitation, Efficiency optimization, Non-inverting buck-boost, Phase-shift modulation

Manuscript received Jan. 2, 2019; accepted May 14, 2019

Recommended for publication by Associate Editor Wu Chen.

^†Corresponding Author: zhaozm@mail.tsinghua.edu.cn  Tel: +86-13701150652, Tsinghua University

^*Dept. of Electrical Engineering, Tsinghua University, China

^**School of Electrical Engineering, Beijing Jiaotong University, China

^***Dept. of Electr. Eng. and Computer Science, Univ. of Tennessee, USA

I. INTRODUCTION

A wide input voltage range is common among various power electronic applications, such as solar generation which produces large voltage fluctuations. Under such circumstances, where input voltage has the chance to be higher or lower than the output voltage, a step-up/step-down converter is required to meet the demands of varying the ratio between the input and output voltage.

There are various types of step-up/step-down converters, including isolated DC/DC, Sepic, Zeta, Cuk, inverting Buck- Boost and non-inverting Buck-Boost converters (IBB and NIBB). The isolated DC/DC converters like DAB are not suitable for a wide input voltage range, which results in a large inductor current [3], [5]. For Sepic and Zeta converters, there are too many passive components, resulting in a low power density. The Cuk converter is a better choice as a current-source converter, but is not suitable for voltage source applications [4]. Although the IBB has less switches than the NIBB, it introduces much higher voltage and current stresses on the switches, and has higher values for the current RMS and the current ripple on the inductor [1], [2]. This results in higher requirements for the current capacity of the inductors and switches, which in turn results in higher costs. Therefore, the NIBB is a reasonable choice and is the main focus of this paper.

For the NIBB in Fig. 1(a), Q_1SR is complementary to Q₁, and Q_2SR is complementary to Q₂. Under a unidirectional power-flow situation such as PV power generation, Q_1SR and Q_2SR are usually kept off or replaced by two diodes as shown in Fig. 1(b) [4]. Both synchronous control and asynchronous control can be used for the NIBB. In synchronous control [2], Q₁ and Q₂ are switched on or off simultaneously, transforming the NIBB into the IBB and consequently causing higher voltage and current stresses. To solve this problem, asynchronous control was proposed for voltage and current stress reduction.

Fig. 1. Non-inverting buck-boost converter. (a) Four active switches. (b) Two active switches.

(a)

(b)

In asynchronous control, the control signal of Q₁ is independent from that of Q₂. Two-mode control (buck mode and boost mode) has attracted the attention of some researchers thanks to its high efficiency [6]-[9]. When the input voltage is lower than the output voltage, Q₂ is switched on and off while Q₁ is kept on. This is called the boost mode. When the input voltage is higher than the output voltage, Q₁ is on and off while Q₂ is kept off. This is called the buck mode. However, neither of the modes can operate well when the input voltage is close to the output voltage due to switching delay and driver delay [10], [11]. Therefore, a buffer mode, when the input voltage gets close to the output voltage, is inserted between the buck and boost modes, which is called three-mode control [12]-[14].

Three-mode control includes buck, boost and buck-boost modes. In the buck-boost mode, four switches (including two active power semiconductors and two diodes) operate at high frequencies, resulting in a significant increase of the switching loss. Many papers tend to improve efficiency by soft-switching [15]-[17]. However, this inevitably increases the voltage and current stresses on the switches. Some papers have proposed strategies to increase the efficiency of NIBB in the buck-boost mode. One such strategy involves decreasing the equivalent switching frequency [6], [12]. Wide band gap semiconductors (e.g. silicon carbide) have also been used for switching loss reduction. Some other papers solve the efficiency problem from the perspective of the modulation scheme. A novel modulation scheme to achieve a higher efficiency was proposed in [19]. However, the current stress, which is equal to the peak current value of the switches, is too high, which may result in overcurrent damage on the switches. Reference [7] attempts to decrease the current RMS value with leading edge modulation and a decrease in the switching frequency, which reduces the conduction and switching loss of the switches. However, only two types of modulation schemes (leading edge and trailing edge) were compared in [7]. The impact of a shifted phase is considered in [18]. However, it only focuses on efficiency maximization through ZVS, which, as previously discussed, inevitably increases current stress on the switches. In addition, without analytic inductor current expressions in all of the modulation schemes, the analysis of the efficiency in [18] is qualitative rather than quantitative. In this paper, a novel general phase-shift modulation scheme is proposed, with every input voltage, duty ratio and shifted phase taken into account. Then analytical expressions of the inductor current are derived accurately for different types of modulation schemes, presenting the switch current stress and converter efficiency. Both the current stress limitation and the efficiency optimization in the buck-boost mode are discussed from the perspective of modulation schemes. All of the other factors, such as the power stage and switching frequency, are fixed.

This paper focuses on designing an optimal modulation scheme, and achieving efficiency optimization and current stress limitation for a unidirectional two-switch NIBB in the buck-boost mode. In Section II, the basic input voltage range of the unidirectional NIBB in the buck-boost mode is introduced. Then, formulas are derived considering two degrees of freedom including the shifted phase and duty ratio. In Section III, a general phase-shift modulation is introduced. Based on this, the inductor current considering every duty ratio, shifted phase and input voltage is derived. In Section IV, the current stress of the switches, and the converter efficiency are analyzed in detail. Accordingly, by optimizing an objective function with inequality constraints, an offline design methodology of the modulation scheme for both converter efficiency optimization and current stress limitation is proposed. Efficiency can be optimized based on the premise of current stress limitation, which can be determined by the designers according to system requirements. In Section V, a novel optimal modulation scheme is presented, based on the design methodology, which provides the selection method for the NIBB converter parameters. The current stress limitation and efficiency optimization of the modulation scheme are experimentally validated on a 300V, 1.5kW NIBB prototype. Finally, some conclusions are presented in Section VI.

II. OPERATION PRINCIPLE OF THE NIBB

A. Operation Range of the Buck-Boost Mode

A two-switch NIBB is shown in Fig. 1(b). In the asynchronous control, Q₁ and Q₂ can be controlled independently. The relationship between the input voltage and the output voltage is:

            (1)

where d₁ is the duty ratio of Q₁, and d₂ is the duty ratio of Q₂.

There are three operation modes for the NIBB. When the input voltage V_in is much lower than V_out, the converter operates in the boost mode with Q₁ kept on and Q₂ operating in the PWM mode. When the input voltage is much higher than V_out, the converter operates in the buck mode with Q₂ kept off and Q₁ operating in the PWM mode. When V_in is close to V_out, the NIBB operates in the buck-boost mode where both Q₁ and Q₂ operate in the PWM mode. The relationships among the operation modes and the input voltage are shown in Fig. 2. As shown in [7], two hysteresis zones are needed between the two adjacent operation modes (i.e. the boost and buck-boost modes, and the buck-boost and buck modes) to avoid converter swing.

Fig. 2. Three operation modes in a NIBB.

When the NIBB operates in the boost mode, the relationship between V_in and V_out is:

             (2)

When the NIBB operates in the buck mode, the relationship between V_in and V_out is:

            (3)

Because of the switching delay and the driver delay, there is a minimum pulse width for the power semiconductor, which is notated as d_min. The ranges of the duty ratios can be represented as:

         (4)

By substituting Eqns. (4) into (2) and (3), the maximum input voltage V₁ in the boost mode and the minimum input voltage V₂ in the buck mode are:

           (5)

Set ∆V as the hysteresis width. Then the input voltage range for the buck-boost mode can be presented by:

         (6)

Define c as the ratio of the input voltage to the output voltage. Then c can be represented as:

         (7)

B. Degrees of Freedom for the Modulation Scheme in the Buck-Boost Mode

Since only the buck-boost mode is considered in this paper, its control and modulation diagram are presented in Fig. 3. The PWM signals of Q₁ and Q₂ are generated by comparing the duty ratios d₁ and d₂ with two sawtooth carriers. Here, d₁ is set as a constant value while d₂ is determined by two PI controllers. The inductor current i_L and the output voltage V_out are sampled once per switching period. The outer-loop controller calculates the inductor current reference i_L^*, while the inner-loop controller regulates i_L to i_L^*. The controller design is not the focus of this paper. With a certain input and output voltage, the degrees of freedom for a modulation scheme are the shifted phase ratio ∆p between the carriers of Q₁ and Q₂ and d₁. Various modulation schemes are represented by these two factors. ∆p can arbitrarily vary between 0 and 1, where 1 means 2π for the shifted phase. The limitation on d₁ is derived as follows.

Fig. 3. Control and modulation diagram in the buck-boost mode.

Substituting Eqns. (1) and (5) into (6) yields:

       (8)

In order to guarantee operation over the full input voltage range mentioned in (6) in the buck-boost mode, the range of d₂ should meet the requirements in (8). Considering Eqns. (4) and (8), d₁ should satisfy:

        (9)

Therefore, the range of d₁ is derived as:

    (10)

As discussed above, with given values of d_min, V_{out and ∆}V, the range of d₁ should satisfy the requirements in Eq. (10), which are used as boundaries for optimization design in the following sections.

III. ANALYSIS OF A NIBB WITH PHASE-SHIFT MODULATION

The two control degrees of freedom d₁ and ∆p can change to form different types of modulation schemes. With consideration of the different types of modulation schemes, a general phase- shift modulation, which can be used for NIBB converter improvement, is introduced in this paper. In this section, different situations involving various input voltages, duty ratios and phase shift ratios are analyzed with this general phase-shift modulation.

A. Waveforms in Different Situations with Phase-shift Modulation

For the NIBB shown in Fig. 1(b), there are four states. The four states are: Q₁ and Q₂ are both on; Q₁ and Q₂ are both off; Q₁ is off and Q₂ is on; and Q₁ is on and Q₂ is off. The inductor current slopes for the four switching states can be calculated as:

        (11)

Based on the above four inductor current slopes, inductor current waveforms in different situations in a switching period T_s are shown in Fig. 4 through Fig. 7, considering different input voltages and d₁. In each figure, inductor current waveforms with various phase-shift ratios are diagramed during four periods (i.e. t₁, t₂, t₃ and t₄).

Fig. 4. Gate signals and inductor current waveforms when V_in<V_out and d₁>d₂.

In fact, the relative positions between the two control signals of Q₁ and Q₂ can be sorted into six phase-shift types (PST) as shown in Fig. 8. The above 16 situations can be grouped into these six PSTs, as shown in Table I.

TABLE I  RELATIONS AMONG THE 16 SITUATIONS AND SIX PSTS

	Vin<Vout, d1>d2 Fig. 4	Vin<Vout, d1<d2 Fig. 5	Vin>Vout, d1>d2 Fig. 6	Vin>Vout, d1<d2 Fig. 7
PST (1): Fig. 8(a)	Fig. 4(a)		Fig. 6(a)
PST (2): Fig. 8(b)	Fig. 4(b)	Fig. 5(a)	Fig. 6(b)	Fig. 7(a)
PST (3): Fig. 8(d)	Fig. 4(c)	Fig. 5(b)
PST (4): Fig. 8(c)			Fig. 6(c)	Fig. 7(b)
PST (5): Fig. 8(e)	Fig. 4(d)	Fig. 5(c)	Fig. 6(d)	Fig. 7(c)
PST (6): Fig. 8(f)		Fig. 5(d)		Fig. 7(d)
The characteristics for these six PSTs are as follows. PST (1): 0 ≤ ∆p < d1- d2, which appears only when d1 > d2. PST (2): min(d1- d2,0) ≤ ∆p < min(d1,1-d2). PST (3): 1-d2 ≤ ∆p < d1, which appears only when Vin< Vout. PST (4): d1 ≤ ∆p < 1-d2, which appears only when Vin > Vout. PST (5): max(d1,1-d2) ≤ ∆p < min(1+d1-d2, 1). PST (6): 1+d1-d2 ≤ ∆p < 1, which appears only when d1 < d2.

Fig. 8. Relative position between the two control signals in six PSTs.

(a)	(b)	(c)
(d)	(e)	(f)

B. Ampere-second Equivalent Principle

When Q₂ is off, the current flow of the inductor, as shown in Fig. 1(b), is expressed by:

        (12)

When Q₂ is on, the current flow of the inductor satisfies:

        (13)

In addtion, there is:

          (14)

Assuming the time duration when Q₂ is kept off is t_off and the time duration when Q₂ is kept on is T_s - t_off. Equation (14) is integrated in a switching period, and the item in the right side is zero. Combining (12) and (13) yields:

     (15)

Therefore:

        (16)

When V_out is stable, the integral of i_L during t_off remains constant.

C. Derivation of the Inductor Current

i₁ is the inductor current at the rising edge of Q₁, i₃ is the inductor current at the falling edge of Q₁, i₂ is the inductor current at the rising edge of Q₂, and i₄ is the inductor current at the falling edge of Q₂. From Fig. 4 through Fig. 7, i₁ and i₂ are never higher than i₃ and i₄. The maximum inductor current is the higher among i₃ and i₄, while the minimum value is the lower among i₁ and i₂. The current stress, defined as the peak current of the switches, is equal to the maximum inductor current.

Fig. 9. Inductor current in PST (1).

Fig. 9 shows an inductor current waveform in PST (1), which is only suitable when d₁ > d₂. The inductor currents in PST (1) are given by:

         (17)

According to the above ampere-second equivalent principle, the currents i₁, i₂, i₃ and i₄ can be derived by combining Eqns. (17) and (16):

       (18)

i₁, i₂, i₃ and i₄ from PST (2) to PST (6) are derived and given as follows.

PST (2): d₁-d₂ ≤ ∆p < min(d₁, 1-d₂)

      (19)

PST (3): 1-d₂ ≤ ∆p < d₁ and V_in < V_out

      (20)

PST (4): d₁ ≤ ∆p < 1-d₂ and V_in > V_out

      (21)

PST (5): max(d₁, 1-d₂) ≤ ∆p < min(1+d₁-d₂, 1)

    (22)

PST (6): 1+d₁-d₂ ≤ ∆p < 1 and d₁ < d₂

         (23)

In summary, the inductor current waveforms with various duty ratios, input voltages and shifted phases between the control signals of Q₁ and Q₂ are sorted into six PSTs based on the relative positions of the control signals. The analytical expressions of the inductor current are all obtained with the ampere-second equivalent principle. In the following section, the current stress and efficiency will be analyzed and calculated for current stress minimization and efficiency maximization over the entire input voltage range.

IV. OFFLINE DESIGN METHODOLOGY FOR THE OPTIMAL MODULATION SCHEME

Based on the inductor current derived in Section III, current stress minimization and efficiency maximization schemes for minimal current stress and maximal efficiency over the entire V_in range are proposed. Then, a design methodology for modulation schemes in the buck-boost mode to take both the current stress and efficiency into consideration is proposed. Current stress should be limited to protect switches to operate in the safe operating area. Efficiency is optimized in the buck-boost mode on premise of current stress limitation in this section.

A. Current Stress Minimization

With the current stress i_stress(∆p, d₁, V_in) derived above, the procedure for achieving the modulation scheme with minimal current stress i_stress*(V_in) in the range of inequality (6) in the buck-boost mode is:

1) Configuration of d1:

There are two control degrees of freedom including d₁ and ∆p. First, d₁ can be randomly configured in the range of inequality (10).

2) Derivation of ∆p = f(d1, Vin) to Minimize Current Stress istress(∆p, d1, Vin) for a Given d1:

Take the situations in Fig. 4 as an example to analyze the current stress tendency with ∆p increasing from 0 to 1 when d₁ and V_in are fixed. According to Table I, there are four PSTs (1), (2), (3) and (5) in this case.

When ∆p changes from 0 to d₁-d₂, the situation belongs to PST (1), and the current stress is i₄. The relationship between i₄ and ∆p is shown in the following equation. i₄ increases with an increasing ∆p.

          (24)

When ∆p changes from d₁-d₂ to 1- d₂, the situation belongs to PST (2) and the current stress is i₃ or i₄(i₃= i₄). The relationship between the current stress and ∆p is shown as follows. The current stress decreases with an increasing ∆p.

      (25)

When ∆p changes from 1- d₂ to d₁, the situation belongs to PST (3) and the current stress is i₄. The relationship between i₄ and ∆p is given as follows. i₄ is constant with an increasing ∆p.

          (26)

When ∆p changes from d₁ to 1, the situation belongs to PST (5) and the current stress is i₄. The relationship between i₄ and ∆p is shown as the following inequality. i₄ increases with an increasing ∆p.

      (27)

Therefore, for given values of V_in and d₁, the current stress reaches its minimum in PST (3) when ∆p changes from 0 to 1.

The current stress in other cases (as shown in Fig.5, Fig.6 and Fig.7) can be derived using the above procedure. For given value of V_in and d₁, the current stress reaches its minimum in PST (3) when V_in < V_out, and in PST (4) when V_in > V_out.

Fig. 5. Gate signals and inductor current waveforms when V_in<V_out and d₁<d₂.

Fig. 6. Gate signals and inductor current waveforms when V_in>V_out and d₁>d₂.

Fig. 7. Gate signals and inductor current waveforms when V_in>V_out and d₁<d₂.

3) Determination of d1 to Minimize Current Stress istress*(Vin) = min(istress(Vin, d1)):

As discussed above, considering the minimum current stress in PST (3) and PST (4), the minimized current stress under various values of d₁ can be obtained through an analysis of these two PSTs. For the current stress in PST (3), the derivation of the current stress with respect to d₁ is represented as:

         (28)

For the unidirectional NIBB, i₁ i₂ i₃ i₄ ≥ 0. Therefore, ∂i₄/∂d₁ ≤ 0. i_stress(d₁) decreases with an increasing d₁. Similarly, the current stress in PST (4) when V_in > V_out can also be analyzed.

It can be concluded that over the entire range of V_in, the current stress reaches its minimum value in PST (3) when V_in < V_out or in PST (4) when V_in > V_{out. ∆}p for the minimum current stress with a given d₁ can be obtained with consideration of these two PSTs. In terms of the freedom of d₁, based on Eq. (28), it should be configured as the maximum value in the range in Eq. (10). Eventually, the two degrees of freedom (d₁ and ∆p) for current stress minimization i_stress*, where each V_in can be obtained as listed in Table II.

TABLE II  (D₁, ∆P) FOR CURRENT STRESS MINIMIZATION

	d1	∆p	Current stress istress*(Vin)
Vin<Vout		1-d2 ≤ ∆p < d1
Vin≥Vout		d1 ≤ ∆p < 1-d2

B. Efficiency Maximization

A model calculating the power loss is needed to obtain the efficiency. The power losses of the NIBB mainly consist of the inductor loss, and the conduction and switching losses of the power semiconductors. The impact of the other power losses (e.g. auxiliary power supply loss and PCB copper trace loss) are negligible for various modulation schemes and input voltages.

The inductor currents i₁, i₂, i₃ and i₄ shown in Fig. 9(a) are equal to the turn-on and turn-off currents of Q₁ and Q₂, which impacts the switching losses. The power semiconductors are approximated at the conduction state as resistors. The RMS value of the inductor current, which impacts the conduction loss of the power semiconductors and inductor loss, can also be obtained with i₁, i₂, i₃ and i₄. Therefore, the total power loss of the NIBB is highly affect by i₁, i₂, i₃ and i₄.

1) Efficiency Calculation:

a) Inductor Losses

As for the losses of the inductor, according to test results [20] - [22], the core loss of the inductor can be obtained by:

       (29)

where B is the maximum magnet density of the AC component, and f_s is the magnet density frequency of the AC component, which is also the switching frequency. C_m, α and β can be obtained by curve fittings based on experimental results.

R_Lac and R_Ldc are the AC resistance and DC resistance of the winding, respectively. The copper loss can be represented as:

          (30)

where:

        (31)

b) Switching Losses of Power Semiconductors

There are two kinds of power semiconductors in the NIBB, including two diodes and two active switches. Switching losses exist during the turn-on and turn-off of Q₁ and Q₂.

When Q₁ turns on, Q₁ commutates with Q_SR1, resulting in turn-on loss of Q₁ and turn-off loss of Q_SR1. These losses can be presented by a function of i₁:

        (32)

When Q₁ turns off, there is only the turn-off loss of Q₁ since the turn-on loss of the diode is negligible. It can be calculated by:

           (33)

where f_on(iV) is the total turn-on loss and f_off(iV) is the total turn-off loss relating to current and voltage of Q₁ (i.e. V_in). f_on and f_off can be obtained by the following steps.

(1) Collect the switching data of the power semiconductor through double pulse tests under different load currents and dc voltages.

(2) Calculate the turn-on and turn-off losses by integrating the product of switching current and voltage during switching transients.

(3) Obtain f_on(iV) and f_off(iV) through curve fitting.

When Q₂ turns on, Q₂ commutates with Q_SR2, resulting in the turn-on losses of Q₂ and the turn-off losses of Q_SR2. They can be calculated by:

        (34)

When Q₂ turns off, only the turn-off loss of Q₂ exists. This loss can be represented as:

       (35)

c) Conduction Losses of Power Semiconductors

The RMS value of the conduction current on the power semiconductors is required for the conduction loss calculation. Taking the situation in Fig. 9 as an example, the RMS current values of Q₁ and Q_SR1 are:

     (36)

Then, the conduction losses of Q₁ and Q_SR1 are:

       (37)

Where U_{on_Q1} and U_{on_QSR1} are the conduction voltage on Q₁ and Q_SR1. They are related to the current on Q₁ and Q_SR1 (i_{rms_Q1} and i_{rms_QSR1}) and can be achieved by experiments and curve fittings. The conduction losses of Q₂ and Q_SR2 are the same as those of Q₁ and Q_SR1.

d) Efficiency Calculation

The total loss can be derived by:

    (38)

Thus, the efficiency can be represented as:

        (39)

In terms of the equations (18)-(23) given in Section III-C, even with the same V_in(c), the inductor current waveforms change with the PSTs (i.e. various d₁ and ∆p), resulting in different efficiencies. The efficiency η(d₁,∆p) can be calculated by substituting the inductor current given in equations (18)- (23) into equations (29)-(39). Then, considering efficiency maximization, d₁ and ∆p can be obtained with the given V_in.

2) Objective Function of Efficiency Over the Entire Range of Vin and Efficiency Maximization:

V_in in the range in Eq. (6) can be discretized into n steps as V_in(1), V_in(2),…, V_in(n). The efficiency in each step can be calculated as η₁(x), η₂(x),…, η_n(x), where x refers to (d₁ and ∆p).

The efficiency functions η_i(x)(i=1,2,…,n) with different input voltages V_in are different from each other and can be optimized with a particular x₁, x₂ …, x_n shown in Eq. (40), as analyzed above.

        (40)

Total efficiency optimization with two control freedom degrees (d₁ and the shifted phase angle ∆p) over the entire range of V_in is derived as a multi-objective optimization, as shown in Eq. (41).

    (41)

To turn this multi-objective optimization into a single- objective optimization, an objective function of efficiency is obtained by a linear weighted summation algorithm as follows.

Step 1: discretize V_in in the range in Eq. (6) into n steps as V_in(i), where i = 1:n. The efficiency at V_in(i) is derived as η_i(x), where x refers to (d₁, ∆p). For every η_i(x) (i=1,…,n), calculate η_i(x_j) (j=1,…,n).

Step 2: calculate the bias δ_ij = η_i(x_i) - η_i(x_j).

Step 3: calculate the average bias m_i by

             (42)

Step 4: sort m_i:

        (43)

The weight coefficients can be represented as:

       (44)

Correspondingly, λ_s1 ≥ λ_s2 ≥ … ≥ λ_sn. Then, define the objective function of the efficiency over the entire V_in range as shown in the following formula.

   (45)

Finally, considering η_goal as the objective function of efficiency over the entire range of V_in, x_goal (i.e. d₁ and ∆p) can be obtained through the maximization of η_goal(x).

C. Proposed Design Methodology of Optimal Modulation Schemes

It is feasible to design a modulation scheme achieving the current stress minimization as analyzed in Section IV-A or the efficiency maximization as analyzed in Section IV-B over the entire input voltage range in the buck-boost mode. However, neither of them can achieve both goals (i.e. efficiency maximization and current stress minimization) at the same time.

A design methodology for the modulation schemes is proposed to take both efficiency and current stress into account. Efficiency is optimized in the buck-boost mode based on the premise of current stress limitation by maximizing the objective function with n inequality constraints shown in Eq. (46). The n inequality constraints are for the current stress limitation while the objective function is for efficiency optimization.

      (46)

where i_stress*(V_in) is the minimum current stress with V_in derived in Table II. In addition, i_stress(d₁, ∆p, V_in) is the current stress function of d₁, ∆p with V_in derived by Eq. (18)-(23). λ, the limitation ratio for the current stress, should be determined by the designers according to their requirements in terms of current stress limitation. λ is always greater than 1. The higher the requirements of the current stress limitation, the closer λ should be to 1.

The whole process for the proposed design methodology in Fig. 10 is divided into two steps.

Fig. 10. Flow chart of the proposed design methodology.

(1) Limit the current stress based on the analysis in Section IV-A. The range of (d₁, ∆p), meeting that the current stress is lower than a defined threshold λi_stress* (V_in(i)) (e.g. λ = 1.1) for every V_in(i) can be solved.

(2) Maximize the efficiency based on the discussion in Section IV-B, while (d₁, ∆p) should be in the range obtained in step (1).

V. SIMULATIONS AND EXPERIMENTAL VERIFICATIONS

In order to verify the proposed design methodology, a prototype with an output voltage of 300 V is built, as shown in Fig. 11. FF150R12MS4G IGBTs are used as the active switches and diodes. A DSP320F2812 is applied as the DSP chip of the control board, while a CPLD is used for hardware protection. A power analyzer YOKOGAWA-WT1800 is used to measure the efficiency of the prototype.

Fig. 11. Prototype of a NIBB.

The parameters of the prototype are given in Table III. The performance of the NIBB in the buck-boost mode is the focus of this paper, and the input voltage varies from 280 V to 320 V. d₁ changes from 0.054 to 0.88 as calculated by an inequality, while _∆p varies from 0 to 1. The discretization step size of d₁, ∆p and V_in are 0.01, 0.01 and 1 V, respectively. The parameters d_min and ∆V are introduced in Section II. λ is the ratio between the current stress threshold and the minimal current stress, as introduced in Section IV-C. It can be determined by the designers according to the requirements in terms of current stress limitation.

TABLE III  PARAMETERS OF THE NIBB IN THE BUCK-BOOST MODE

parameters	values
Input voltage Vin	280 V~320 V
Output voltage Vout	300 V
Output power	1.5 kW
Inductance L	1 mH
Equivalent AC resistor RLac	0.2 Ω
Equivalent DC resistor RLdc	0.733 Ω
Load resistor R	60 Ω
Output capacitor C	420 μF
Switching period Ts	50 μs
dmin	0.05
∆V	5 V
λ	1.1

A. Simulations and Modulation Scheme Design

1) Simulation Verifications for Inductor Current Analyses and Formulations:

Take PST (1) and PST (3) as examples to verify the inductor current analyses and formulations in Section III with simulation results. V_in = 280 V, d₁ = 0.85. In Fig. 12, ∆p = 0, and it belongs to PST (1). A simulation inductor current waveform shown by the blue line in Fig. 12 is almost the same as the one obtained by analyses and calculations shown as the green dotted line. Similarly, in Fig. 13, ∆p = d₁, and it belongs to PST (3). The shape and value of the simulation inductor current shown as the blue line in Fig. 13 are almost the same as the inductor current waveform by analyses and calculations shown as the green dotted line.

Fig. 12. Simulation verification for inductor current analyses in PST (1).

Fig. 13. Simulation verification for inductor current analyses in PST (3).

2) Current Stress Limitation:

Firstly, with a fixed V_in, 280 V for instance, i_stress* can be achieved by the current stress minimization scheme in Section IV-A. According to the current stress minimization scheme in Section IV-A, i_stress* is obtained when d₁ reaches its maximum and ∆p is in PST (3). As shown in the simulation results shown in Fig. 14, the minimum current stress i_stress* can be achieved when d₁ = 0.88 and ∆p = 0.8446, which is between 1-d₂ and d₁. i_stress* is 6.5 A when V_in = 280 V. The horizontal plane is the current stress threshold which is equal to λi_stress* = 1.1 i_stress*.

Fig. 14. Current stress varying with the shifted phase and d₁ when V_in = 280 V.

Then, the range of (d₁, ∆p), meeting that the current stress limitation, is lower than 1.1 i_stress*, when V_in is fixed to 280 V is obtained as shown in the yellow area in Fig. 15.

Fig. 15. Appropriate area of (d₁, ∆p) for limited current stress when V_in =280 V.

Similarly, as shown Fig. 15, when V_in varies inside the scope of the buck-boost mode, every range of (d₁, ∆p) under various values of V_in considering the current stress limitation can be obtained. The intersection area of these ranges, where the current stress is lower than the threshold over the entire range of V_in in the buck-boost mode, is shown as the yellow area in Fig. 16, where the efficiency optimization is conducted.

Fig. 16. Intersection area of (d1, ∆p) for limited current stress over the entire range of V_in.

3) Efficiency Optimization:

V_in varies from 280 V to 320 V and can be divided into 41 steps with a step size of 1 V. Based on the analysis in Section IV-B, the maximum η₁, η₂, …, η₄₁ in the range given in Fig. 16 is shown in Fig. 17.

Fig. 17. Optimized efficiency when V_in varies.

With the same procedure used in Section IV-B, the optimized modulation parameter (d₁, ∆p) considering both current stress limitation and efficiency optimization is (0.88, 0.99).

4) Simulation Comparisons of the Efficiencies between the Designed Modulation Scheme and the Modulation Scheme in [7]:

Power losses and efficiency can be calculated with the mathematical formulations (29)-(39) for loss evaluation. Efficiency with the designed optimal modulation scheme is compared with that with the modulation scheme in reference [7], which obtained the highest efficiency among previous studies, as shown in Fig. 18. A higher efficiency for an NIBB in the buck-boost mode is achieved with the designed optimal modulation scheme. Then, taking V_in = 280 V as an example, comparisons of the simulation losses for each part between the designed modulation scheme in this paper and the one in [7] are shown in Fig. 19. Power losses in each part are reduced with the modulation scheme designed in this paper.

Fig. 18. Simulation results of the efficiencies of two optimization schemes.

Fig. 19. Simulation comparisons of the efficiency of each part for the two optimization schemes.

B. Experimental Verifications

1) Experimental Verifications for the Inductor Current Analyses and Formulations:

In the first step, experiments are conducted to validate the formulations and analyses on inductor current waveforms with given values of V_in and d₁. V_in is 280 V, which is lower than V_out = 300 V. d₁ is 0.85, which is larger than d₂. Experimental verifications for the inductor current analyses and formulas in PST (1) and PST (3) are shown in Fig. 20(a) and (b). The shape and value of the experimental inductor current waveforms shown as the red lines in these figures are consistent with the inductor current waveforms by analyses and simulations shown as the blue lines.

Fig. 20. Experimental verifications for the inductor current analyses in: PST (1); PST (3).

(a)

(b)

With regard to the verifications for the current stress analyses, four types of the experimental results are shown in Fig. 21, corresponding to PSTs in Fig. 4(a), (b), (c) and (d), respectively. The trend of the current stress follows the conclusion provided in section IV-A. The current stress reaches its minimum in PST (3), as shown in Fig. 4(c). This satisfies the conclusion on the minimum current stress in Section IV-A.

Fig. 21. Inductor current waveforms of experiments. (a1) Phase-shift situation in Fig. 4(a); shifted phase is 0. (a2) Phase-shift situation in Fig. 4(a); shifted phase is 0.36. (b) Phase-shift situation in Fig. 4(b); shifted phase is 0.80. (c) Phase-shift situation in Fig. 4(c); shifted phase is 0.83. (d) Phase-shift situation in Fig. 4(d); shifted phase is 0.93.

(a1)	(a2)
(b)	(c)

For the current stress in PST (3), d₁ is varied and the relationship between the current stress and d₁ is validated. Experimental results for the current stress with various values of d₁ when V_in = 280 V and 320 V are shown in Table IV. The current stress decreases with d₁ increasing for every V_in, which satisfies the conclusion on the minimum current stress in Section IV-A.

TABLE IV  CURRENT STRESS WITH VARIOUS VALUES OF D₁

	d1= 0.80	d1= 0.85	d1= 0.88
Vin=280 V	7.29 A	6.93 A	6.33 A
Vin=320 V	6.70 A	6.06 A	5.67 A

2) Current Stress Limitation Verifications with the Designed Modulation Scheme

Then, experiments are conducted to verify that the inductor current stress with the designed optimal modulation scheme meets the current stress limitation as stated in Section IV-C. With a fixed input voltage, Fig. 22 shows experimental inductor current waveforms with the designed modulation and one with minimal current stress. The inductor current shown in Fig. 22(a) is obtained with the modulation scheme designed by the current stress minimization method in Section IV-A, with which the minimal current stress among all types of modulation schemes is obtained. The inductor current shown in Fig. 22(b) is obtained with the designed optimal modulation scheme. The current stress, equal to the maximum in the inductor’s current waveform with the designed modulation scheme, is similar to the minimal current stress shown in Fig. 22(a).

Fig. 22. Inductor current waveforms of modulation schemes with two design methods. (a) Modulation scheme designed with current stress minimization. (b) Designed optimal modulation scheme.

(a)

(b)

In Fig. 23, over the entire input voltage range in the buck- boost mode, the current stress with the designed modulation scheme is smaller than the limited current stress λi_stress* = 1.1i_stress*. The designed modulation scheme meets the current stress limitation.

Fig. 23. Current stress limitation with the proposed optimization scheme.

3) Efficiency Optimization Verifications with the Designed Modulation Scheme

Finally, the efficiency with the designed optimal modulation scheme is compared with the efficiency with the modulation scheme in reference [7], which obtained the highest efficiency among previous studies, as shown in Fig. 24. A higher efficiency for an NIBB at the buck-boost mode is achieved with the designed optimal modulation scheme. Despite of the small efficiency improvement, the fact that the designed modulation scheme with the proposed design method achieve the optimal efficiency among all of the existing modulation schemes is verified.

Fig. 24. Experimental results showing the efficiency of two optimization schemes.

With regard to the loss comparisons for each part, take V_in = 280 V as an example. Because the power losses for each part cannot be easily measured directly by experimental instruments, they are calculated by substituting experimental inductor current waveforms obtained with the designed modulation scheme and the one in [7] into the loss models in (29) - (37). Fig. 25 shows experimental inductor current waveforms with the designed modulation scheme and the one in [7], which achieves i₁, i₂, i₃ and i₄. By substituting them into loss models, the power losses for each part can be obtained and shown in Fig. 26. The power losses for each part with the designed modulation scheme are smaller than those with the modulation scheme in [7]. The same conclusions in terms of power losses and efficiency as the former simulations and loss calculations shown in Fig. 18 and Fig. 19 are obtained. In addition, the shapes of experimental efficiency and power loss results in Fig. 24 and Fig. 26 are consistent with those of the simulation and calculated results in Fig. 18 and Fig. 19. This validates the provided mathematical formulations for the loss evaluation.

Fig. 25. Experimental inductor current waveforms with the: (a) Modulation scheme in [7]. (b) Designed modulation scheme.

(a)

(b)

Fig. 26. Experimental power losses comparisons between two modulation schemes.

Efficiency optimization and current stress limitation over the entire input voltage range of the buck-boost mode are both realized with the designed optimal modulation scheme by the proposed design methodology.

VI. CONCLUSION

Non-inverting Buck-Boost converters have been extensively used in wide-input-voltage-range applications. To overcome the drawback of low-efficiency in the buck-boost mode, this paper tries to reduce the total loss through improving the modulation scheme. A general phase-shift modulation scheme for a NIBB is proposed in this paper. Furthermore, an offline design method for the optimal modulation optimization scheme over the entire input voltage range at the buck-boost mode is provided, with converter efficiency optimized and switch current stress limited. The proposed design method has three merits.

1) The general phase-shift modulation considers all of the possible situations of the switching states, which is suitable for both two-switch and four-switch NIBBs.

2) Analytic current expressions for all of the possible scenarios are derived completely so the current stress and the converter efficiency can be analyzed and calculated in detail.

3) With the designed optimal modulation scheme, both efficiency optimization and current stress limitation over the entire input voltage range are realized.

The feasibility and validity of the whole design process have been confirmed by experimental results.

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Bingqing Shi was born in China, in 1993. She received her B.S. degree in Electrical Engineering from Tsinghua University, Beijing, China, in 2015, where she is presently working towards her Ph.D. degree in Electrical Engineering. Her current research interests include PV generation, storage management, DC-DC converters modulation schemes and control theory, which includes predictive control, self-correction control, sliding mode control and parameter identification algorithms.

Zhengming Zhao received his B.S. and M.S. degrees in Electrical Engineering from Hunan University, Changsha, China, in 1982 and 1985, respectively. He received his Ph.D. degree from Tsinghua University, Beijing, China, in 1991. In 1991, he joined the Department of Electrical Engineering, Tsinghua University. From 1994 to 1996, he was a Postdoctoral Fellow at Ohio State University, Columbus, OH, USA. After that, he spent one year as a Visiting Scholar at the University of California, Irvine, CA, USA. He is presently working as a Professor in the Department of Electrical Engineering, Tsinghua University. His current research interests include high-power conversion, power electronics, motor control, and solar energy applications. Prof. Zhao is the Vice President of the Beijing Power Electronics Society and a Chairman of the IEEE Power Electronics Society Beijing Chapter.

Kai Li received his B.S. degree in Electrical Engineering from Wuhan University, Hubei, China, in 2011, and his Ph.D. degree from Tsinghua University, Beijing, China, in 2017. He was a Visiting Scholar at the Center for Power Electronics Systems, Virginia Tech, Blacksburg, VA, USA, from 2013 to 2015. He was a Post-Doctoral Fellow at Tsinghua University, Beijing, China, from 2017 to 2019. In 2019, he joined School of Electrical Engineering, Beijing Jiaotong University. His current research interests include solid-state transformers, modular multilevel converters and PWM strategies.

Gaohui Feng received his B.S. and M.S. degrees from the Mechanical Engineering College, Shijiazhuang, China, in 2002 and 2005, respectively. He received his Ph.D. degree in Electrical Engineering from Tsinghua University, Beijing, China, in 2017. He is presently working as an Assistant Professor in the Department of Electrical Engineering, Tsinghua University. His current research interests include power electronic transformers, dc-dc converters, solar energy applications and stored energy applications.

Shiqi Ji received his B.S. and Ph.D. degrees in Electrical Engineering from Tsinghua University, Beijing, China, in 2010 and 2015, respectively. He is presently working as a Research Assistant Professor in CURENT, University of Tennessee, Knoxville, TN, USA. His current research interests include semiconductor device modeling, medium- voltage and high-power converter designs, high voltage SiC device characterization, application techniques and grid-connected converter design.

Jiayue Zhou was born in Guangzhou, China, in 1997. She is presently working towards her B.S. degree in Electrical Engineering at Tsinghua University, Beijing, China. Her current research interests include predictive control algorithms based on incremental motor models and the extended-Kalman- filter-based permanent magnet flux estimation method.