https://doi.org/10.6113/JPE.2019.19.5.1171
ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718
Comparison of Capacitor Voltage Balancing Methods for 1GW MMC-HVDC Based on Real-Time Digital Simulator and Physical Control Systems
Jun-Min Lee*,**, Jung-Woo Park**, Dae-Wook Kang**, Jong-Pil Lee**,Dong-Wook Yoo**, and Jang-Myung Lee†
†,*Department of Electrical Engineering, Pusan National University, Pusan, Korea
**Korea Electrotechnology Research Institute, Changwon, Korea
Abstract
Modular Multilevel Converter (MMC)-based HVDC power transmission using a real-time simulator is one of the key technologies in power electronics research. This paper introduces the design methodology of a physical MMC-HVDC control system based on a Field-Programmable Gate Array (FPGA), which has the advantage of high-speed parallel operation, and validates the accuracy of MMC-HVDC control when operated with a Real-Time Digital Simulator (RTDS). Finally, this paper compares and analyzes the characteristics of capacitor voltage balancing methods such as Nearest Level Control (NLC), NLC with a reduced switching frequency, and tolerance band modulation implemented on physical control system.
Key words: FPGA, Hardware-in-the-loop simulation, HVDC, Modular-multilevel converter, Real time digital simulator
Manuscript received Dec. 14, 2018; accepted May 29, 2019
Recommended for publication by Associate Editor Younghoon Cho.
†Corresponding Author: jmlee@pusan.ac.kr Tel: +82-51-510-2378, Fax: +82-51-510-5190, Pusan Nat’l University
*Dept. of Electrical Eng., Pusan Nat’l University, Korea
**Dept. of Power Conversion and Control Research Center, Korea Electrotechnology Research Institute, Korea
Ⅰ. INTRODUCTION
The development of voltage source converter type high voltage transmission systems is becoming an important technology in the power transmission industry [1]. DC transmission is economical because the insulation level of the line is low. In addition, it has the effect of dividing the power system and is advantageous in terms of power loss at long distances when compared to AC transmission. In particular, since it has high controllability, it is possible to apply various control methods suited to the characteristics of AC systems [2]. Therefore, it is expected that more HVDC control methods will be studied in the future. However, in order to build HVDC transmission systems, initial simulations are needed to verify a system because they require a huge amount of money. The simulation method is largely divided into two different methods. The first is the Software-In-the-Loop Simulation (SILS) method, which designs the controller, topology and various devices by software-based design. The second is the Hardware-In-the-Loop Simulation (HILS) method, which interfaces with a real-time simulation device to create a physical control system and to approximate an actual system at the hardware level. These two methods each have a variety of software tools and perform various functions for the purpose of the simulation. HILS consists of a precision real-time simulation device that has been proven in the power industry, and a CAD program that designs it. In addition, the real-time simulation device and the physical control system must be configured to interface with each other. Therefore, this paper introduces a method to implement the HILS of a Back-To-Back type 1GW MMC-HVDC by designing a real MMC control device based on a FPGA, and verifies the performance of controller [3]. In order to construct the HILS, it is necessary to perform precise verification of each part while constructing the interface between the real-time simulation device and the physical control system. These parts can be divided into three categories: platform, communication and algorithm. It is necessary to collect data based on many experiments to see how all of the parts react under various conditions. The platform should be designed by defining the hierarchy of the controllers. In addition, a proper communication system should be constructed for mutual cooperation among these layers. Furthermore, it is necessary to consider the timing of the communications between layers. Experiments should also be conducted to find alternatives to the packet loss that can occur in each segment. Once the hardware design of the HILS system has been completed, software-based alternatives to the various problems that arise in the controller's internal computing system should be prepared. In order to verify the performance of the designed controller, s low voltage ride through (LVRT) control test is conducted under unbalanced voltage conditions in the grid connection [4]. When the AC grid voltages are unbalanced, circulating current suppression algorithms should be selected according to the computation speed and the calculation performance in the actual controller. In addition, various capacitor voltage balancing methods are implemented as FPGA logic, which can operate in parallel [5]. Furthermore, a method to design a 1GW MMC HVDC power converter with optimal switching frequency and ripple is introduced. A low-level controller, such as capacitor voltage balancing, must be designed in consideration of the timing of the control logic because it must be implemented in the FPGA for high-speed parallel operation. Since HILS can identify and solve various problems that can occur in real systems, it can be the most reliable verification method before making an actual large capacity MMC-HVDC.
Ⅱ. MODULAR MULTILEVEL CONVERTER
A. Topology
Fig. 1 shows the structure of a grid-connected three-phase MMC consisting of six arms [6]. Each phase has two arms. Each arm has one inductor, one resistor, and N submodules in the form of a half-bridge connected in series. Each submodule consists of one capacitor and two IGBTs, and controls the ON / OFF state of the switches T1 and T2 to produce a desired AC or DC voltage. T1 and T2 are complementary to each other. When T1 is ON and T2 is OFF, the capacitor is charged or discharged depending on the direction of the arm current. Conversely, when T1 is OFF and T2 is ON, the capacitor is bypassed and the voltage value remains unchanged. In other words, the control method of the MMC is affected by the switching pattern of the submodules [7].
Fig. 1. Topology of an MMC.
Fig. 2. Three-phase equivalent circuit of an MMC.
To balance the voltages of the upper and lower arms of each phase, the voltage across the submodules in each arm must be shared. Therefore, the voltage reference must be calculated to select a number to switch the submodules in eacharm [8]. Fig. 2 shows an equivalent circuit of a MMC. State equations are obtained based on this equivalent circuit and the voltage references of each arm are finally obtained as follows [9]:
(1)
(2)In these equations, 
means the a, b, c phase, and 
is the DC voltage. In addition, 
means the upper arm voltages and 
means the lower arm voltages. 
means resistance of each arm, and 
means inductance of each arm. Equations (1) and (2) are the voltage equations of the upper and lower arms for 
, which was defined as the phase voltages.
(3)
(4)
(5)If equations (1) and (2) are subtracted and rearrange with equation (3), which was defined as the imaginary inner alternating voltages 
in Ref. [10], and equation (4), which was defined as the phase currents 
, equation (5) is obtained.
(6)
(7)If equations (1) and (2) are summed and rearrange with equation (6), which was defined as the difference currents 
, equation (7) is obtained. Hence, 
, which was defined as the total sum of the internal voltages of each phase, is given as:
(8)By rearranging equations (3) and (8), 
, which was defined as the voltage references of the upper arm, and 
, which was defined as the voltage references of the lower arm, can be obtained as follows:
(9)
(10)As shown in Fig. 3, the control system of this paper is classified into a high-level control that obtains voltage references through power control, current control and circulating current suppression control, and a low-level control that performs voltage balancing by receiving the voltage references.
Fig. 3. Control system of a MMC.
B. Specification Design
To determine the power transmission capacity of an HVDC system, the number of SMs and the control period must be determined first. The number of SMs is determined by the DC transmission capacity and the capacitor capacity of a SM. The control period should be designed so that the voltage level obtained by the voltage references can be changed by one level per cycle. In addition, it should be designed so that both high-level control and low-level control can be operated within a control period.
Fig. 4. Time step for a voltage level.
In other words, as shown in Fig. 4, setting the control period faster than the minimum value of 
results in a voltage level with a high resolution.
(11)The number of SMs and the control period according to the transmission capacity were determined by equation (11) [11] as shown in Table I.
| Power |
No.SM / Valve |
Cycle |
| 100MW |
50 |
80usec |
| 200MW |
100 |
40usec |
| 400MW |
200 |
20usec |
| 1GW |
400 |
10usec |
Ⅲ. HARDWARE-IN-THE-LOOP SIMULATION
A. Implementation of a 1GW MMC-HVDC Controller
A Hardware-In-the-Loop Simulation (HILS) between a FPGA-based KERI controller and a Real-Time Digital Simulator (RTDS) was built as shown in Fig. 5. The hierarchical structure of the control device is configured as shown in Fig. 6, and a Grand Master Clock (GMC) is used as the reference clock to synchronize all of the layers.
Fig. 5. HILS configuration of a 1GW MMC-HVDC.
Fig. 6. Hierarchy of a KERI control device.
The high-level controller is a Station Controller (SC) that implements a high-level control algorithm by receiving analog signals such as the grid voltage, grid current, DC-link voltage and DC current output from the GTAO mounted on the RTDS. Below the SC, there are 6 VC-MCs (Valve Controller - Master Controller) that control the 3-phase upper and lower valves to implement the low-level control algorithm by receiving the Sub-Module (SM) capacitor voltage output from the MMC Support Unit (MSU). In addition, there are 6 Interface Boards (IB) to intercommunicate the packets between the VC-MCs and the RTDS. The communication between each controller is based on Xilinx's Aurora Protocol and consists of 5 Gbps high-speed serial communication.
The full-duplex communication packets between the 1 GW MMC HVDC controller and the RTDS are shown in Fig. 7. In the RTDS, the arm voltages, arm currents and up to 512 SM capacitor voltages transfer at the 2-ports over 4 times with a time step of 2.5usec. In this case, the number of the SM capacitor voltages is set to 432. These packets are processed by the IBs, divided into 3-ports, and sent to the VC-MCs to implement the sorting algorithm. The arm currents are sent to the SC and used as data for operating the high-level control algorithm. When the voltage references are calculated in the SC, the number to turn on/off the SMs are sent to the VC-MCs. Based on the number to turn on/off the SMs, the VC-MCs generate gate pulse signals and send them to the IBs through the 3-ports. In addition, the IBs processe packets according to communication packets of the RTDS as 2-ports and send them to the RTDS.
Fig. 7. Full-duplex communication packets between a 1GW MMC control device and a real-time simulator.
The number of SMs should be the highest priority for designing the controller. Then the control period should be determined. When the control period is determined, the communication time, the amount of the algorithm computation processed by the CPU, and all of the Intellectual Properties (IP) designed on the FPGA logic must be calculated and processed within the control period. A 1GW MMC-HVDC control device has 432 SMs. Therefore, each IP in the FPGA is designed based on 432 FIFO registers and 432 comparators.
B. RTDS Design
The modeling of an MMC-HVDC in a RTDS can be designed with a program called RS-CAD for the circuit design of a 1 GW system.
The primary and secondary voltage of the transformer were set to 528 kV and 460 kV. The capacity of the SM capacitors was set to 10 mF, and the inductance of the arm reactors was set to 50 mH as shown in Table II.
| Quantity |
Value of Unit |
| Max Active Power |
1000MW |
| Rated DC Link Voltage |
±500kV |
| Rated DC Current |
1000A |
| Power Factor |
0.95 |
| Primary Voltage of Transformer |
528kV |
| Secondary Voltage of Transformer |
460kV |
| No. of SM per Arm |
432 |
| Inductance per Arm Reactor |
50mH |
| Capacity per SM |
10mF |
| Control Cycle |
10usec |
It can be seen in Fig. 8 that AC 460 kV is output from the secondary voltage of the transformer of the rectifier side, and that voltage control is performed so the DC-Link voltage converges to 1,000 kV at no load. The figure also shows that the control device and RS-CAD are well designed.
Fig. 8. RUNTIME of a 1GW MMC-HVDC HILS.
Ⅳ. CAPACITOR VOLTAGE BALANCING
A. Parallel Sorting Network
Parallel operation using an FPGA is indispensable for calculating high-level control and low-level control within 10usec. Quick sorting, which is one of the fast sorting algorithms, performs recursive operations. Parallel operation of a recursive function based on FPGA hardware logic is complicated and difficult to sort in a desired time [12]. Therefore, in order to design a sorting algorithm based on a FPGA, it is necessary to select one of the most basic sorting methods, even though it is slow, like bubble sorting that is not implemented as the recursive. As can be seen from the time complexity 
, the bubble sorting algorithm has an operation speed corresponding to worst case, where the comparison operation increases by the square of the number of data to be sorted [13]. However, if parallel sorting is performed by an even-odd bubble sorting network, as shown in Fig. 9, it is possible to complete the sorting with only 8 parallel comparisons of 8 data. In addition, the computation time can be greatly reduced when compared with a single CPU. In other words, in order to sort 
data, the sorting is completed with only 
parallel comparison operations [14].
Fig. 9. Even-odd bubble sorting network.
In order to implement this sorting network on hardware, it should have simultaneous access to Index 0-1, Index 2-3, Index 4-5 and Index 6-7. Then, in the next cycle, Index 1-2, Index 3-4 and Index 5-6 are accessed at the same time because access to same memory is not possible at the same time.
Therefore, as shown in Fig. 10, the data of the index addresses of two adjacent submodules that are not simultaneously accessed are read in the first cycle. After the data is compared in the second cycle, it is written to the index address of the adjacent submodules that are not simultaneously accessed in the third cycle. In other words, the sorting of 432 capacitor voltages is completed in only 434 clocks. Since the operation clock is set to 200 MHz, it is 5nsec per clock. As a result, the calculation is completed in only 2.17 usec. Then, since the sorting for the capacitor selection is performed in the low- level control, a calculation time of 2.17 usec is required once again.
Fig. 10. Logic of parallel sorting.
As shown in Fig. 11, when the SC receives grid voltage and grid current data and computes the high-level control, the VC-MC starts simultaneously sorting the sub-module capacitor voltages. In the high-level control, the voltage reference is calculated and transferred to the VC-MC, which performs low-level control using the sorted submodule capacitor voltages and six arm currents. This entire process is completed within 10usec.
Fig. 11. Flowchart of the algorithm operation.
B. Modulation Methods for MMCs
Fig. 12 shows the phase shift carrier PWM method and the nearest level control method, which are widely used as capacitor voltage balancing methods in MMCs [15]. By using these the two methods, the number of submodules to turn on or off (
) is obtained and the capacitor selection is implemented.
Fig. 12. Modulation Methods for MMCs.
The phase shifted carrier method is the most basic method to implement PWM by comparing the voltage reference with carriers. However, as the number of SMs increases, the number of also carriers increases. As a result, pulse modulation occurs faster than the control period, and may not be recognized. In other words, when the number of carriers increases, 
is not calculated precisely, which can increase the DC-LINK voltage ripple. The nearest level control method is a modulation method that determines 
by rounding the voltage reference divided by the DC-LINK voltage. This method has a higher switching frequency. However, the submodule capacitor voltage ripples and circulating current ripples are better since the voltage level is constantly increased or decreased in every cycle regardless of the number of SMs [16]. Since 432 SMs were selected, this paper used the NLC method which experiences no adverse effect from increasing the number of SMs.
C. Capacitor Selection
The capacitor voltage balancing methods include full sorting, Reduced Switching Frequency (RSF), and tolerance band modulation. The full sorting method sorts every cycle, and turns on the SM with the smallest capacitor voltage when charging, and turns on the SM with the largest capacitor voltage when discharging [17]. The RSF method first turns on the SM with the smallest capacitor voltage among the remaining SMs except for the SM that was turned on in the previous state. Conversely, when discharging, the SM having the largest capacitor voltage among the remaining SMs, except the SM turned on in the previous state, is turned on [18]. The tolerance band method creates a band for the capacitor voltage waveform using an average method and an individual capacitor method [19].
Ⅴ. EXPERIMENTAL RESULTS
Fig. 13 shows the transient state for a full load of the MMC-HVDC converter system between the physical controller and the RTDS. Station #1 and station #2 mean the rectifier station and the inverter station, respectively. First, the circuit breakers of each station are closed to start pre-charging. Then the rectifier station starts to control and boosts the dc voltage. Finally, 1 GW of power is transmitted by controlling a load current of 1,000 A at the inverter station.
Fig. 13. Experimental characteristics under a full load.
Then the circulating current suppression control algorithm using a Proportional-Integral (PI) controller in the d-q frame, and the circulating current suppression control algorithm using a Proportional-Resonant (PR) controller in the a-b-c frame were implemented [20]. In order to verify the controller performance of a converter connected to the grid, the characteristics of the Low Voltage Ride Through (LVRT) for the two circulating current suppression control algorithms were compared when a grid voltage imbalance occurred.
As shown in Fig. 14, the PR controller in the a-b-c frame suppresses the circulating current better with less computation time when compared with that in the d-q frame when a low voltage of 95 % occurs in each phase.
|
(a) |
|
(b) |
Methods for balancing submodule capacitor voltages in MMCs include full sorting, reduced switching frequency type sorting, and tolerance band modulation. These methods correspond to low-level control in VC-MCs, and the logic is operated within a control period by parallelization based on a FPGA. The DC-link voltage ripples and circulating current characteristics are different for each of these methods.
Fig. 15 shows the waveform of eight capacitor voltages for the full sorting method. The voltage ripple is the smallest and the switching frequency is the greatest because it is a method of updating the capacitor voltage by sorting every cycle. As shown in Fig. 16, the full-sorting method can confirm that the circulating current is small. Since the switching frequency is affected by the number of control cycles and the number of submodules, it is confirmed that the full sorting method has a switching frequency of about 6.4 kHz in a system having a control period of 10 usec and 432 submodules.
Fig. 15. Capacitor voltage of the full sorting method.
Fig. 16. Circulating current of the full sorting method.
Fig. 17 shows the reduced switching frequency sorting method, in which the switch is turned on / off according to the condition of the previous state. In other words, when charging, the submodule turns on the submodule where the voltage is the lowest and the previous state is off. On the other hand, when discharging, the submodule turns off the submodule where the voltage is the highest and the previous state is on. Therefore, the capacitor voltage balancing method has the smallest switching frequency while having the greatest ripple. As shown in Fig. 18, the magnitude of the circulating current is large. In this system, the RSF method has a switching frequency of about 55 Hz.
Fig. 17. Capacitor voltage of the RSF method.
Fig. 18. Circulating current of the RSF method.
Fig. 19 shows waveforms that balance the submodule capacitor voltage band between 2.1 kV and 2.5 kV by limiting the minimum and maximum values of the capacitor voltage with the cell tolerance band method. In addition, Fig. 20 shows CTB circulating current waveforms with a band between 2.1 kV and 2.5 kV. In this system, the CTB method has a switching frequency of about 135Hz when the capacitor voltage is set to a band from a maximum of 2.5 kV to a minimum of 2.0 kV.
Fig. 19. Capacitor voltage of the CTB method.
Fig. 20. Circulating current of the CTB method.
Fig. 21 shows the average tolerance band method, which calculates the average of the submodule capacitor voltages, and generates a 4 % band based on this average. Fig. 22 shows ATB circulating current waveforms with a 4 % band. In this system, the ATB method has a switching frequency of about 190 Hz when the capacitor average voltage is set to a 4 % band.
Fig. 21. Capacitor voltage of the ATB method.
Fig. 22. Circulating current of the ATB method.
As can be seen from the two schemes, the tolerance band method is a balancing technique that can achieve a tradeoff between the DC-link voltage ripple and the switching frequency by varying the band. Therefore, it is a good balancing method for multilevel converters of GW class or higher using many submodules.
Ⅵ. CONCLUSIONS
This paper provides a method to implement a 1GW MMC-HVDC HILS system using a RTDS and a physical control system. This HILS system was able to verify the performance of the controller for LVRT characteristics by testing for system imbalance or various fault conditions before simulating the actual experiment in a testbed. In addition, it is shown that it is a good simulation device to compare the characteristics of each algorithm by implementing various submodule capacitor voltage balancing methods. MMC-HVDC systems should focus on the control cycle and switching frequency when the number of submodules increases. By using an FPGA's high-speed operation and parallel processing, it is possible to design 1 GW or higher MMC control devices.
ACKNOWLEDGMENT
This work was supported by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No.2017931010060).
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Jun-Min Lee was born in Busan, Korea. He received his B.S. degree in Electrical Engineering from Kyungsung University, Busan, Korea, in 2011; and his M.S. in Electrical Engineering from Pusan National University, Busan, Korea, in 2013, where he is presently working towards his Ph.D. degree in Electrical Engineering. Since 2015, he has been with Korea Electrotechnology Research Institute (KERI), Changwon, Korea. His current research interests include intelligent control systems, digital signal processing, HILS, the control of HVDCs, multilevel converters, and the application of power electronics to power systems.
Jung-Woo Park was born in Chungnam, Korea. He received his B.S. and M.S. degrees in Electronics Engineering from Chungnam National University, Daejeon, Korea, in 1986 and 1988, respectively. He received his Ph.D. degree in Electrical Engineering from Kyungpook National University, Daegu, Korea. Since 1998, he has been a Principal Researcher with the Korea Electrotechnology Research Institute (KERI), Changwon, Korea. His current research interests include the control of HVDCs, multilevel converters, wind energy generation, and renewable energy.
Dae-Wook Kang received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from Hanyang University, Seoul, Korea, in 1998, 2000 and 2004, respectively. Since 2004, he has been a Principal Researcher with the Korea Electrotechnology Research Institute (KERI), Changwon, Korea. His current research interests include the control of HVDCs, multilevel converters, multi-terminal DC transmission, renewable energy, and the application of power electronics to power systems.
Jong-Pil Lee received his B.S. degree in Control and Instrumentation Engineering, and his M.S. and Ph.D. degrees in Electrical Engineering from Korea University, Seoul, Korea, in 1997, 1999 and 2012, respectively. From 1999 to 2005, he was a Senior Researcher with the Electric and Hybrid Vehicle Research Division, Hyundai Heavy Industries, Ulsan, Korea. He is presently working as a Team Leader with the Power Conversion and Control Research Center, Smart Grid Research Division, Korea Electrotechnology Research Institute (KERI), Changwon, Korea. His current research interests include photovoltaic power conditioning systems (PCSs), permanent-magnet synchronous generator wind turbine PCSs, distributed power generation systems, and power conversion for HVDC systems.
Dong-Wook Yoo received his B.S. degree in Electrical Engineering from Sungkyunkwan University (SKKU), Suwon, Korea, in 1983; his M.S. degree in Electrical Engineering from Yonsei University, Seoul, Korea, in 1985; and his Ph.D. degree in Power Electronics from SKKU, in 1997. He is presently working at the Korea Electrotechnology Research Institute (KERI), Changwon, Korea, where he became a Researcher in 1985, a Senior Researcher in 1989, and a Principal Researcher in 1997. Since 1997, he has been a Team Leader in the Power Electronics Laboratory, the Renewable Energy Laboratory, and Power Conversion Control Research Center, KERI. In addition, he is an Executive Director with the HVDC Research Division, KERI. He is presently serving as a Vice President in KERI. Dr. Yoo is a member of the IEEE Power Electronics Society, IEEE Industry Applications Society, The Korean Institute of Power Electronics (KIPE), and The Korean Institute of Electrical Engineers (KIEE). He was a Committee Member of KIEE from 2005 to 2006, and of KIPE from 2009 to 2010. In 2009, he became the Chairman of a KIPE conference. He was a corecipient of a Best Paper Award at the 2002 Annual Conference of the IEEE Industrial Electronics Society, and a Best Paper Award at the 2007 International Conference on Power Electronics, Daegu, Korea.
Jang-Myung Lee received his B.S. and M.S. degrees in Electronic Engineering from Seoul National University, Seoul Korea, in 1980 and 1982, respectively. He received his Ph.D. degree in Computer Engineering from the University of Southern California (USC), Los Angeles, CA, USA, in 1990. Since 1992, he has been a Professor in the Intelligent Robot Laboratory, Pusan National University, Busan, Korea. Dr. Lee is a former Chairman of the Research Center for Special Environment Navigation/Localization. He was the President of the Korean Robotics Society in 2010. His current research interests include intelligent robotic systems, transport robots, and intelligent sensor and control algorithms.