https://doi.org/10.6113/JPE.2019.19.6.1337

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Phase-Shift Triple Full-Bridge ZVZCS Converter with All Soft Switched Devices

Junjie Zhu^{*}, Qinsong Qian^{*}, Shengli Lu^{*}, and Weifeng Sun^{†}

^{†,*}National ASIC System Engineering Research Center, Southeast University, Nanjing, China

Abstract

This paper proposes a Phase-Shift Triple Full-Bridge (PSTB) Zero-Voltage Zero-Current-Switching (ZVZCS) converter with a high switching frequency and high efficiency. In the proposed converter, all three bridge legs are shared leading-legs, and all three transformers work in the Discontinuous Conduction Mode (DCM). Thus, all of the switches and diodes in the PSTB ZVZCS can be soft switched. Moreover, since all of the transformers can pass energy from the primary-side to the secondary- side when their primary-side currents are not zero, there is no circulating current. As a result, the PSTB ZVZCS converter can achieve a high efficiency at high operating frequencies. A theoretical analysis and the characteristics of the proposed converter are presented and verified on a 1MHz 200~300V/24V 1.2kW hardware prototype. The proposed converter can reach a peak efficiency of 96.6%.

Key words: Phase-shift triple full-bridge, Shared legs, Soft switched, ZCS, ZVS

Manuscript received Jun. 5, 2018; accepted Nov. 23, 2018

Recommended for publication by Associate Editor Jongwon Shin.

^{†}Corresponding Author: swffrog@seu.edu.cn Tel: +86-025-83795811, Southeast University

^{*}National ASIC System Eng. Research Center, Southeast Univ., China

Ⅰ. INTRODUCTION

Higher switching frequencies and higher efficiencies are the eternal pursuits of switching converters. Several topologies with soft-switched devices have been proposed to increase efficiency when the switching frequency is high.

Phase-shift full-bridge (PSFB) converters have received a lot of attention for high-power applications [1], [2]. All of the leading-leg switches in a PSFB can be turned on with ZVS [3]. However, realizing ZVS of lagging-leg switches presents many problems [4]. To solve these problems, Zero-Voltage Zero- Current-Switching (ZVZCS) PSFB converters [5]-[7] have been proposed. In addition, basing on the “shared leg” technique, several converters have been proposed in [8-10]. Nevertheless, there are circulating currents in all these converters. The circulating currents result in circulating loss and limit the efficiency of these converters.

The authors of this paper proposed a PSTB converter to solve the lagging-leg problems and reduce the circulating loss [11]. In the PSTB converter, there are three bridge-legs and three full-bridges. Each bridge-leg is shared by two full-bridges. One bridge-leg is the leading leg of one full-bridge, and the lagging-leg of the other full-bridge. Thus, in the PSTB converter, all of the primary-side switches can easily realize ZVS. Nevertheless, there are three output inductances in the PSTB converter. Thus, all three transformers in the PSTB converter work in the CCM. Then, the secondary-side diodes cannot be turned off with ZCS.

This paper proposes a PSTB ZVZCS converter based on the PSTB converter in [11]. Thus, ZVS of all the primary- side switches in the proposed converter can be easily realized. When compared with the PSTB converter, the proposed converter removes all three output inductances. As a result, all three of the transformers in the proposed converter can work in the DCM, and all of the secondary-side diodes can realize ZCS. Thus, the power density, switching frequency and efficiency of the proposed converter can be significantly improved. Furthermore, there is no circulating current in both of the working modes. A 1MHz 1.2kW hardware prototype has been built to verify the characteristics of the proposed converter.

By removing the output inductances, the proposed converter is similar to some three-phase and DAB (Dual Active Bridge) converters [12]-[15]. Nevertheless, the three- phase converter in [12] and the DAB converter in [13] utilize the phase-shift between the primary-side switches and the secondary-side switches to regulate the output voltage. Thus, the secondary- side switches in [12] and [13] cannot be turned off with ZCS. The converters proposed in [14] and [15] use the phase-shift between primary-side legs to regulate the output voltage, and there is no shared leg. Thus, the lagging- leg switches in [14] and [15] can be turned on with ZVS. However, they can only be turned off with ZCS. Since realizing ZVS results in less switching loss than realizing ZCS, the proposed converter should have less switching loss than all of these converters.

This paper is organized as follows. Section II presents the circuit configuration and detailed operation principle of the power stage. Section III analyzes some detailed features and characteristics. In Section IV, a 1.2kW hardware converter prototype has been designed, built and tested to verify the validity and performance of the proposed circuit. Finally, some conclusions are presented in Section V.

Ⅱ. CIRCUIT DESCRIPTION AND OPERATION PRINCIPLE

Fig. 1 shows the circuit configuration of the proposed converter, which includes a triple full-bridge. The triple full- bridge topology consists of three shared legs (including six switches, S_{1}-S_{6}), three center-tapped transformers (TR1-TR3) and three center tapped rectifiers. C_{1}-C_{6} are the output capacitances of the switches. L_{lk1}-L_{lk3} are the leakage inductances of TR1-TR3. L_{m1}-L_{m3} are the magnetizing inductances of TR1-TR3. The turns ratios of TR1-TR3 are k_{1}:1:1, k_{2}:1:1 and k_{3}:1:1. The secondary- sides of the transformers connect with six power diodes (D_{1}-D_{6}) and an output capacitances C_{o}. The load resistance is R_{L}.

Fig. 1. Circuit diagram of the proposed converter.

In the full-bridge of TR1, the leading-leg is made up of S_{1} and S_{2}, and the lagging-leg is made up of S_{3} and S_{4}. The full-bridge of TR2 includes S_{3} and S_{4} as leading-leg, and S_{5} and S_{6} as lagging-leg. In the full-bridge of TR3, S_{5} and S_{6} represent the leading-leg, while S_{1} and S_{2} represent the lagging-leg.

According to the circuit diagram of the proposed converter, there are the following relationships in all of the working modes.

1) According to Kirchhoff’s laws, v_{AB}+v_{BC}+v_{CA}=0.

2) The voltages across the magnetizing inductances of TR1, TR2 and TR3 are v_{1}, v_{2} and v_{3}.

3) Assume that L_{m1}- L_{m3} are large enough, and that the primary-side magnetizing currents are nearly zero. The current through the primary-sides of TR1, TR2 and TR3 are i_{p1}, i_{p2} and i_{p3}.

4) , n=1, 2, 3.

5) All of the primary-side switches S_{1}-S_{6} have the same switching frequencies.

6) The switches of the same bridge leg have the same conducting times.

7) The output capacitors of the switches S_{1}-S_{6} are expressed as C_{oss}=C_{1}=C_{2}=C_{3}=C_{4}=C_{5}=C_{6}.

8) The parasitic capacitors of the diodes D_{1}-D_{6} are ignored.

The behavior of the proposed converter is analyzed as follows. The proposed converter has two different working modes depending on the output power. When the load is light, the proposed converter works in the light mode. Otherwise, it works in the heavy mode. The boundary between the light mode and the heavy mode is proposed in Section III, Part A.

A. The Light Mode

The light mode goes through twelve stages during a half-switching cycle when the load is light. Equivalent operation circuits for the different stages are shown in Fig. 2, and key waveforms are shown in Fig. 3. In Fig. 2 and Fig. 4, the colored lines show the real current following directions to explain the stages. In Fig. 3 and Fig. 5, the current following directions are the same as those in Fig. 1.

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(e) |

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Fig. 3. Key waveforms. (a) In the proposed converter in the light mode. (b) Enlarged from t_{0} to t_{12}.

(a) |

(b) |

(c) |

(d) |

(e) |

(f) |

(g) |

(h) |

(i) |

(j) |

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(l) |

Fig. 5. Key waveforms in the proposed converter in the heavy mode.

Stage 1 [t_{0}<t<t_{1}]: Before t_{0}, S_{3} and S_{6} are on, and the other primary-side switches are off. Both i_{p1} and i_{p3} are below zero, and only i_{p2} is above zero. Since |i_{p1}|-|i_{p3}| is above zero, the anti-parallel diode of S_{1} is on.

At t_{0}, S_{1} has been turned on with ZVS. During this interval, v_{AB} is equal to zero, v_{BC} maintains V_{in}, and v_{CA} maintains –V_{in}. All of the transformers pass energy from the primary-side to the secondary-side. Thus, D_{2}, D_{3} and D_{6} are conducted. There are the following relationships.

This stage ends when i_{p1} reaches zero.

Stage 2 [t_{1}<t<t_{2}]: At t_{1}, the current through D_{2} which is equal to k_{1}|i_{p1}| reaches zero. As a result, D_{2} has been turned off with ZCS. During this stage, v_{1} equals zero, and there is no current through TR1. Thus, i_{p1} maintains zero.

Stage 3 [t_{2}<t<t_{3}]: At t_{2}, S_{3} is turned off. Then, the output capacitor of S_{3} is charged, and that of S_{4} is discharged.

During this stage, L_{lk1} and L_{lk2} are resonance with the output capacitances of S_{3} and S_{4}. Since the value of i_{p2} is large enough, and the period time of this interval is quite short, i_{p1 }and i_{p2} can be regarded as constant during this stage. In Section 2, to make it easier to explain the working modes, the currents through the primary-side are considered to be constant when the output capacitances of the switches are charged and discharged. Then, during this stage, v_{BC} can be calculated as equation (7).

This stage ends when v_{BC} reaches zero.

Stage 4 [t_{3}<t<t_{4}]: At t_{3}, i_{p1} starts to be above zero. Then, the current through D_{1}, which is equal to k_{1}i_{p1}, is above zero, and |i_{p2}|-|i_{p1}| is also above zero. As a result, D_{1} and the anti- parallel diode of S_{4} are on. During this stage, v_{1} maintains k_{1}V_{o}, and v_{BC} maintains zero. There are the following relationships.

Stage 5 [t_{4}<t<t_{5}]: At t_{4}, S_{4} has been turned on with ZVS. This stage ends when i_{p2} reaches zero.

Stage 6 [t_{5}<t<t_{6}]: At t_{5}, the current through D_{3} which is equal to k_{2}|i_{p2}| reaches zero. As a result, D_{3} has been off with ZCS. During this stage, v_{2} is equal to zero, and there is no current through TR2. Thus, i_{p2} maintains zero.

Stage 7 [t_{6}<t<t_{7}]: At t_{6}, S_{6} is turned off. During this stage, the output capacitor of S_{6} is charged, and that of S_{5} is discharged. The primary-side currents i_{p2 }and i_{p3} are considered to be constant during this stage.

This stage ends when v_{CA} reaches zero.

Stage 8 [t_{7}<t<t_{8}]: At t_{7}, i_{p2} goes under zero. Then, the current through D_{4} which is equal to k_{2}|i_{p2}| is over zero, and |i_{p3}|-|i_{p2}| is above zero. As a result, D_{4} and the anti-parallel diode of S_{5} are on. During this stage, v_{2} is equal to –k_{2}V_{o}, and v_{CA} maintains zero. There are the following relationships.

Stage 9 [t_{8}<t<t_{9}]: At t_{8}, S_{5} has been turned on with ZVS. This stage ends when i_{p3} reaches zero.

Stage 10 [t_{9}<t<t_{10}]: At t_{9}, the current through D_{6} which is equal to k_{3}|i_{p3}| reaches zero. As a result, D_{6} has been off with ZCS. During this stage, v_{3} is equal to zero, and there is no current through TR3. Thus, i_{p3} maintains zero.

Stage 11 [t_{10}<t<t_{11}]: At t_{10}, S_{1} is turned off. During this stage, the output capacitor of S_{1} is charged, and that of S_{2} is discharged. The primary-side currents i_{p1 }and i_{p3} are also considered to be constant during this stage.

This stage ends when v_{AB} reaches zero.

Stage 12 [t_{11}<t<t_{12}]: At t_{11}, i_{p3} goes above zero. Then, the current through D_{5} which is equal to k_{3}|i_{p3}| is over zero, and |i_{p1}|-|i_{p3}| is above zero. Thus, D_{5} and the anti-parallel diode of S_{2} are on. During this stage, v_{3} maintains k_{3}V_{o}, and v_{AB} maintains zero. There are the following relationships.

B. The Heavy Mode

The heavy mode goes through twelve stages during a half-switching cycle when the load is heavy. Equivalent operation circuits for the different stages are shown in Fig. 4.

Key waveforms are shown in Fig. 5.

Stage 1 [t_{0}<t<t_{1}]: Before t_{0}, S_{3} and S_{6} are on, and the other primary-side switches are off. Both i_{p2} and i_{p3} are above zero, and i_{p1} is below zero. Thus, the anti-parallel diode of S_{1} is on.

At t_{0}, S_{1} has been turned on with ZVS. During this interval, v_{AB} is equal to zero, v_{BC} maintains V_{in}, and v_{CA} maintains –V_{in}. All of the transformers pass energy from the primary-side to the secondary-side. Thus, D_{2}, D_{3} and D_{5} are conducted. Then, v_{1} is equal to –k_{1}V_{o}, v_{2} maintains k_{2}V_{o}, and v_{3} maintains k_{3}V_{o}. During this stage, equations (4) and (5) are established, and i_{p3} decreases with a constant slope as follows.

This stage ends when i_{p3} reaches zero.

Stage 2 [t_{1}<t<t_{2}]: At t_{1}, the current through D_{5} which is equal to k_{3}|i_{p3}| reaches zero. As a result, D_{5} has been switched off with ZCS. At the same time, D_{6} is on. Then, v_{3} is equal to -k_{3}V_{o}. During this interval, equation (6) is established.

Stage 3 [t_{2}<t<t_{3}]: At t_{2}, S_{3} is turned off. During this stage, the output capacitor of S_{3} is charged and that of S_{4} is discharged. The primary-side currents i_{p1 }and i_{p2} are regarded to be constant during this stage. Thus, v_{BC} changes as follows.

This stage ends when v_{BC} reaches zero.

Stage 4 [t_{3}<t<t_{4}]: At t_{3}, i_{p1} is under zero, and i_{p2} is above zero. Then, the anti-parallel diode of S_{4} is on. During this stage, equation (9) is established, and i_{p1} increases with a constant slope as follows.

Stage 5 [t_{4}<t<t_{5}]: At t_{4}, S_{4} is turned on with ZVS. This stage ends when i_{p1} reaches zero.

Stage 6 [t_{5}<t<t_{6}]: At t_{5}, the current through D_{2} which is equal to k_{1}|i_{p1}| reaches zero. As a result, D_{2} is turned off with ZCS. At the same time, D_{1} is on. Then, v_{1} maintains k_{1}V_{o}. During this stage, equation (8) is established.

Stage 7 [t_{6}<t<t_{7}]: At t_{6}, S_{6} is turned off. During this stage, the output capacitor of S_{6} is charged, and that of S_{5} is discharged. The primary-side currents i_{p2 }and i_{p3} are also considered to be constant during this stage. Thus, v_{CA} changes as follows.

This stage ends when v_{CA} reaches zero.

Stage 8 [t_{7}<t<t_{8}]: At t_{7}, i_{p2} is above zero, and i_{p3} is under zero. Then, the anti-parallel diode of S_{5} is on. During this interval, equation (12) is established, adn i_{p2} decreases with a constant slope as follows.

Stage 9 [t_{8}<t<t_{9}]: At t_{8}, S_{5} is turned on with ZVS. This stage ends when i_{p2} reaches zero.

Stage 10 [t_{9}<t<t_{10}]: At t_{9}, the current through D_{3} which is equal to k_{2}|i_{p2}| reaches zero. As a result, D_{3} is turned off with ZCS. Then, D_{4} is on. Thus, v_{2} maintains -k_{2}V_{o}. During this interval, equation (11) is established.

Stage 11 [t_{10}<t<t_{11}]: At t_{10}, S_{1} is turned off. During this stage, the output capacitor of S_{1} is charged, and that of S_{2} is discharged. The primary-side currents i_{p1 }and i_{p3} are also considered to be constant during this stage. As a result, v_{AB} changes as follows.

This stage ends when v_{AB} reaches zero.

Stage 12 [t_{11}<t<t_{12}]: At t_{11}, i_{p1} is above zero, and i_{p3} is under zero. Then, the anti-parallel diode of S_{2} is on. During this interval, equation (14) is established, and i_{p3} increases with a constant slope as:

Ⅲ. ANALYSIS OF THE PSTB ZVZCS CONVERTER

A. Analysis of Steady-State Operation

To obtain the DC gain characteristic of the PSTB ZVZCS in different modes, the calculations are based on the following assumptions.

1) All of the transformers have the same turns ratios and the same leakage inductances, hence k=k_{1}=k_{2}=k_{3} and L_{lk}=L_{lk1}=L_{lk2}=L_{lk3}.

2) It takes no time to charge or discharge the output capacitances of S_{1}-S_{6} and the parasitic capacitors of D_{1}-D_{6}. Thus, t_{2}=t_{3}, t_{6}=t_{7}, t_{10}=t_{11}, and the voltages of v_{1}-v_{3} change in no time.

3) The turn-on and turn-off of S_{1}-S_{6} are symmetrical. As a result, t_{6}-t_{2}=t_{10}-t_{6}=T/6, and T is the time of a full-switching cycle.

4) Assume that in the light mode, t_{1}-t_{0}+t_{12}-t_{10}=t_{5}-t_{2}=t_{9}-t_{6}=t_{L}, and that in the heavy mode, t_{1}-t_{0}+t_{12}-t_{10}=t_{5}-t_{2}=t_{9}-t_{6}=t_{H.}

5) Assume that P_{L} is the output power in the light mode, and that P_{H} is the output power in the heavy mode.

Then, the DC gain characteristics of the proposed converter in different working modes can be calculated.

1) The Light Mode: The relationship between V_{in} and V_{o} in the light mode can be obtained according to the analysis in Section Ⅱ, Part A.

Depending on the relationships of the currents through the primary-sides and the secondary-sides of TR1-TR3, equation (24) can be obtained.

Then, the DC gain characteristic can be obtained.

G_{L} is the DC gain characteristic of the PSTB ZVZCS in the light mode. The range of R_{L} should make t_{L} smaller than T/6. This can also be used to judge whether the converter is in the light mode. In equation (26), if the value of R_{L} makes t_{L} larger than T/6, the converter works in the heavy mode.

The working modes can also be judged by the values of V_{in} and V_{o}. According to equation (23), where t_{L} is smaller than T/6, V_{in} should be smaller than 3kV_{o}/2. Then, the converter works in the light mode. When V_{in} is larger than 3kV_{o}/2, the proposed converter works in the heavy mode.

According to equations (23) and (24), t_{L} and P_{L} can be calculated.

2) The Heavy Mode: The relationship between V_{in} and V_{o} in the heavy mode can be obtained according to the analysis in Section Ⅱ, Part B.

According to the relationships among the currents through the primary-sides and the secondary-sides of TR1-TR3, equation (30) can be obtained.

Thus, there are the following relationships.

G_{H} is the DC gain characteristic of the PSTB ZVZCS in the heavy mode. The range of R_{L} should make t_{H} larger than zero. It can also be utilized to judge whether the converter works in the heavy mode. In equation (32), if the value of R_{L} makes t_{H} outside 0~T/6, the converter does not work in the heavy mode.

According to equations (29) and (30), t_{H} and P_{H} can be calculated.

3) Controlling the DC Gain Characteristic and the Output Power: According to equations (25), (26), (29) and (30), G_{L} and G_{H} are only decided by the value of R_{L} when the transformers and switching frequency of the converter are fixed. The on-off control method may be used to regulate the DC gain characteristic of the PSTB ZVZCS when the output load is fixed.

Assume that D is the on-time duty cycle of the converter, R_{LC} is the real load of the converter, and P_{o} is the real output power of the converter. R_{L} is the equivalent load when the converter is on, which is also the R_{L} in equations (26) and (30). P_{L} and P_{H} are the equivalent output powers when the converter is on, as in equations (28) and (34). The values of k, L_{lk} and T are fixed. For a constant voltage source, the output voltage is also fixed. When R_{LC} or V_{in} changes, D is controlled to regulate the output voltage and power. There are the following relationships.

Assume that k=4, L_{lk}=4.84uH, T=1us and V_{o}=24V. These parameters are the same as those of the converter in Section Ⅳ. Then, the relationships among P_{o}, D and V_{in} are shown in Fig. 6. From Fig. 6, it can be seen that D increases with P_{o}, and that it increases when V_{in} decreases. It can be utilized to regulate the output power and voltage. When V_{in} and V_{o} are fixed, D should be larger to make the output power higher according to equation (36) and Fig. 6.

Fig. 6. Relationships among P_{o}, D and V_{in}.

Equation (25), (26), (29) and (30) depend on many assumptions. Thus, the relationships in Fig. 6 may not be accurate in practical applications. In this situation, the relationships among P_{o}, D and V_{in} should be measured by experiments. All of these parameters can be measured by observing the oscilloscope waveforms of the converter under different working conditions.

Although the relationships among P_{o}, D and V_{in} seems complex and hard to measure, the output voltage of the converter can be regulated in a simple way. According to equation (35), when R_{LC} is fixed, R_{L} is proportional to D. Depending on equations (25), (26), (31) and (32), it can be found that no matter which mode the converter works in, V_{o} increases with R_{L}. Then, increasing D can increase the output voltage. The reverse is also true. Thus, the output voltage can be regulated by controlling the value of D.

B. Soft-Switching Conditions for the Switches of the PSTB ZVZCS

To analysis whether ZVS of the switches can be realized, the equations in Section II cannot be used. Since the primary- side currents change when the output capacitances of the switches are charged and discharged, Stage 3 in both modes should be discussed again.

1) The Light Mode: During Stage 3, i_{p1}, i_{p2} and v_{1} change. There are the following relationships.

In equation (37), the change of v_{1} during this interval is decided by the parasitic capacitance of D_{1}. Considering the change of v_{1} makes the calculation too complicate. When i_{p1} is larger, the ZVS of S_{4} becomes harder to realize. Thus, in the following calculation, the value of v_{1} is regarded as zero. If the ZVS of S_{4} can be realized when v_{1} is equal to zero, the ZVS of S_{4} can be achieved in practical applications.

Since i_{p1}(t_{2})=0, according to equations (37)-(40), v_{BC}(t) can be obtained. To make sure v_{BC} can reach zero, inequation (41) should be established.

The time needed to realize ZVS of the switches is Δt_{L}.

In Stage 4, S_{4} should not be turned on too late. The ZVS of S_{4} cannot be achieved if i_{p1} reaches i_{p2} during Stage 4. After i_{p1} reaches i_{p2}, i_{p1} starts to charge the output capacitor of S_{4} and discharge that of S_{3}. Then, the ZVS of S_{4} cannot be realized.

Assume that the dead-time is t_{d}, and t_{d}=t_{4}-t_{2}=t_{8}-t_{6}=t_{12}-t_{10}. To make sure the ZVS of switches can be realized, inequation (43) should be established according to equations (8) and (9).

In equation (43), if ∆t_{L}>kt_{L}V_{o}/V_{in}, then inequation (41) cannot be established.

If L_{lk} is large enough, inequation (41) can always be established no matter how light the load is. Nevertheless, ∆t_{L} may be too long when the load is light. When ∆t_{L} is longer than T/6, the ZVS of S_{4} cannot be realized.

To achieve ZVS when the load is very light, the assistance of magnetizing current is needed. A smaller L_{m2} can make i_{p2}(t_{2}) larger. As a result, ∆t_{L} can be shorter. Nevertheless, this method increases the conduction loss. Thus, when a high peak efficiency is needed, the value of the magnetizing inductance should be as large as possible. When the ZVS of the switches needs to be realized at a very light load, the value of the magnetizing inductance should be small enough.

2) The Heavy Mode: During Stage 3, i_{p1} and i_{p2} change. There are the following relationships, and equation (40) is still established.

According to equations (40) and (44)-(47), v_{BC}(t) can be obtained. To ensure that v_{BC} can reach zero, inequation (48) should be established.

The time required to realize the ZVS of the switches is ∆t_{H}.

In the heavy mode, S_{4} cannot be turned on too late too. When S_{4} is turned on too late, i_{p1} may reach i_{p2} during Stage 4. If this occurs, S_{4} cannot achieve ZVS for the same reason as in the light mode. To that ensure the ZVS of S_{4} can be realized in a short time, S_{4} should be turned on before i_{p1} reaches zero. Then, inequation (50) should be established.

In inequation (50), if ∆t_{H}>t_{H}, then it is in the light mode.

In the experiment part, GaN transistors are used. Since the voltage drop of the anti-parallel diode of a GaN transistor is quite large, t_{d} should be just a little longer than ∆t_{L} or ∆t_{H}. Thus, t_{d} should vary according to the load.

C. Analysis of Efficiency

The efficiency of the PSTB ZVZCS converter can be higher than those of other phase-shift converters at high switching frequencies. This is due to the following two reasons.

1) All of the switches in the proposed converter can realize ZVS, and all the diodes in it can achieve ZCS. Thus, there is little switching loss in both the switches and the diodes.

2) In the proposed converter, there is no circulating current, and the magnetizing current can be as little as possible. Thus, the conduction loss can be reduced.

According to the analysis in Section II, the transformers passes energy during all of the stages in the heavy mode. Thus, there is no circulating current in the heavy mode. In the light mode, when the transformer does not pass energy, the primary-side current of the transformer is zero aside from the magnetizing current. Then, all of the transformers can pass energy from the primary-side to the secondary-side when their primary-side currents are not zero. As a result, there is no circulating current in the proposed converter. Furthermore, the magnetizing current is not needed to realize ZVS of the switches when the load is heavy. Thus, the magnetizing current can be as little as possible. As a result, almost all of the primary-side current can pass energy to the secondary-side. Then, the conduction loss in the proposed converter can be little.

D. Analysis of Power Density

In [11], the PSTB converter has been shown to have a high power density. Since more transformers can pass more energy, the PSTB converter has a higher power density than other phase-shift converters. Three output inductors have been removed in the proposed converter. As a result, the power density of the proposed converter is higher than that of the PSTB converter. In Section 4, a 1.2kW PSTB ZVZCS converter is made to verify the high power density of the proposed converter.

Ⅳ. EXPERIMENT RESULTS AND DISCUSSIONS

A 1.2kW hardware prototype of the PSTB ZVZCS converter has been made and tested to verify the circuit operation principles. The specifications of the converter are as follows: input voltage V_{in}=200~300V, output voltage V_{o}=24V, output power P_{o}=1.2kW and switching frequency f_{s}=1MHz. The input voltage range in the experimental part is not in accord with the DC gain character range in Section III, Part A. This is because the calculated G is different from the actual conditions.

Fig. 7 shows a schematic diagram of the experimental circuit. To better validate the two working modes of the proposed converter, the three inductances L_{1}, L_{2} and L_{3} are in series with the primary-side of TR1-TR3. Then, this converter can work in the heavy mode when the output power is 1.2kW. A synchronous rectifier is used to reduce the conduction loss of the secondary-side. The switches S_{7}-S_{12} are utilized to replace the diodes D_{1}-D_{6}. As a result, S_{7}-S_{12} should be turned on when D_{1}-D_{6} are on, and turned off when D_{1}-D_{6} are off. A synchronous rectifier controller IC can be utilized to drive S_{7}-S_{12}.

Fig. 7. Schematic diagram of experimental circuit.

An ARM STM32F334R8 from ST Corporation with high resolution PWM (HRPWM) is selected to control the primary- side switches. The output voltage is sampled and compared with the reference voltage V_{ref}. V_{ref} is used to set the target output voltage, and is proportional to the target output voltage. Then, an error voltage is produced and amplified by the PID part. The timer modulates the duty cycle of the ON/OFF signal according to the error voltage. Three HRPWMs are enabled or disabled by the ON/OFF signal. The converter is on for the fixed six duty cycles one time, and then the off time is regulated to control the value of D. Thus, the on-off frequency of the converter is D/6T, where T is equal to 1us.

The circuit parameters of the converters are illustrated in Table I. A photograph of the PSTB ZVZCS converter is shown in Fig. 8. The length of the proposed converter is 53.95mm. The power density of the PSTB converter is as large as 843W/in^{3}.

Components |
Parameters |

Transformer TR1, TR2, TR3 |
FEXXOCUBE EQ18-3F46 ferrite core; Primary side series connection; Primary turns 4*1, 2.8mm*1Oz; Secondary side paralleled connection; Secondary turns 1*2, 2.8mm*2Oz; Magnetizing inductance 40uH; Leakage inductance 0.23uH |

Series Inductance L |
FEXXOCUBE ER9.5-3F46 ferrite core; turns 1*8, 4.6uH, 0.5mm* 2Oz |

Primary Switches S |
GaN System GS66504B Bottom-side cooled 650 V E-mode GaN transistor 650V, 15A. R |

Secondary Switches S |
BSC028N06LS3G 60V, 100A. R |

Output Capacitor C |
50V, 4.7uF*50 ceramic capacitor |

Fig. 8. Photograph of the PSTB converter.

Fig. 9-Fig. 11 are measured when the on time duty cycle is 100%. Thus, the measured V_{in} may be beyond the input voltage range.

(a) |

(b) |

(a) |

(b) |

(a) |

(b) |

Fig. 9 shows key waveforms of the PSTB ZVZCS converter. Fig. 9(a) is measured under the conditions of V_{in}=100V and P_{o}=120W. Fig. 9(b) is measured under the conditions of V_{in}=200V and P_{o}=1.2kW. It can be seen that waveforms of the PSTB ZVZCS converter are almost the same as those in Fig. 3 and Fig. 5. As a result, the proposed converter works in the light mode, as shown in Fig. 9 (a), and in the heavy mode, as shown in Fig. 9 (b).

Fig. 10 shows waveforms of S_{2}, S_{4} and S_{6}. In Fig. 10, v_{ds2} is the drain-source voltage of S_{2}, v_{gs2} is the gate-source voltage of S_{2}, v_{ds4} is the drain-source voltage of S_{4}, v_{gs4} is the gate-source voltage of S_{4}, v_{ds6} is the drain-source voltage of S_{6}, and v_{gs6} is the gate-source voltage of S_{6}. The dead-time of the proposed converter is set a little longer than the time needed to realize ZVS. It can be clearly seen that ZVS of all the switches in the PSTB ZVZCS converter can be realized with a full load range.

Fig. 11 shows waveforms of S_{7}, S_{9} and S_{11}. In Fig. 11, v_{ds7} is the drain-source voltage of S_{7}, v_{ds9} is the drain-source voltage of S_{9}, v_{ds11} is the drain-source voltage of S_{11}, i_{ds7} is the current through S_{7},_{ }i_{ds9} is the current through S_{9}, and i_{ds11} is the current through S_{11}. This shows that ZCS of all the secondary-side switches can be realized with a full load range. In Fig. 11(b), it can be found that the transformers pass energy from the primary-side to the secondary-side during a full duty cycle in the heavy mode.

Fig. 12 shows a loss evaluation for several main parts of the PSTB ZVZCS converter when V_{in}=200V and P_{o}=1.2kW. The loss evaluation is made depending on the measured waveforms and calculated by an oscilloscope. The efficiency in this situation is 96.6%, which is also the peak efficiency of the PSTB ZVZCS converter. Since all of the switches in the proposed converter can be soft-switched, the switching loss is little.

Fig. 12. Loss evaluation of the PSTB ZVZCS converter.

Measured efficiencies with different input voltages and output loads are given in Fig. 13. The peak efficiency of the PSTB ZVZCS converter reaches 96.6% under 1.2kW output power and 200V input voltage conditions. The on time duty cycle of the converter is 100% only in this situation. When the input voltage is larger than 200V or the output power is less than 1.2kW, the on time duty cycle of the converter is less than 100%.

Fig. 13. Experimental results of the efficiency of the PSTB ZVZCS converter with different input voltages and loads.

Table II shows a comparison of several phase-shift converters. In Table II, only the proposed converter can realize ZVS of all the primary-side switches and ZCS of all the secondary- side switches at the same time. Thus, the efficiency of the proposed converter is significantly improved when compared with the PSTB converter in [11]. Since switching loss is proportional to switching frequency, the peak efficiency of the proposed converter at different switching frequencies can be evaluated according to Fig. 12. Considering the switching frequency, the proposed topology has a higher efficiency than almost all of the other PS topologies. Since the energy in C_{oss} can be saved by realizing ZVS, realizing ZVS results in less switching loss than just realizing ZCS. As a result, the efficiency of the proposed converter is a little higher than that of ZVZCS FB [7] at the same switching frequency.

PS Converters |
ZVZCS FB |
PSDB |
PSTB |
The proposed converter |

Whether all the primary-side switches can be turned on with ZVS |
No |
Yes |
Yes |
Yes |

Whether all the secondary-side switches can be turned off with ZCS |
Yes |
No |
No |
Yes |

Switching Frequency(kHz) |
220 |
50 |
300 |
1000 |

Efficiency (%) |
96.8 |
95.3 |
90.5 |
96.6 |

Fig. 14 shows the dynamic response when the output load changes. In Fig. 14, I_{o} is the output current, V_{o} is the output voltage, and v_{gs2} is the gate-source voltage of S_{2}. As a result, v_{gs2} can show the on-off duty cycle of the converter. Fig. 14 shows dynamic waveforms when the output current changes from 50A to 25A. Before T_{0}, I_{o} is 50A, D is 100%, and V_{o} is 24V. From T_{0} to T_{1}, the load changes, I_{o} decreases from 50A to 25A, D is kept the same, and V_{o} changes from 24V to 27V. At T_{2}, the control system finds that V_{o} is higher than the target output voltage. The target output voltage is 24V. The difference between V_{o} and the target output voltage creates an error voltage. Then, D changes according to this error voltage by the PID. According to the analysis in Section Ⅲ, Part A, D should be less to make V_{o} decrease to the target output voltage. From T_{2} to T_{3}, D decreases from 100% to 55%. At T_{4}, V_{o} decreases back down to 24V. Then, the error voltage is zero, and D stays at 55%. As a result, it can be verified that the output voltage and power can be regulated by controlling the value of D.

Fig. 14. Dynamic response when the output load changes.

From Fig. 14, it can be seen that the frequency of the output voltage ripple depends on the on-off frequency of the converter, which is equal to D/6T. As a result, it may lead to audible noise and a low-frequency output voltage ripple when D is not large enough. According to Fig.6, D decreases with the output power. Thus, problems may occur at light loads. Since the on-off frequency of the converter increases with the switching frequency, these problems can be prevented by decreasing T. Due to the high switching frequency of the converter, the frequency of the output voltage in Fig. 14 is about 100kHz when D is equal to 55%. This is an acceptable result. Since the proposed converter is utilized for very high switching frequency applications, audible noise and low- frequency output ripple may not be big problems as long as the output power is not too low.

Ⅴ. CONCLUSIONS

This paper proposes a novel PSTB ZVZCS converter. All of the switches can be soft switched with a full load range, and there is no circulating current. Thus, the switching frequency and efficiency of the converter can be very high. Finally, experimental results are presented to verify the performance of this converter.

ACKNOWLEDGMENT

This work is supported by the Natural Science Foundation of Jiangsu Province (BK20171155) and the Key Research and Development Plan of Jiangsu (BE2018003-3).

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Junjie Zhu received his B.S. and M.S. degrees in Electronics Engineering from Southeast University, Nanjing, China, in 2011 and 2013, respectively. He is presently working towards his Ph.D. degree in the National ASIC System Engineering Research Center of Southeast University. His current research interests include high switching frequency and high power density converters.

Qinsong Qian received his Ph.D. degree in Electronics Engineering from Southeast University (SEU), Nanjing, China, in 2012. He joined the School of Electronic Science and Engineering, SEU, in 2012, where he is presently working as an Associate Professor. His current research interests include power converter topologies, simulations and digital control strategies.

Shengli Lu received his Ph.D. degree in Information and Physics from Nanjing University, Nanjing, China, in 1994. His current research interests include VLSI and application specific integrated circuits.

Weifeng Sun received his B.S., M.S. and Ph.D. degrees in Electronic Engineering from Southeast University (SEU), Nanjing, China, in 2000, 2003 and 2007, respectively. Since 2006, he has been with the School of Electronic Science and Engineering, Southeast University, where he is presently working as a Professor. His current research interests include new power device designs, power ICs, power device modeling and power systems.